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lis2dux12_reg.h
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lis2dux12_reg.h
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/*
******************************************************************************
* @file lis2dux12_reg.h
* @author Sensors Software Solution Team
* @brief This file contains all the functions prototypes for the
* lis2dux12_reg.c driver.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DUX12_REGS_H
#define LIS2DUX12_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include <stddef.h>
#include <math.h>
/** @addtogroup LIS2DUX12
* @{
*
*/
/** @defgroup Endianness definitions
* @{
*
*/
#ifndef DRV_BYTE_ORDER
#ifndef __BYTE_ORDER__
#define DRV_LITTLE_ENDIAN 1234
#define DRV_BIG_ENDIAN 4321
/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
* by uncommenting the define which fits your platform endianness
*/
//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
#else /* defined __BYTE_ORDER__ */
#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
#define DRV_BYTE_ORDER __BYTE_ORDER__
#endif /* __BYTE_ORDER__*/
#endif /* DRV_BYTE_ORDER */
/**
* @}
*
*/
/** @defgroup STMicroelectronics sensors common types
* @{
*
*/
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
uint8_t bit3 : 1;
uint8_t bit4 : 1;
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bit7 : 1;
uint8_t bit6 : 1;
uint8_t bit5 : 1;
uint8_t bit4 : 1;
uint8_t bit3 : 1;
uint8_t bit2 : 1;
uint8_t bit1 : 1;
uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
#define PROPERTY_ENABLE (1U)
/** @addtogroup Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
typedef int32_t (*stmdev_write_ptr)(void *ctx, uint8_t reg, const uint8_t *data, uint16_t len);
typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, uint8_t *data, uint16_t len);
typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
typedef struct
{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
/** Component optional fields **/
stmdev_mdelay_ptr mdelay;
/** Customizable optional pointer **/
void *handle;
} stmdev_ctx_t;
/**
* @}
*
*/
#endif /* MEMS_SHARED_TYPES */
#ifndef MEMS_UCF_SHARED_TYPES
#define MEMS_UCF_SHARED_TYPES
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
* You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
* @{
*
*/
typedef struct
{
uint8_t address;
uint8_t data;
} ucf_line_t;
/**
* @}
*
*/
#endif /* MEMS_UCF_SHARED_TYPES */
/**
* @}
*
*/
/** @defgroup LIS2DUX12_Infos
* @{
*
*/
/** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/
#define LIS2DUX12_I2C_ADD_L 0x31U
#define LIS2DUX12_I2C_ADD_H 0x33U
/** Device Identification (Who am I) **/
#define LIS2DUX12_ID 0x47U
/**
* @}
*
*/
#define LIS2DUX12_EXT_CLK_CFG 0x08U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 7;
uint8_t ext_clk_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ext_clk_en : 1;
uint8_t not_used0 : 7;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_ext_clk_cfg_t;
#define LIS2DUX12_PIN_CTRL 0x0CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t pp_od : 1;
uint8_t cs_pu_dis : 1;
uint8_t h_lactive : 1;
uint8_t pd_dis_int1 : 1;
uint8_t pd_dis_int2 : 1;
uint8_t sda_pu_en : 1;
uint8_t sdo_pu_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t sdo_pu_en : 1;
uint8_t sda_pu_en : 1;
uint8_t pd_dis_int2 : 1;
uint8_t pd_dis_int1 : 1;
uint8_t h_lactive : 1;
uint8_t cs_pu_dis : 1;
uint8_t pp_od : 1;
uint8_t sim : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_pin_ctrl_t;
#define LIS2DUX12_WAKE_UP_DUR_EXT 0x0EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 4;
uint8_t wu_dur_extended : 1;
uint8_t not_used1 : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 3;
uint8_t wu_dur_extended : 1;
uint8_t not_used0 : 4;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_wake_up_dur_ext_t;
#define LIS2DUX12_WHO_AM_I 0x0FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t id : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t id : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_who_am_i_t;
#define LIS2DUX12_CTRL1 0x10U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wu_z_en : 1;
uint8_t wu_y_en : 1;
uint8_t wu_x_en : 1;
uint8_t drdy_pulsed : 1;
uint8_t if_add_inc : 1;
uint8_t sw_reset : 1;
uint8_t int1_on_res : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t int1_on_res : 1;
uint8_t sw_reset : 1;
uint8_t if_add_inc : 1;
uint8_t drdy_pulsed : 1;
uint8_t wu_x_en : 1;
uint8_t wu_y_en : 1;
uint8_t wu_z_en : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_ctrl1_t;
#define LIS2DUX12_CTRL2 0x11U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 3;
uint8_t int1_drdy : 1;
uint8_t int1_fifo_ovr : 1;
uint8_t int1_fifo_th : 1;
uint8_t int1_fifo_full : 1;
uint8_t int1_boot : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int1_boot : 1;
uint8_t int1_fifo_full : 1;
uint8_t int1_fifo_th : 1;
uint8_t int1_fifo_ovr : 1;
uint8_t int1_drdy : 1;
uint8_t not_used0 : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_ctrl2_t;
#define LIS2DUX12_CTRL3 0x12U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_sign_x : 1;
uint8_t st_sign_y : 1;
uint8_t hp_en : 1;
uint8_t int2_drdy : 1;
uint8_t int2_fifo_ovr : 1;
uint8_t int2_fifo_th : 1;
uint8_t int2_fifo_full : 1;
uint8_t int2_boot : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int2_boot : 1;
uint8_t int2_fifo_full : 1;
uint8_t int2_fifo_th : 1;
uint8_t int2_fifo_ovr : 1;
uint8_t int2_drdy : 1;
uint8_t hp_en : 1;
uint8_t st_sign_y : 1;
uint8_t st_sign_x : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_ctrl3_t;
#define LIS2DUX12_CTRL4 0x13U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t boot : 1;
uint8_t soc : 1;
uint8_t not_used0 : 1;
uint8_t fifo_en : 1;
uint8_t emb_func_en : 1;
uint8_t bdu : 1;
uint8_t inact_odr : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t inact_odr : 2;
uint8_t bdu : 1;
uint8_t emb_func_en : 1;
uint8_t fifo_en : 1;
uint8_t not_used0 : 1;
uint8_t soc : 1;
uint8_t boot : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_ctrl4_t;
#define LIS2DUX12_CTRL5 0x14U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs : 2;
uint8_t bw : 2;
uint8_t odr : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t odr : 4;
uint8_t bw : 2;
uint8_t fs : 2;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_ctrl5_t;
#define LIS2DUX12_FIFO_CTRL 0x15U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t stop_on_fth : 1;
uint8_t not_used0 : 2;
uint8_t fifo_depth : 1;
uint8_t cfg_chg_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t cfg_chg_en : 1;
uint8_t fifo_depth : 1;
uint8_t not_used0 : 2;
uint8_t stop_on_fth : 1;
uint8_t fifo_mode : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_ctrl_t;
#define LIS2DUX12_FIFO_WTM 0x16U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 7;
uint8_t xl_only_fifo : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t xl_only_fifo : 1;
uint8_t fth : 7;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_wtm_t;
#define LIS2DUX12_INTERRUPT_CFG 0x17U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t interrupts_enable : 1;
uint8_t lir : 1;
uint8_t dis_rst_lir_all_int : 1;
uint8_t sleep_status_on_int : 1;
uint8_t not_used0 : 1;
uint8_t wake_ths_w : 1;
uint8_t not_used1 : 1;
uint8_t timestamp_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp_en : 1;
uint8_t not_used1 : 1;
uint8_t wake_ths_w : 1;
uint8_t not_used0 : 1;
uint8_t sleep_status_on_int : 1;
uint8_t dis_rst_lir_all_int : 1;
uint8_t lir : 1;
uint8_t interrupts_enable : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_interrupt_cfg_t;
#define LIS2DUX12_SIXD 0x18U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 5;
uint8_t d6d_ths : 2;
uint8_t d4d_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t d4d_en : 1;
uint8_t d6d_ths : 2;
uint8_t not_used0 : 5;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_sixd_t;
#define LIS2DUX12_WAKE_UP_THS 0x1CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t sleep_on : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t sleep_on : 1;
uint8_t wk_ths : 6;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_wake_up_ths_t;
#define LIS2DUX12_WAKE_UP_DUR 0x1DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t st_sign_z : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ff_dur : 1;
uint8_t wake_dur : 2;
uint8_t st_sign_z : 1;
uint8_t sleep_dur : 4;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_wake_up_dur_t;
#define LIS2DUX12_FREE_FALL 0x1EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ff_dur : 5;
uint8_t ff_ths : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_free_fall_t;
#define LIS2DUX12_MD1_CFG 0x1FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_emb_func : 1;
uint8_t int1_timestamp : 1;
uint8_t int1_6d : 1;
uint8_t int1_tap : 1;
uint8_t int1_ff : 1;
uint8_t int1_wu : 1;
uint8_t not_used0 : 1;
uint8_t int1_sleep_change : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int1_sleep_change : 1;
uint8_t not_used0 : 1;
uint8_t int1_wu : 1;
uint8_t int1_ff : 1;
uint8_t int1_tap : 1;
uint8_t int1_6d : 1;
uint8_t int1_timestamp : 1;
uint8_t int1_emb_func : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_md1_cfg_t;
#define LIS2DUX12_MD2_CFG 0x20U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_emb_func : 1;
uint8_t int2_timestamp : 1;
uint8_t int2_6d : 1;
uint8_t int2_tap : 1;
uint8_t int2_ff : 1;
uint8_t int2_wu : 1;
uint8_t not_used0 : 1;
uint8_t int2_sleep_change : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int2_sleep_change : 1;
uint8_t not_used0 : 1;
uint8_t int2_wu : 1;
uint8_t int2_ff : 1;
uint8_t int2_tap : 1;
uint8_t int2_6d : 1;
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_md2_cfg_t;
#define LIS2DUX12_WAKE_UP_SRC 0x21U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
uint8_t wu_ia : 1;
uint8_t sleep_state : 1;
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t sleep_change_ia : 1;
uint8_t ff_ia : 1;
uint8_t sleep_state : 1;
uint8_t wu_ia : 1;
uint8_t x_wu : 1;
uint8_t y_wu : 1;
uint8_t z_wu : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_wake_up_src_t;
#define LIS2DUX12_TAP_SRC 0x22U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 4;
uint8_t triple_tap_ia : 1;
uint8_t double_tap_ia : 1;
uint8_t single_tap_ia : 1;
uint8_t tap_ia : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t tap_ia : 1;
uint8_t single_tap_ia : 1;
uint8_t double_tap_ia : 1;
uint8_t triple_tap_ia : 1;
uint8_t not_used0 : 4;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_tap_src_t;
#define LIS2DUX12_SIXD_SRC 0x23U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
uint8_t yh : 1;
uint8_t zl : 1;
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t d6d_ia : 1;
uint8_t zh : 1;
uint8_t zl : 1;
uint8_t yh : 1;
uint8_t yl : 1;
uint8_t xh : 1;
uint8_t xl : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_sixd_src_t;
#define LIS2DUX12_ALL_INT_SRC 0x24U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia_all : 1;
uint8_t wu_ia_all : 1;
uint8_t single_tap_all : 1;
uint8_t double_tap_all : 1;
uint8_t triple_tap_all : 1;
uint8_t d6d_ia_all : 1;
uint8_t sleep_change_ia_all : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t sleep_change_ia_all : 1;
uint8_t d6d_ia_all : 1;
uint8_t triple_tap_all : 1;
uint8_t double_tap_all : 1;
uint8_t single_tap_all : 1;
uint8_t wu_ia_all : 1;
uint8_t ff_ia_all : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_all_int_src_t;
#define LIS2DUX12_STATUS 0x25U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t not_used0 : 4;
uint8_t int_global : 1;
uint8_t not_used1 : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 2;
uint8_t int_global : 1;
uint8_t not_used0 : 4;
uint8_t drdy : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_status_register_t;
#define LIS2DUX12_FIFO_STATUS1 0x26U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 6;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_wtm_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t not_used0 : 6;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_status1_t;
#define LIS2DUX12_FIFO_STATUS2 0x27U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fss : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fss : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_status2_t;
#define LIS2DUX12_OUT_X_L 0x28U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outx : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outx : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_x_l_t;
#define LIS2DUX12_OUT_X_H 0x29U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outx : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outx : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_x_h_t;
#define LIS2DUX12_OUT_Y_L 0x2AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outy : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outy : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_y_l_t;
#define LIS2DUX12_OUT_Y_H 0x2BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outy : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outy : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_y_h_t;
#define LIS2DUX12_OUT_Z_L 0x2CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outz : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outz : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_z_l_t;
#define LIS2DUX12_OUT_Z_H 0x2DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outz : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outz : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_z_h_t;
#define LIS2DUX12_OUT_T_L 0x2EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outt : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outt : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_t_l_t;
#define LIS2DUX12_OUT_T_H 0x2FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outt : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outt : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_out_t_h_t;
#define LIS2DUX12_SELF_TEST 0x32U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t t_dis : 1;
uint8_t not_used0 : 3;
uint8_t st : 2;
uint8_t not_used1 : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 2;
uint8_t st : 2;
uint8_t not_used0 : 3;
uint8_t t_dis : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_self_test_t;
#define LIS2DUX12_I3C_IF_CTRL 0x33U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bus_act_sel : 2;
uint8_t not_used0 : 3;
uint8_t asf_on : 1;
uint8_t dis_drstdaa : 1;
uint8_t not_used1 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 1;
uint8_t dis_drstdaa : 1;
uint8_t asf_on : 1;
uint8_t not_used0 : 3;
uint8_t bus_act_sel : 2;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_i3c_if_ctrl_t;
#define LIS2DUX12_EMB_FUNC_STATUS_MAINPAGE 0x34U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used1 : 1;
uint8_t is_fsm_lc : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t is_fsm_lc : 1;
uint8_t not_used1 : 1;
uint8_t is_sigmot : 1;
uint8_t is_tilt : 1;
uint8_t is_step_det : 1;
uint8_t not_used0 : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_emb_func_status_mainpage_t;
#define LIS2DUX12_FSM_STATUS_MAINPAGE 0x35U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
uint8_t is_fsm4 : 1;
uint8_t is_fsm5 : 1;
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t is_fsm8 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm6 : 1;
uint8_t is_fsm5 : 1;
uint8_t is_fsm4 : 1;
uint8_t is_fsm3 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm1 : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fsm_status_mainpage_t;
#define LIS2DUX12_MLC_STATUS_MAINPAGE 0x36U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
uint8_t is_mlc3 : 1;
uint8_t is_mlc4 : 1;
uint8_t not_used0 : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 4;
uint8_t is_mlc4 : 1;
uint8_t is_mlc3 : 1;
uint8_t is_mlc2 : 1;
uint8_t is_mlc1 : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_mlc_status_mainpage_t;
#define LIS2DUX12_SLEEP 0x3DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t deep_pd : 1;
uint8_t not_used0 : 7;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 7;
uint8_t deep_pd : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_sleep_t;
#define LIS2DUX12_EN_DEVICE_CONFIG 0x3EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t soft_pd : 1;
uint8_t not_used0 : 7;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 7;
uint8_t soft_pd : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_en_device_config_t;
#define LIS2DUX12_FUNC_CFG_ACCESS 0x3FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fsm_wr_ctrl_en : 1;
uint8_t not_used0 : 6;
uint8_t emb_func_reg_access : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t emb_func_reg_access : 1;
uint8_t not_used0 : 6;
uint8_t fsm_wr_ctrl_en : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_func_cfg_access_t;
#define LIS2DUX12_FIFO_DATA_OUT_TAG 0x40U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 3;
uint8_t tag_sensor : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t tag_sensor : 5;
uint8_t not_used0 : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_tag_t;
#define LIS2DUX12_FIFO_DATA_OUT_X_L 0x41U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_data_out : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_data_out : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_x_l_t;
#define LIS2DUX12_FIFO_DATA_OUT_X_H 0x42U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_data_out : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_data_out : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_x_h_t;
#define LIS2DUX12_FIFO_DATA_OUT_Y_L 0x43U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_data_out : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_data_out : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_y_l_t;
#define LIS2DUX12_FIFO_DATA_OUT_Y_H 0x44U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_data_out : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_data_out : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_y_h_t;
#define LIS2DUX12_FIFO_DATA_OUT_Z_L 0x45U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_data_out : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_data_out : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_z_l_t;
#define LIS2DUX12_FIFO_DATA_OUT_Z_H 0x46U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_data_out : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_data_out : 8;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_data_out_z_h_t;
#define LIS2DUX12_FIFO_BATCH_DEC 0x47U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 3;
uint8_t dec_ts_batch : 2;
uint8_t not_used0 : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 3;
uint8_t dec_ts_batch : 2;
uint8_t bdr_xl : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_fifo_batch_dec_t;
#define LIS2DUX12_TAP_CFG0 0x6FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 1;
uint8_t invert_t : 5;
uint8_t axis : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t axis : 2;
uint8_t invert_t : 5;
uint8_t not_used0 : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_tap_cfg0_t;
#define LIS2DUX12_TAP_CFG1 0x70U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t post_still_t : 4;
uint8_t pre_still_ths : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t pre_still_ths : 4;
uint8_t post_still_t : 4;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_tap_cfg1_t;
#define LIS2DUX12_TAP_CFG2 0x71U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wait_t : 6;
uint8_t post_still_t : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t post_still_t : 2;
uint8_t wait_t : 6;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_tap_cfg2_t;
#define LIS2DUX12_TAP_CFG3 0x72U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t latency_t : 4;
uint8_t post_still_ths : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t post_still_ths : 4;
uint8_t latency_t : 4;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_tap_cfg3_t;
#define LIS2DUX12_TAP_CFG4 0x73U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t peak_ths : 6;
uint8_t not_used0 : 1;
uint8_t wait_end_latency : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t wait_end_latency : 1;
uint8_t not_used0 : 1;
uint8_t peak_ths : 6;
#endif /* DRV_BYTE_ORDER */
} lis2dux12_tap_cfg4_t;
#define LIS2DUX12_TAP_CFG5 0x74U
typedef struct