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Combined group for DDR and HBM measurements
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| Original file line number | Diff line number | Diff line change |
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| SHORT Memory bandwidth in MBytes/s for DDR and HBM | ||
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| EVENTSET | ||
| FIXC0 INSTR_RETIRED_ANY | ||
| FIXC1 CPU_CLK_UNHALTED_CORE | ||
| FIXC2 CPU_CLK_UNHALTED_REF | ||
| FIXC3 TOPDOWN_SLOTS | ||
| MBOX0C0 CAS_COUNT_RD | ||
| MBOX0C1 CAS_COUNT_WR | ||
| MBOX1C0 CAS_COUNT_RD | ||
| MBOX1C1 CAS_COUNT_WR | ||
| MBOX2C0 CAS_COUNT_RD | ||
| MBOX2C1 CAS_COUNT_WR | ||
| MBOX3C0 CAS_COUNT_RD | ||
| MBOX3C1 CAS_COUNT_WR | ||
| MBOX4C0 CAS_COUNT_RD | ||
| MBOX4C1 CAS_COUNT_WR | ||
| MBOX5C0 CAS_COUNT_RD | ||
| MBOX5C1 CAS_COUNT_WR | ||
| MBOX6C0 CAS_COUNT_RD | ||
| MBOX6C1 CAS_COUNT_WR | ||
| MBOX7C0 CAS_COUNT_RD | ||
| MBOX7C1 CAS_COUNT_WR | ||
| MBOX8C0 CAS_COUNT_RD | ||
| MBOX8C1 CAS_COUNT_WR | ||
| MBOX9C0 CAS_COUNT_RD | ||
| MBOX9C1 CAS_COUNT_WR | ||
| MBOX10C0 CAS_COUNT_RD | ||
| MBOX10C1 CAS_COUNT_WR | ||
| MBOX11C0 CAS_COUNT_RD | ||
| MBOX11C1 CAS_COUNT_WR | ||
| MBOX12C0 CAS_COUNT_RD | ||
| MBOX12C1 CAS_COUNT_WR | ||
| MBOX13C0 CAS_COUNT_RD | ||
| MBOX13C1 CAS_COUNT_WR | ||
| MBOX14C0 CAS_COUNT_RD | ||
| MBOX14C1 CAS_COUNT_WR | ||
| MBOX15C0 CAS_COUNT_RD | ||
| MBOX15C1 CAS_COUNT_WR | ||
| HBM0C0 CAS_COUNT_RD | ||
| HBM0C1 CAS_COUNT_WR | ||
| HBM1C0 CAS_COUNT_RD | ||
| HBM1C1 CAS_COUNT_WR | ||
| HBM2C0 CAS_COUNT_RD | ||
| HBM2C1 CAS_COUNT_WR | ||
| HBM3C0 CAS_COUNT_RD | ||
| HBM3C1 CAS_COUNT_WR | ||
| HBM4C0 CAS_COUNT_RD | ||
| HBM4C1 CAS_COUNT_WR | ||
| HBM5C0 CAS_COUNT_RD | ||
| HBM5C1 CAS_COUNT_WR | ||
| HBM6C0 CAS_COUNT_RD | ||
| HBM6C1 CAS_COUNT_WR | ||
| HBM7C0 CAS_COUNT_RD | ||
| HBM7C1 CAS_COUNT_WR | ||
| HBM8C0 CAS_COUNT_RD | ||
| HBM8C1 CAS_COUNT_WR | ||
| HBM9C0 CAS_COUNT_RD | ||
| HBM9C1 CAS_COUNT_WR | ||
| HBM10C0 CAS_COUNT_RD | ||
| HBM10C1 CAS_COUNT_WR | ||
| HBM11C0 CAS_COUNT_RD | ||
| HBM11C1 CAS_COUNT_WR | ||
| HBM12C0 CAS_COUNT_RD | ||
| HBM12C1 CAS_COUNT_WR | ||
| HBM13C0 CAS_COUNT_RD | ||
| HBM13C1 CAS_COUNT_WR | ||
| HBM14C0 CAS_COUNT_RD | ||
| HBM14C1 CAS_COUNT_WR | ||
| HBM15C0 CAS_COUNT_RD | ||
| HBM15C1 CAS_COUNT_WR | ||
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| METRICS | ||
| Runtime (RDTSC) [s] time | ||
| Runtime unhalted [s] FIXC1*inverseClock | ||
| Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock | ||
| CPI FIXC1/FIXC0 | ||
| DDR read bandwidth [MBytes/s] 1.0E-06*(MBOX0C0+MBOX1C0+MBOX2C0+MBOX3C0+MBOX4C0+MBOX5C0+MBOX6C0+MBOX7C0+MBOX8C0+MBOX9C0+MBOX10C0+MBOX11C0+MBOX12C0+MBOX13C0+MBOX14C0+MBOX15C0)*64.0/time | ||
| DDR read data volume [GBytes] 1.0E-09*(MBOX0C0+MBOX1C0+MBOX2C0+MBOX3C0+MBOX4C0+MBOX5C0+MBOX6C0+MBOX7C0+MBOX8C0+MBOX9C0+MBOX10C0+MBOX11C0+MBOX12C0+MBOX13C0+MBOX14C0+MBOX15C0)*64.0 | ||
| DDR write bandwidth [MBytes/s] 1.0E-06*(MBOX0C1+MBOX1C1+MBOX2C1+MBOX3C1+MBOX4C1+MBOX5C1+MBOX6C1+MBOX7C1+MBOX8C1+MBOX9C1+MBOX10C1+MBOX11C1+MBOX12C1+MBOX13C1+MBOX14C1+MBOX15C1)*64.0/time | ||
| DDR write data volume [GBytes] 1.0E-09*(MBOX0C1+MBOX1C1+MBOX2C1+MBOX3C1+MBOX4C1+MBOX5C1+MBOX6C1+MBOX7C1+MBOX8C1+MBOX9C1+MBOX10C1+MBOX11C1+MBOX12C1+MBOX13C1+MBOX14C1+MBOX15C1)*64.0 | ||
| DDR bandwidth [MBytes/s] 1.0E-06*(MBOX0C0+MBOX1C0+MBOX2C0+MBOX3C0+MBOX4C0+MBOX5C0+MBOX6C0+MBOX7C0+MBOX8C0+MBOX9C0+MBOX10C0+MBOX11C0+MBOX12C0+MBOX13C0+MBOX14C0+MBOX15C0+MBOX0C1+MBOX1C1+MBOX2C1+MBOX3C1+MBOX4C1+MBOX5C1+MBOX6C1+MBOX7C1+MBOX8C1+MBOX9C1+MBOX10C1+MBOX11C1+MBOX12C1+MBOX13C1+MBOX14C1+MBOX15C1)*64.0/time | ||
| DDR data volume [GBytes] 1.0E-09*(MBOX0C0+MBOX1C0+MBOX2C0+MBOX3C0+MBOX4C0+MBOX5C0+MBOX6C0+MBOX7C0+MBOX8C0+MBOX9C0+MBOX10C0+MBOX11C0+MBOX12C0+MBOX13C0+MBOX14C0+MBOX15C0+MBOX0C1+MBOX1C1+MBOX2C1+MBOX3C1+MBOX4C1+MBOX5C1+MBOX6C1+MBOX7C1+MBOX8C1+MBOX9C1+MBOX10C1+MBOX11C1+MBOX12C1+MBOX13C1+MBOX14C1+MBOX15C1)*64.0 | ||
| HBM read bandwidth [MBytes/s] 1.0E-06*(HBM0C0+HBM1C0+HBM2C0+HBM3C0+HBM4C0+HBM5C0+HBM6C0+HBM7C0+HBM8C0+HBM9C0+HBM10C0+HBM11C0+HBM12C0+HBM13C0+HBM14C0+HBM15C0)*64.0/time | ||
| HBM read data volume [GBytes] 1.0E-09*(HBM0C0+HBM1C0+HBM2C0+HBM3C0+HBM4C0+HBM5C0+HBM6C0+HBM7C0+HBM8C0+HBM9C0+HBM10C0+HBM11C0+HBM12C0+HBM13C0+HBM14C0+HBM15C0)*64.0 | ||
| HBM write bandwidth [MBytes/s] 1.0E-06*(HBM0C1+HBM1C1+HBM2C1+HBM3C1+HBM4C1+HBM5C1+HBM6C1+HBM7C1+HBM8C1+HBM9C1+HBM10C1+HBM11C1+HBM12C1+HBM13C1+HBM14C1+HBM15C1)*64.0/time | ||
| HBM write data volume [GBytes] 1.0E-09*(HBM0C1+HBM1C1+HBM2C1+HBM3C1+HBM4C1+HBM5C1+HBM6C1+HBM7C1+HBM8C1+HBM9C1+HBM10C1+HBM11C1+HBM12C1+HBM13C1+HBM14C1+HBM15C1)*64.0 | ||
| HBM bandwidth [MBytes/s] 1.0E-06*(HBM0C0+HBM1C0+HBM2C0+HBM3C0+HBM4C0+HBM5C0+HBM6C0+HBM7C0+HBM8C0+HBM9C0+HBM10C0+HBM11C0+HBM12C0+HBM13C0+HBM14C0+HBM15C0+HBM0C1+HBM1C1+HBM2C1+HBM3C1+HBM4C1+HBM5C1+HBM6C1+HBM7C1+HBM8C1+HBM9C1+HBM10C1+HBM11C1+HBM12C1+HBM13C1+HBM14C1+HBM15C1)*64.0/time | ||
| HBM data volume [GBytes] 1.0E-09*(HBM0C0+HBM1C0+HBM2C0+HBM3C0+HBM4C0+HBM5C0+HBM6C0+HBM7C0+HBM8C0+HBM9C0+HBM10C0+HBM11C0+HBM12C0+HBM13C0+HBM14C0+HBM15C0+HBM0C1+HBM1C1+HBM2C1+HBM3C1+HBM4C1+HBM5C1+HBM6C1+HBM7C1+HBM8C1+HBM9C1+HBM10C1+HBM11C1+HBM12C1+HBM13C1+HBM14C1+HBM15C1)*64.0 | ||
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| LONG | ||
| Formulas: | ||
| DDR read bandwidth [MBytes/s] = 1.0E-06*(SUM(MBOX*C0))*64.0/runtime | ||
| DDR read data volume [GBytes] = 1.0E-09*(SUM(MBOX*C0))*64.0 | ||
| DDR write bandwidth [MBytes/s] = 1.0E-06*(SUM(MBOX*C1))*64.0/runtime | ||
| DDR write data volume [GBytes] = 1.0E-09*(SUM(MBOX*C1))*64.0 | ||
| DDR bandwidth [MBytes/s] = 1.0E-06*(SUM(MBOX*C0)+SUM(MBOX*C1))*64.0/runtime | ||
| DDR data volume [GBytes] = 1.0E-09*(SUM(MBOX*C0)+SUM(MBOX*C1))*64.0 | ||
| HBM read bandwidth [MBytes/s] = 1.0E-06*(SUM(HBM*C0))*64.0/runtime | ||
| HBM read data volume [GBytes] = 1.0E-09*(SUM(HBM*C0))*64.0 | ||
| HBM write bandwidth [MBytes/s] = 1.0E-06*(SUM(HBM*C1))*64.0/runtime | ||
| HBM write data volume [GBytes] = 1.0E-09*(SUM(HBM*C1))*64.0 | ||
| HBM bandwidth [MBytes/s] = 1.0E-06*(SUM(HBM*C0)+SUM(HBM*C1))*64.0/runtime | ||
| HBM data volume [GBytes] = 1.0E-09*(SUM(HBM*C0)+SUM(HBM*C1))*64.0 | ||
| -- | ||
| Profiling group to measure memory bandwidth drawn by all cores of a socket for DDR | ||
| as well as HBM. Since this group is based on Uncore events it is only possible to measure on a | ||
| per socket base. Some of the counters may not be available on your system. | ||
| Also outputs total data volume transferred from both memory technologies. | ||
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