temporary: pull in pr stnolting#677

[OCD] add option to select DM legacy mode [stnolting#677](stnolting#677)
NikLeberg · Sep 3, 2023 · 1d3c7ae · 1d3c7ae
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 25.08.2023 | 1.8.8.4 | add new generic to downgrade on-chip debugger's debug module back to spec. version 0.13 (`DM_LEGACY_MODE` generic); [#677](https://github.com/stnolting/neorv32/pull/677) |
 | 23.08.2023 | 1.8.8.3 | :test_tube: add experimental `Smcntrpmf` ISA extension (counter privilege mode filtering; spec. is frozen but not yet ratified); remove unused `menvcfg` CSRs; [#676](https://github.com/stnolting/neorv32/pull/676) |
 | 19.08.2023 | 1.8.8.2 | :warning: constrain `mtval` CSR; add support for `mtinst` CSR (trap instruction); [#674](https://github.com/stnolting/neorv32/pull/674) |
 | 19.08.2023 | 1.8.8.1 | :test_tube: update RTE to support easy emulation of instructions; add example program to showcase how to emulate unaligned memory accesses; [#673](https://github.com/stnolting/neorv32/pull/673) |

diff --git a/docs/datasheet/on_chip_debugger.adoc b/docs/datasheet/on_chip_debugger.adoc
diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -200,11 +200,13 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 |=======================
 | Name | Type | Default | Description
 4+^| **General**
-| `CLOCK_FREQUENCY`       | natural   | -          | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
-| `INT_BOOTLOADER_EN`     | boolean   | false      | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image.
-| `HART_ID`               | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSRs).
-| `VENDOR_ID`             | suv(31:0) | 0x00000000 | JEDEC ID (passed to <<_mvendorid>> CSRs).
-| `ON_CHIP_DEBUGGER_EN`   | boolean   | false      | Implement the on-chip debugger <<_on_chip_debugger_ocd>> and the CPU debug mode.
+| `CLOCK_FREQUENCY`   | natural   | -          | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
+| `INT_BOOTLOADER_EN` | boolean   | false      | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image.
+| `HART_ID`           | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSRs).
+| `VENDOR_ID`         | suv(31:0) | 0x00000000 | JEDEC ID (passed to <<_mvendorid>> CSRs).
+4+^| **<<_on_chip_debugger_ocd>>**
+| `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode.
+| `DM_LEGACY_MODE`      | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
 4+^| **CPU <<_instruction_sets_and_extensions>>**
 | `CPU_EXTENSION_RISCV_A`        | boolean | false | Enable <<_a_isa_extension>> (atomic memory accesses).
 | `CPU_EXTENSION_RISCV_B`        | boolean | false | Enable <<_b_isa_extension>> (bit-manipulation).

diff --git a/rtl/core/neorv32_debug_dm.vhd b/rtl/core/neorv32_debug_dm.vhd
diff --git a/rtl/core/neorv32_debug_dtm.vhd b/rtl/core/neorv32_debug_dtm.vhd
diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -56,7 +56,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080803"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080804"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!
 
@@ -190,6 +190,25 @@ package neorv32_package is
     err  => '0'
   );
 
+  -- Debug Module Interface -----------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  -- request --
+  type dmi_req_t is record
+    addr : std_ulogic_vector(06 downto 0);
+    op   : std_ulogic_vector(01 downto 0);
+    data : std_ulogic_vector(31 downto 0);
+  end record;
+
+  -- request operation --
+  constant dmi_req_nop_c : std_ulogic_vector(1 downto 0) := "00"; -- no operation
+  constant dmi_req_rd_c  : std_ulogic_vector(1 downto 0) := "01"; -- read access
+  constant dmi_req_wr_c  : std_ulogic_vector(1 downto 0) := "10"; -- write access
+
+  -- response --
+  type dmi_rsp_t is record
+    data : std_ulogic_vector(31 downto 0);
+    ack  : std_ulogic;
+  end record;
 
 -- ****************************************************************************************************************************
 -- RISC-V ISA Definitions
@@ -732,6 +751,7 @@ package neorv32_package is
       INT_BOOTLOADER_EN            : boolean := false;  -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
       -- On-Chip Debugger (OCD) --
       ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
+      DM_LEGACY_MODE               : boolean := false;  -- debug module spec version: false = v1.0, true = v0.13
       -- RISC-V CPU Extensions --
       CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic memory operations extension?
       CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit-manipulation extension?

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -54,6 +54,7 @@ entity neorv32_top is
 
     -- On-Chip Debugger (OCD) --
     ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
+    DM_LEGACY_MODE               : boolean := false;  -- debug module spec version: false = v1.0, true = v0.13
 
     -- RISC-V CPU Extensions --
     CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic memory operations extension?
@@ -288,18 +289,8 @@ architecture neorv32_top_rtl of neorv32_top is
   signal d_fence   : std_ulogic; -- data fence
 
   -- debug module interface (DMI) --
-  type dmi_t is record
-    req_valid   : std_ulogic;
-    req_ready   : std_ulogic; -- DMI is allowed to make new requests when set
-    req_address : std_ulogic_vector(05 downto 0);
-    req_op      : std_ulogic_vector(01 downto 0);
-    req_data    : std_ulogic_vector(31 downto 0);
-    rsp_valid   : std_ulogic; -- response valid when set
-    rsp_ready   : std_ulogic; -- ready to receive respond
-    rsp_data    : std_ulogic_vector(31 downto 0);
-    rsp_op      : std_ulogic_vector(01 downto 0);
-  end record;
-  signal dmi : dmi_t;
+  signal dmi_req : dmi_req_t;
+  signal dmi_rsp : dmi_rsp_t;
 
   -- debug core interface (DCI) --
   signal dci_ndmrstn, dci_halt_req : std_ulogic;
@@ -1531,53 +1522,40 @@ begin
     )
     port map (
       -- global control --
-      clk_i             => clk_i,
-      rstn_i            => rstn_ext,
+      clk_i        => clk_i,
+      rstn_i       => rstn_ext,
       -- jtag connection --
-      jtag_trst_i       => jtag_trst_i,
-      jtag_tck_i        => jtag_tck_i,
-      jtag_tdi_i        => jtag_tdi_i,
-      jtag_tdo_o        => jtag_tdo_o,
-      jtag_tms_i        => jtag_tms_i,
+      jtag_trst_i  => jtag_trst_i,
+      jtag_tck_i   => jtag_tck_i,
+      jtag_tdi_i   => jtag_tdi_i,
+      jtag_tdo_o   => jtag_tdo_o,
+      jtag_tms_i   => jtag_tms_i,
       -- debug module interface (DMI) --
-      dmi_req_valid_o   => dmi.req_valid,
-      dmi_req_ready_i   => dmi.req_ready,
-      dmi_req_address_o => dmi.req_address,
-      dmi_req_data_o    => dmi.req_data,
-      dmi_req_op_o      => dmi.req_op,
-      dmi_rsp_valid_i   => dmi.rsp_valid,
-      dmi_rsp_ready_o   => dmi.rsp_ready,
-      dmi_rsp_data_i    => dmi.rsp_data,
-      dmi_rsp_op_i      => dmi.rsp_op
+      dmi_req_o    => dmi_req,
+      dmi_rsp_i    => dmi_rsp
     );
 
     -- On-Chip Debugger - Debug Module (DM) ---------------------------------------------------
     -- -------------------------------------------------------------------------------------------
     neorv32_debug_dm_inst: entity neorv32.neorv32_debug_dm
     generic map (
-      CPU_BASE_ADDR => base_io_dm_c
+      CPU_BASE_ADDR => base_io_dm_c,
+      LEGACY_MODE   => DM_LEGACY_MODE
     )
     port map (
       -- global control --
-      clk_i             => clk_i,
-      rstn_i            => rstn_ext,
-      cpu_debug_i       => cpu_debug,
+      clk_i          => clk_i,
+      rstn_i         => rstn_ext,
+      cpu_debug_i    => cpu_debug,
       -- debug module interface (DMI) --
-      dmi_req_valid_i   => dmi.req_valid,
-      dmi_req_ready_o   => dmi.req_ready,
-      dmi_req_address_i => dmi.req_address,
-      dmi_req_data_i    => dmi.req_data,
-      dmi_req_op_i      => dmi.req_op,
-      dmi_rsp_valid_o   => dmi.rsp_valid,
-      dmi_rsp_ready_i   => dmi.rsp_ready,
-      dmi_rsp_data_o    => dmi.rsp_data,
-      dmi_rsp_op_o      => dmi.rsp_op,
+      dmi_req_i      => dmi_req,
+      dmi_rsp_o      => dmi_rsp,
       -- CPU bus access --
-      bus_req_i         => io_dev_req(IODEV_OCD),
-      bus_rsp_o         => io_dev_rsp(IODEV_OCD),
+      bus_req_i      => io_dev_req(IODEV_OCD),
+      bus_rsp_o      => io_dev_rsp(IODEV_OCD),
       -- CPU control --
-      cpu_ndmrstn_o     => dci_ndmrstn,
-      cpu_halt_req_o    => dci_halt_req
+      cpu_ndmrstn_o  => dci_ndmrstn,
+      cpu_halt_req_o => dci_halt_req
     );
 
   end generate;

diff --git a/sw/ocd-firmware/park_loop.S b/sw/ocd-firmware/park_loop.S
@@ -38,7 +38,7 @@
 .equ DM_DATA_BASE, 0xffffff80 // base address of debug_module's abstract data buffer (DATA)
 .equ DM_SREG_BASE, 0xffffffC0 // base address of debug_module's status register
 
-// status register (SREG) byte(!!!) offsets
+// status register (SREG) byte(!) offsets
 .equ SREG_HLT_ACK, ( 0 / 8) // -/w: CPU has halted in debug mode and is waiting in park loop
 .equ SREG_RES_REQ, ( 8 / 8) // r/-: DM requests to resume
 .equ SREG_RES_ACK, ( 8 / 8) // -/w: CPU starts to resume
@@ -68,24 +68,24 @@ entry_normal:
 // polling loop - waiting for requests
 park_loop:
   sb      zero, (DM_SREG_BASE+SREG_HLT_ACK)(zero) // ACK that CPU is halted
-  lbu     x8, (DM_SREG_BASE+SREG_EXE_REQ)(zero)   // request to execute program buffer?
-  bnez    x8, execute
-  lbu     x8, (DM_SREG_BASE+SREG_RES_REQ)(zero)   // request to resume?
-  beqz    x8, park_loop
+  lbu     x8,   (DM_SREG_BASE+SREG_EXE_REQ)(zero) // request to execute program buffer?
+  bnez    x8,   execute
+  lbu     x8,   (DM_SREG_BASE+SREG_RES_REQ)(zero) // request to resume?
+  beqz    x8,   park_loop
 
 // resume normal operation
 resume:
-  sb      x8, (DM_SREG_BASE+SREG_RES_ACK)(zero)   // ACK that CPU is about to resume
-  csrr    x8, dscratch0                           // restore x8 from dscratch0
+  sb      zero, (DM_SREG_BASE+SREG_RES_ACK)(zero) // ACK that CPU is about to resume
+  csrr    x8,   dscratch0                         // restore x8 from dscratch0
   dret                                            // exit debug mode
 
 // execute program buffer
 execute:
   sb      zero, (DM_SREG_BASE+SREG_EXE_ACK)(zero) // ACK that execution is about to start
-  csrr    x8, dscratch0                           // restore x8 from dscratch0
-  fence.i                                         // synchronize ifetch / i-cache & prefetch with memory (PBUF)
+  csrr    x8,   dscratch0                         // restore x8 from dscratch0
+  fence.i                                         // synchronize i-cache and prefetch with memory (PBUF)
   jalr    zero, zero, %lo(DM_PBUF_BASE)           // jump to beginning of program buffer (PBUF)
 
 // fill remaining ROM space with instructions that cause a debug-mode-internal exception
 unused:
-  ecall
+  ecall                                           // should never be reached
diff --git a/sw/openocd/openocd_neorv32.cfg b/sw/openocd/openocd_neorv32.cfg
@@ -22,7 +22,7 @@ ftdi layout_signal nTRST -ndata 0x0010 -noe 0x0040
 # ----------------------------------------------
 # Logical interface configuration
 # ----------------------------------------------
-adapter speed 2000
+adapter speed 4000
 transport select jtag
 
 
@@ -43,13 +43,6 @@ target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
 riscv set_mem_access progbuf
 
 
-# ----------------------------------------------
-# Scratch pad RAM
-# ----------------------------------------------
-# work area ("scratch pad RAM"): beginning of (internal) DMEM, 256 bytes, requires(!) backup
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 256 -work-area-backup 1
-
-
 # ----------------------------------------------
 # Expose NEORV32-specific CSRs
 # ----------------------------------------------