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data_path.syr
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Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.18 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.18 secs
--> Reading design: data_path.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "data_path.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "data_path"
Output Format : NGC
Target Device : xc3s200-4-ft256
---- Source Options
Top Module Name : data_path
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_1.vhd" in Library work.
Architecture behavioral of Entity sbox_1 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_2.vhd" in Library work.
Architecture behavioral of Entity sbox_2 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_3.vhd" in Library work.
Architecture behavioral of Entity sbox_3 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_4.vhd" in Library work.
Architecture behavioral of Entity sbox_4 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/register_32.vhd" in Library work.
Architecture behavioral of Entity register_32 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/buffer.vhd" in Library work.
Architecture behavioral of Entity tri_state_buffer is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/f_function.vhd" in Library work.
Architecture behavioral of Entity f_function is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_evaluator.vhd" in Library work.
Architecture behavioral of Entity key_evaluator is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_adjuster.vhd" in Library work.
Architecture behavioral of Entity key_adjuster is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_mux.vhd" in Library work.
Architecture behavioral of Entity key_mux is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/register_448.vhd" in Library work.
Architecture behavioral of Entity register_448 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/combinational_shifter.vhd" in Library work.
Architecture behavioral of Entity combinational_shifter is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/register_576.vhd" in Library work.
Architecture behavioral of Entity register_576 is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/pi_combinational_shifter.vhd" in Library work.
Architecture behavioral of Entity pi_combinational_shifter is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/mode_register.vhd" in Library work.
Architecture behavioral of Entity mode_register is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_generator.vhd" in Library work.
Architecture behavioral of Entity key_generator is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/round.vhd" in Library work.
Architecture behavioral of Entity round is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/post_processing.vhd" in Library work.
Architecture behavioral of Entity post_processing is up to date.
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/data_path.vhd" in Library work.
Entity <data_path> compiled.
Entity <data_path> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <data_path> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <mode_register> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <key_generator> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <round> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <post_processing> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <key_evaluator> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <key_adjuster> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <key_mux> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <register_448> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <combinational_shifter> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <register_576> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <pi_combinational_shifter> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <register_32> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <f_function> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <tri_state_buffer> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <sbox_1> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <sbox_2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <sbox_3> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <sbox_4> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <data_path> in library <work> (Architecture <behavioral>).
Entity <data_path> analyzed. Unit <data_path> generated.
Analyzing Entity <mode_register> in library <work> (Architecture <behavioral>).
Entity <mode_register> analyzed. Unit <mode_register> generated.
Analyzing Entity <key_generator> in library <work> (Architecture <behavioral>).
Entity <key_generator> analyzed. Unit <key_generator> generated.
Analyzing Entity <key_evaluator> in library <work> (Architecture <behavioral>).
Entity <key_evaluator> analyzed. Unit <key_evaluator> generated.
Analyzing Entity <key_adjuster> in library <work> (Architecture <behavioral>).
Entity <key_adjuster> analyzed. Unit <key_adjuster> generated.
Analyzing Entity <key_mux> in library <work> (Architecture <behavioral>).
Entity <key_mux> analyzed. Unit <key_mux> generated.
Analyzing Entity <register_448> in library <work> (Architecture <behavioral>).
Entity <register_448> analyzed. Unit <register_448> generated.
Analyzing Entity <combinational_shifter> in library <work> (Architecture <behavioral>).
Entity <combinational_shifter> analyzed. Unit <combinational_shifter> generated.
Analyzing Entity <register_576> in library <work> (Architecture <behavioral>).
Entity <register_576> analyzed. Unit <register_576> generated.
Analyzing Entity <pi_combinational_shifter> in library <work> (Architecture <behavioral>).
Entity <pi_combinational_shifter> analyzed. Unit <pi_combinational_shifter> generated.
Analyzing Entity <round> in library <work> (Architecture <behavioral>).
Entity <round> analyzed. Unit <round> generated.
Analyzing Entity <register_32> in library <work> (Architecture <behavioral>).
Entity <register_32> analyzed. Unit <register_32> generated.
Analyzing Entity <f_function> in library <work> (Architecture <behavioral>).
Entity <f_function> analyzed. Unit <f_function> generated.
Analyzing Entity <sbox_1> in library <work> (Architecture <behavioral>).
Entity <sbox_1> analyzed. Unit <sbox_1> generated.
Analyzing Entity <sbox_2> in library <work> (Architecture <behavioral>).
Entity <sbox_2> analyzed. Unit <sbox_2> generated.
Analyzing Entity <sbox_3> in library <work> (Architecture <behavioral>).
Entity <sbox_3> analyzed. Unit <sbox_3> generated.
Analyzing Entity <sbox_4> in library <work> (Architecture <behavioral>).
Entity <sbox_4> analyzed. Unit <sbox_4> generated.
Analyzing Entity <post_processing> in library <work> (Architecture <behavioral>).
Entity <post_processing> analyzed. Unit <post_processing> generated.
Analyzing Entity <tri_state_buffer> in library <work> (Architecture <behavioral>).
Entity <tri_state_buffer> analyzed. Unit <tri_state_buffer> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <mode_register>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/mode_register.vhd".
Found 1-bit register for signal <interim>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <mode_register> synthesized.
Synthesizing Unit <key_evaluator>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_evaluator.vhd".
WARNING:Xst:647 - Input <input<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <key_evaluator> synthesized.
Synthesizing Unit <key_adjuster>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_adjuster.vhd".
Unit <key_adjuster> synthesized.
Synthesizing Unit <key_mux>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_mux.vhd".
Unit <key_mux> synthesized.
Synthesizing Unit <register_448>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/register_448.vhd".
Found 448-bit register for signal <reg_val>.
INFO:Xst:738 - HDL ADVISOR - 448 flip-flops were inferred for signal <reg_val>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
Summary:
inferred 448 D-type flip-flop(s).
Unit <register_448> synthesized.
Synthesizing Unit <combinational_shifter>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/combinational_shifter.vhd".
Found 448-bit 16-to-1 multiplexer for signal <result>.
Summary:
inferred 448 Multiplexer(s).
Unit <combinational_shifter> synthesized.
Synthesizing Unit <register_576>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/register_576.vhd".
Found 576-bit register for signal <reg_val>.
INFO:Xst:738 - HDL ADVISOR - 576 flip-flops were inferred for signal <reg_val>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
Summary:
inferred 576 D-type flip-flop(s).
Unit <register_576> synthesized.
Synthesizing Unit <pi_combinational_shifter>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/pi_combinational_shifter.vhd".
Unit <pi_combinational_shifter> synthesized.
Synthesizing Unit <register_32>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/register_32.vhd".
Found 32-bit register for signal <reg_val>.
Summary:
inferred 32 D-type flip-flop(s).
Unit <register_32> synthesized.
Synthesizing Unit <sbox_1>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_1.vhd".
WARNING:Xst:1781 - Signal <myrom<9>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<8>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<7>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<6>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<5>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<4>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<3>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<2>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<1>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<15>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<14>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<13>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<12>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<11>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<10>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<0>> is used but never assigned. Tied to default value.
Found 16x512-bit ROM for signal <myrom$rom0000>.
Found 32-bit 16-to-1 multiplexer for signal <output>.
Summary:
inferred 1 ROM(s).
inferred 32 Multiplexer(s).
Unit <sbox_1> synthesized.
Synthesizing Unit <sbox_2>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_2.vhd".
WARNING:Xst:1781 - Signal <myrom<9>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<8>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<7>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<6>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<5>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<4>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<3>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<2>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<1>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<15>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<14>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<13>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<12>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<11>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<10>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<0>> is used but never assigned. Tied to default value.
Found 16x512-bit ROM for signal <myrom$rom0000>.
Found 32-bit 16-to-1 multiplexer for signal <output>.
Summary:
inferred 1 ROM(s).
inferred 32 Multiplexer(s).
Unit <sbox_2> synthesized.
Synthesizing Unit <sbox_3>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_3.vhd".
WARNING:Xst:1781 - Signal <myrom<9>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<8>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<7>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<6>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<5>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<4>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<3>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<2>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<1>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<15>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<14>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<13>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<12>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<11>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<10>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<0>> is used but never assigned. Tied to default value.
Found 16x512-bit ROM for signal <myrom$rom0000>.
Found 32-bit 16-to-1 multiplexer for signal <output>.
Summary:
inferred 1 ROM(s).
inferred 32 Multiplexer(s).
Unit <sbox_3> synthesized.
Synthesizing Unit <sbox_4>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/sbox_4.vhd".
WARNING:Xst:1781 - Signal <myrom<9>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<8>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<7>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<6>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<5>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<4>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<3>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<2>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<1>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<15>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<14>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<13>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<12>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<11>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<10>> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <myrom<0>> is used but never assigned. Tied to default value.
Found 16x512-bit ROM for signal <myrom$rom0000>.
Found 32-bit 16-to-1 multiplexer for signal <output>.
Summary:
inferred 1 ROM(s).
inferred 32 Multiplexer(s).
Unit <sbox_4> synthesized.
Synthesizing Unit <tri_state_buffer>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/buffer.vhd".
Found 64-bit tristate buffer for signal <interim_output>.
Summary:
inferred 64 Tristate(s).
Unit <tri_state_buffer> synthesized.
Synthesizing Unit <key_generator>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/key_generator.vhd".
Found 32-bit xor2 for signal <round_key>.
Unit <key_generator> synthesized.
Synthesizing Unit <post_processing>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/post_processing.vhd".
Found 32-bit xor2 for signal <left>.
Unit <post_processing> synthesized.
Synthesizing Unit <f_function>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/f_function.vhd".
Found 32-bit adder for signal <output>.
Found 32-bit adder for signal <output$addsub0000> created at line 105.
Found 32-bit xor2 for signal <output$xor0000> created at line 105.
Summary:
inferred 2 Adder/Subtractor(s).
Unit <f_function> synthesized.
Synthesizing Unit <round>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/round.vhd".
Found 32-bit xor2 for signal <left_result>.
Found 32-bit xor2 for signal <right_result>.
Unit <round> synthesized.
Synthesizing Unit <data_path>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/data_path.vhd".
Unit <data_path> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 4
16x512-bit ROM : 4
# Adders/Subtractors : 2
32-bit adder : 2
# Registers : 582
1-bit register : 577
32-bit register : 4
448-bit register : 1
# Multiplexers : 5
32-bit 16-to-1 multiplexer : 4
448-bit 16-to-1 multiplexer : 1
# Tristates : 1
64-bit tristate buffer : 1
# Xors : 5
32-bit xor2 : 5
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# ROMs : 4
16x512-bit ROM : 4
# Adders/Subtractors : 2
32-bit adder : 2
# Registers : 1153
Flip-Flops : 1153
# Multiplexers : 5
32-bit 16-to-1 multiplexer : 4
448-bit 16-to-1 multiplexer : 1
# Xors : 5
32-bit xor2 : 5
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <data_path> ...
Optimizing unit <register_448> ...
Optimizing unit <register_576> ...
Optimizing unit <register_32> ...
Optimizing unit <key_generator> ...
Optimizing unit <round> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block data_path, actual ratio is 137.
Optimizing block <data_path> to meet ratio 100 (+ 5) of 1920 slices :
WARNING:Xst:2254 - Area constraint could not be met for block <data_path>, final ratio is 136.
FlipFlop generating_keys/key_register/reg_val_20 has been replicated 1 time(s)
FlipFlop generating_keys/key_register/reg_val_31 has been replicated 1 time(s)
FlipFlop generating_keys/pi_register/reg_val_20 has been replicated 1 time(s)
FlipFlop generating_keys/pi_register/reg_val_31 has been replicated 1 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 1157
Flip-Flops : 1157
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : data_path.ngr
Top Level Output File Name : data_path
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 140
Cell Usage :
# BELS : 5825
# GND : 1
# INV : 1
# LUT2 : 213
# LUT2_D : 18
# LUT3 : 1687
# LUT3_D : 12
# LUT4 : 2422
# LUT4_D : 458
# LUT4_L : 5
# MUXCY : 62
# MUXF5 : 530
# MUXF6 : 256
# MUXF7 : 96
# XORCY : 64
# FlipFlops/Latches : 1157
# FDCE : 578
# FDCPE : 578
# FDE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 139
# IBUF : 75
# OBUFT : 64
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 2618 out of 1920 136% (*)
Number of Slice Flip Flops: 1157 out of 3840 30%
Number of 4 input LUTs: 4816 out of 3840 125% (*)
Number of IOs: 140
Number of bonded IOBs: 140 out of 173 80%
Number of GCLKs: 1 out of 8 12%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 1157 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------------------------------------------+---------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
---------------------------------------------------------------------------------------------------+---------------------------------------------+-------+
clr | IBUF | 578 |
N0(XST_GND:G) | NONE(generating_keys/pi_register/reg_val_10)| 293 |
pi_preset | IBUF | 293 |
generating_keys/pi_register/reg_val_573_and0000(generating_keys/pi_register/reg_val_573_and00001:O)| NONE(generating_keys/pi_register/reg_val_0) | 285 |
generating_keys/pi_register/reg_val_573_and0001(generating_keys/pi_register/reg_val_573_and00011:O)| NONE(generating_keys/pi_register/reg_val_0) | 285 |
---------------------------------------------------------------------------------------------------+---------------------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 20.283ns (Maximum Frequency: 49.302MHz)
Minimum input arrival time before clock: 6.150ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: 10.096ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 20.283ns (frequency: 49.302MHz)
Total number of paths / destination ports: 7974992 / 1156
-------------------------------------------------------------------------
Delay: 20.283ns (Levels of Logic = 41)
Source: generating_keys/key_register/reg_val_22 (FF)
Destination: recurring_rounds/left_register/reg_val_31 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: generating_keys/key_register/reg_val_22 to recurring_rounds/left_register/reg_val_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 8 0.720 1.422 generating_keys/key_register/reg_val_22 (generating_keys/key_register/reg_val_22)
LUT2:I0->O 503 0.551 4.560 generating_keys/Mxor_round_key_Result<22>1 (round_key<22>)
LUT4:I3->O 1 0.551 0.827 recurring_rounds/the_f_function/s_box_2/Mrom_myrom_rom000012911_SW0 (N293)
LUT4:I3->O 1 0.551 0.869 recurring_rounds/the_f_function/s_box_2/Mrom_myrom_rom000012911 (recurring_rounds/the_f_function/s_box_2/Mrom_myrom_rom0000129)
LUT3:I2->O 1 0.551 0.000 recurring_rounds/the_f_function/s_box_2/Mmux_output_634 (recurring_rounds/the_f_function/s_box_2/Mmux_output_634)
MUXF5:I1->O 1 0.360 0.000 recurring_rounds/the_f_function/s_box_2/Mmux_output_5_f5_21 (recurring_rounds/the_f_function/s_box_2/Mmux_output_5_f522)
MUXF6:I0->O 1 0.342 0.827 recurring_rounds/the_f_function/s_box_2/Mmux_output_3_f6_10 (recurring_rounds/the_f_function/s_box_2/Mmux_output_3_f611)
LUT4:I3->O 1 0.551 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_lut<1> (recurring_rounds/the_f_function/Madd_output_addsub0000_lut<1>)
MUXCY:S->O 1 0.500 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<1> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<1>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<2> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<2>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<3> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<3>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<4> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<4>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<5> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<5>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<6> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<6>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<7> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<7>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<8> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<8>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<9> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<9>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<10> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<10>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<11> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<11>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<12> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<12>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<13> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<13>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<14> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<14>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<15> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<15>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<16> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<16>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<17> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<17>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<18> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<18>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<19> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<19>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<20> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<20>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<21> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<21>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<22> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<22>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<23> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<23>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<24> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<24>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<25> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<25>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<26> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<26>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<27> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<27>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<28> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<28>)
MUXCY:CI->O 1 0.064 0.000 recurring_rounds/the_f_function/Madd_output_addsub0000_cy<29> (recurring_rounds/the_f_function/Madd_output_addsub0000_cy<29>)
XORCY:CI->O 1 0.904 0.869 recurring_rounds/the_f_function/Madd_output_addsub0000_xor<30> (recurring_rounds/the_f_function/output_addsub0000<30>)
LUT3:I2->O 1 0.551 0.000 recurring_rounds/the_f_function/Madd_output_lut<30> (recurring_rounds/the_f_function/Madd_output_lut<30>)
MUXCY:S->O 0 0.500 0.000 recurring_rounds/the_f_function/Madd_output_cy<30> (recurring_rounds/the_f_function/Madd_output_cy<30>)
XORCY:CI->O 1 0.904 0.827 recurring_rounds/the_f_function/Madd_output_xor<31> (recurring_rounds/substitute_value<31>)
LUT4:I3->O 1 0.551 0.000 recurring_rounds/left_mux_out<31>1 (recurring_rounds/left_mux_out<31>)
FDCE:D 0.203 recurring_rounds/left_register/reg_val_31
----------------------------------------
Total 20.283ns (10.082ns logic, 10.201ns route)
(49.7% logic, 50.3% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 1736 / 1672
-------------------------------------------------------------------------
Offset: 6.150ns (Levels of Logic = 2)
Source: key_mux_select (PAD)
Destination: generating_keys/key_register/reg_val_1 (FF)
Destination Clock: clk rising
Data Path: key_mux_select to generating_keys/key_register/reg_val_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 448 0.821 4.575 key_mux_select_IBUF (key_mux_select_IBUF)
LUT2:I0->O 1 0.551 0.000 generating_keys/key_multiplexer/output<97>1 (generating_keys/mux_output<97>)
FDCE:D 0.203 generating_keys/key_register/reg_val_97
----------------------------------------
Total 6.150ns (1.575ns logic, 4.575ns route)
(25.6% logic, 74.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 64 / 64
-------------------------------------------------------------------------
Offset: 7.165ns (Levels of Logic = 1)
Source: post_process/left_register/reg_val_31 (FF)
Destination: cyphertext<63> (PAD)
Source Clock: clk rising
Data Path: post_process/left_register/reg_val_31 to cyphertext<63>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 1 0.720 0.801 post_process/left_register/reg_val_31 (post_process/left_register/reg_val_31)
OBUFT:I->O 5.644 cyphertext_63_OBUFT (cyphertext<63>)
----------------------------------------
Total 7.165ns (6.364ns logic, 0.801ns route)
(88.8% logic, 11.2% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 64 / 64
-------------------------------------------------------------------------
Delay: 10.096ns (Levels of Logic = 3)
Source: output_ready (PAD)
Destination: cyphertext<63> (PAD)
Data Path: output_ready to cyphertext<63>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.821 0.801 output_ready_IBUF (output_ready_IBUF)
INV:I->O 64 0.551 2.036 post_process/my_buffer/output_ready_inv1_INV_0 (post_process/my_buffer/output_ready_inv)
OBUFT:T->O 5.887 cyphertext_63_OBUFT (cyphertext<63>)
----------------------------------------
Total 10.096ns (7.259ns logic, 2.837ns route)
(71.9% logic, 28.1% route)
=========================================================================
Total REAL time to Xst completion: 79.00 secs
Total CPU time to Xst completion: 79.15 secs
-->
Total memory usage is 329788 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 67 ( 0 filtered)
Number of infos : 2 ( 0 filtered)