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combinational_shifter.syr
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combinational_shifter.syr
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Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: combinational_shifter.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "combinational_shifter.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "combinational_shifter"
Output Format : NGC
Target Device : xc3s200-4-ft256
---- Source Options
Top Module Name : combinational_shifter
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/combinational_shifter.vhd" in Library work.
Architecture behavioral of Entity combinational_shifter is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <combinational_shifter> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <combinational_shifter> in library <work> (Architecture <behavioral>).
Entity <combinational_shifter> analyzed. Unit <combinational_shifter> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <combinational_shifter>.
Related source file is "C:/Users/jerem/OneDrive/Desktop/projects/blowfish/combinational_shifter.vhd".
Found 448-bit 16-to-1 multiplexer for signal <result>.
Summary:
inferred 448 Multiplexer(s).
Unit <combinational_shifter> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multiplexers : 1
448-bit 16-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multiplexers : 1
448-bit 16-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <combinational_shifter> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block combinational_shifter, actual ratio is 36.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : combinational_shifter.ngr
Top Level Output File Name : combinational_shifter
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 900
Cell Usage :
# BELS : 1162
# LUT2 : 1
# LUT3 : 643
# LUT4 : 294
# MUXF5 : 192
# MUXF6 : 32
# IO Buffers : 900
# IBUF : 452
# OBUF : 448
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 511 out of 1920 26%
Number of 4 input LUTs: 938 out of 3840 24%
Number of IOs: 900
Number of bonded IOBs: 900 out of 173 520% (*)
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 14.675ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 3904 / 448
-------------------------------------------------------------------------
Delay: 14.675ns (Levels of Logic = 5)
Source: key_size<0> (PAD)
Destination: output<191> (PAD)
Data Path: key_size<0> to output<191>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 266 0.821 3.533 key_size_0_IBUF (key_size_0_IBUF)
LUT2:I0->O 96 0.551 2.415 Mmux_result121911 (N01)
LUT4:I1->O 1 0.551 0.000 Mmux_result_395 (Mmux_result_395)
MUXF5:I1->O 1 0.360 0.801 Mmux_result_2_f5_94 (output_99_OBUF)
OBUF:I->O 5.644 output_99_OBUF (output<99>)
----------------------------------------
Total 14.675ns (7.927ns logic, 6.748ns route)
(54.0% logic, 46.0% route)
=========================================================================
Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.55 secs
-->
Total memory usage is 243900 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)