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Hi
I crafted a "standard" IP for the DDR interface for the nexys video, to aid my students (at USM, usm.cl) to instance and use the ddr interface. Needs testing and nicer packaging. If you like it, I think a rework of this IP to other Digilent boards might be feasible. Currently I'm also working in an Arty and Nexysa7/DDR versions.
Is not a great deal. I relied in the fact that boards usually have just one memory configuration, but now we not depend on the older Coregen based MIG. It behaves like a normal IP