{"payload":{"header_redesign_enabled":false,"results":[],"type":"repositories","page":1,"page_count":0,"elapsed_millis":34,"errors":[],"result_count":0,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Avossstef%252FVIC20Nano%2B%2Blanguage%253ASystemVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/sponsors/batch_deferred_sponsor_buttons":{"post":"4TxDFB_PLkOMXaDpy1gAu45ROSyP9i3s_4fy0pYHa3tNWz75IjdKoEUpp0r48JnNo0YvoFttK25xObuKkiN3xA"}}},"title":"Repository search results"}