diff --git a/sonic_platform_base/sonic_xcvr/api/public/cmis.py b/sonic_platform_base/sonic_xcvr/api/public/cmis.py
index 36657ddd7..a677f32ff 100644
--- a/sonic_platform_base/sonic_xcvr/api/public/cmis.py
+++ b/sonic_platform_base/sonic_xcvr/api/public/cmis.py
@@ -31,6 +31,12 @@ def __init__(self, xcvr_eeprom):
         self.vdm = CmisVdmApi(xcvr_eeprom) if not self.is_flat_memory() else None
         self.cdb = CmisCdbApi(xcvr_eeprom) if not self.is_flat_memory() else None
 
+    def get_manufacturer(self):
+        '''
+        This function returns the manufacturer of the module
+        '''
+        return self.xcvr_eeprom.read(consts.VENDOR_NAME_FIELD)
+
     def get_model(self):
         '''
         This function returns the part number of the module
@@ -2069,7 +2075,7 @@ def get_application(self, lane):
 
         return (appl & 0xf)
 
-    def set_application(self, channel, appl_code):
+    def set_application(self, channel, appl_code, ec=0):
         """
         Update the selected application code to the specified lanes on the host side
 
@@ -2092,11 +2098,323 @@ def set_application(self, channel, appl_code):
                 lane_first = lane
             addr = "{}_{}_{}".format(consts.STAGED_CTRL_APSEL_FIELD, 0, lane + 1)
             data = (appl_code << 4) | (lane_first << 1)
+            #set EC bit
+            data|= ec
             self.xcvr_eeprom.write(addr, data)
 
-        # Apply DataPathInit
+    def scs_apply_datapath_init(self, channel):
+        '''
+        This function applies DataPathInit
+        '''
         return self.xcvr_eeprom.write("%s_%d" % (consts.STAGED_CTRL_APPLY_DPINIT_FIELD, 0), channel)
 
+    def get_rx_output_amp_max_val(self):
+        '''
+        This function returns the supported RX output amp val
+        '''
+        rx_amp_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_LEVEL_SUPPORT)
+        if rx_amp_max_val is None:
+            return None
+        return rx_amp_max_val
+
+    def get_rx_output_eq_pre_max_val(self):
+        '''
+        This function returns the supported RX output eq pre cursor val
+        '''
+        rx_pre_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_PRE_CURSOR_MAX)
+        if rx_pre_max_val is None:
+            return None
+        return rx_pre_max_val
+
+    def get_rx_output_eq_post_max_val(self):
+        '''
+        This function returns the supported RX output eq post cursor val
+        '''
+        rx_post_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_POST_CURSOR_MAX)
+        if rx_post_max_val is None:
+            return None
+        return rx_post_max_val
+
+    def get_tx_input_eq_max_val(self):
+        '''
+        This function returns the supported TX input eq val
+        '''
+        tx_input_max_val = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_MAX)
+        if tx_input_max_val is None:
+            return None
+        return tx_input_max_val
+
+    def get_tx_cdr_supported(self):
+        '''
+        This function returns the supported TX CDR field
+        '''
+        tx_cdr_support = self.xcvr_eeprom.read(consts.TX_CDR_SUPPORT_FIELD)
+        if not tx_cdr_support or tx_cdr_support is None:
+            return False
+        return tx_cdr_support
+
+    def get_rx_cdr_supported(self):
+        '''
+        This function returns the supported RX CDR field
+        '''
+        rx_cdr_support = self.xcvr_eeprom.read(consts.RX_CDR_SUPPORT_FIELD)
+        if not rx_cdr_support or rx_cdr_support is None:
+            return False
+        return rx_cdr_support
+
+    def get_tx_input_eq_fixed_supported(self):
+        '''
+        This function returns the supported TX input eq field
+        '''
+        tx_fixed_support = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD)
+        if not tx_fixed_support or tx_fixed_support is None:
+            return False
+        return tx_fixed_support
+
+    def get_tx_input_adaptive_eq_supported(self):
+        '''
+        This function returns the supported TX input adaptive eq field
+        '''
+        tx_adaptive_support = self.xcvr_eeprom.read(consts.TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD)
+        if not tx_adaptive_support or tx_adaptive_support is None:
+            return False
+        return tx_adaptive_support
+
+    def get_tx_input_recall_buf1_supported(self):
+        '''
+        This function returns the supported TX input recall buf1 field
+        '''
+        tx_recall_buf1_support = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_RECALL_BUF1_SUPPORT_FIELD)
+        if not tx_recall_buf1_support or tx_recall_buf1_support is None:
+            return False
+        return tx_recall_buf1_support
+
+    def get_tx_input_recall_buf2_supported(self):
+        '''
+        This function returns the supported TX input recall buf2 field
+        '''
+        tx_recall_buf2_support = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_RECALL_BUF2_SUPPORT_FIELD)
+        if not tx_recall_buf2_support or tx_recall_buf2_support is None:
+            return False
+        return tx_recall_buf2_support
+
+    def get_rx_ouput_amp_ctrl_supported(self):
+        '''
+        This function returns the supported RX output amp control field
+        '''
+        rx_amp_support = self.xcvr_eeprom.read(consts.RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD)
+        if not rx_amp_support or rx_amp_support is None:
+            return False
+        return rx_amp_support
+
+    def get_rx_output_eq_pre_ctrl_supported(self):
+        '''
+        This function returns the supported RX output eq pre control field
+        '''
+        rx_pre_support = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_PRE_CTRL_SUPPORT_FIELD)
+        if not rx_pre_support or rx_pre_support is None:
+            return False
+        return rx_pre_support
+
+    def get_rx_output_eq_post_ctrl_supported(self):
+        '''
+        This function returns the supported RX output eq post control field
+        '''
+        rx_post_support = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_POST_CTRL_SUPPORT_FIELD)
+        if not rx_post_support or rx_post_support is None:
+            return False
+        return rx_post_support
+
+    def scs_lane_write(self, si_param, host_lanes_mask, si_settings_dict):
+        '''
+        This function sets each lane val based on SI param
+        '''
+        for lane in range(self.NUM_CHANNELS):
+            if ((1 << lane) & host_lanes_mask) == 0:
+                continue
+            lane = lane+1
+            si_param_lane = "{}{}".format(si_param, lane)
+            si_param_lane_val = si_settings_dict[si_param_lane]
+            if si_param_lane_val is None:
+                return False
+            if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val):
+                return False
+        return True
+
+    def stage_output_eq_pre_cursor_target_rx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies RX output eq pre cursor settings
+        '''
+        rx_pre_max_val = self.get_rx_output_eq_pre_max_val()
+        if rx_pre_max_val is None:
+            return False
+        for lane in range(self.NUM_CHANNELS):
+            if ((1 << lane) & host_lanes_mask) == 0:
+                continue
+            lane = lane+1
+            si_param_lane = "{}{}".format(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX, lane)
+            si_param_lane_val = si_settings_dict[si_param_lane]
+            if si_param_lane_val is None or si_param_lane_val > rx_pre_max_val:
+                return False
+            if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val):
+                return False
+        return True
+
+    def stage_output_eq_post_cursor_target_rx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies RX output eq post cursor settings
+        '''
+        rx_post_max_val = self.get_rx_output_eq_post_max_val()
+        if rx_post_max_val is None:
+            return False
+        for lane in range(self.NUM_CHANNELS):
+            if ((1 << lane) & host_lanes_mask) == 0:
+                continue
+            lane = lane+1
+            si_param_lane = "{}{}".format(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX, lane)
+            si_param_lane_val = si_settings_dict[si_param_lane]
+            if si_param_lane_val is None or si_param_lane_val > rx_post_max_val:
+                return False
+            if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val):
+                return False
+        return True
+
+    def stage_output_amp_target_rx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies RX output amp settings
+        '''
+        rx_amp_max_val = self.get_rx_output_amp_max_val()
+        if rx_amp_max_val is None:
+            return False
+        for lane in range(self.NUM_CHANNELS):
+            if ((1 << lane) & host_lanes_mask) == 0:
+                continue
+            lane = lane+1
+            si_param_lane = "{}{}".format(consts.OUTPUT_AMPLITUDE_TARGET_RX, lane)
+            si_param_lane_val = si_settings_dict[si_param_lane]
+            if si_param_lane_val is None or si_param_lane_val > rx_amp_max_val:
+                return False
+            if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val):
+                return False
+        return True
+
+    def stage_fixed_input_target_tx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies fixed TX input si settings
+        '''
+        tx_fixed_input = self.get_tx_input_eq_max_val()
+        if tx_fixed_input is None:
+            return False
+        for lane in range(self.NUM_CHANNELS):
+            if ((1 << lane) & host_lanes_mask) == 0:
+                continue
+            lane = lane+1
+            si_param_lane = "{}{}".format(consts.FIXED_INPUT_EQ_TARGET_TX, lane)
+            si_param_lane_val = si_settings_dict[si_param_lane]
+            if si_param_lane_val is None or si_param_lane_val > tx_fixed_input:
+                return False
+            if not self.xcvr_eeprom.write(si_param_lane, si_param_lane_val):
+                return False
+        return True
+
+    def stage_adaptive_input_eq_recall_tx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies adaptive TX input recall si settings.
+        '''
+        if si_settings_dict is None:
+            return False
+        return self.scs_lane_write(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX, host_lanes_mask, si_settings_dict)
+
+    def stage_adaptive_input_eq_enable_tx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies adaptive TX input enable si settings
+        '''
+        if si_settings_dict is None:
+            return False
+        return self.scs_lane_write(consts.ADAPTIVE_INPUT_EQ_ENABLE_TX, host_lanes_mask, si_settings_dict)
+
+    def stage_cdr_tx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies TX CDR si settings
+        '''
+        if si_settings_dict is None:
+            return False
+        return self.scs_lane_write(consts.CDR_ENABLE_TX, host_lanes_mask, si_settings_dict)
+
+    def stage_cdr_rx(self, host_lanes_mask, si_settings_dict):
+        '''
+        This function applies RX CDR si settings
+        '''
+        if si_settings_dict is None:
+            return False
+        return self.scs_lane_write(consts.CDR_ENABLE_RX, host_lanes_mask, si_settings_dict)
+
+    def stage_rx_si_settings(self, host_lanes_mask, si_settings_dict):
+        for si_param in si_settings_dict:
+            if si_param == consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX:
+                if self.get_rx_output_eq_pre_ctrl_supported():
+                    if not self.stage_output_eq_pre_cursor_target_rx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            elif si_param == consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX:
+                if self.get_rx_output_eq_post_ctrl_supported():
+                    if not self.stage_output_eq_post_cursor_target_rx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            elif si_param == consts.OUTPUT_AMPLITUDE_TARGET_RX:
+                if self.get_rx_ouput_amp_ctrl_supported():
+                    if not self.stage_output_amp_target_rx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            elif si_param == consts.CDR_ENABLE_RX:
+                if self.get_rx_cdr_supported():
+                    if not self.stage_cdr_rx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            else:
+                return False
+
+        return True
+
+    def stage_tx_si_settings(self, host_lanes_mask, si_settings_dict):
+        for si_param in si_settings_dict:
+            if si_param == consts.FIXED_INPUT_EQ_TARGET_TX:
+                if self.get_tx_input_eq_fixed_supported():
+                    if not self.stage_fixed_input_target_tx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            elif si_param == consts.ADAPTIVE_INPUT_EQ_RECALLED_TX:
+                if self.get_tx_input_recall_buf1_supported() or self.get_tx_input_recall_buf2_supported():
+                    if not self.stage_adaptive_input_eq_recall_tx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            elif si_param == consts.ADAPTIVE_INPUT_EQ_ENABLE_TX:
+                if self.get_tx_input_adaptive_eq_supported():
+                    if not self.stage_adaptive_input_eq_enable_tx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            elif si_param == consts.CDR_ENABLE_TX:
+                if self.get_tx_cdr_supported():
+                    if not self.stage_cdr_tx(host_lanes_mask, si_settings_dict[si_param]):
+                        return False
+            else:
+                return False
+
+        return True
+
+    def stage_custom_si_settings(self, host_lanes_mask, optics_si_dict):
+        # Create TX/RX specific si_dict
+        rx_si_settings = {}
+        tx_si_settings = {}
+        for si_param in optics_si_dict:
+            if si_param.endswith("Tx"):
+                tx_si_settings[si_param] = optics_si_dict[si_param]
+            elif si_param.endswith("Rx"):
+                rx_si_settings[si_param] = optics_si_dict[si_param]
+
+        # stage RX si settings
+        if not self.stage_rx_si_settings(host_lanes_mask, rx_si_settings):
+            return False
+
+        # stage TX si settings
+        if not self.stage_tx_si_settings(host_lanes_mask, tx_si_settings):
+            return False
+
+        return True
+
     def get_error_description(self):
         dp_state = self.get_datapath_state()
         conf_state = self.get_config_datapath_hostlane_status()
diff --git a/sonic_platform_base/sonic_xcvr/fields/consts.py b/sonic_platform_base/sonic_xcvr/fields/consts.py
index c638f19b6..e9e250a32 100644
--- a/sonic_platform_base/sonic_xcvr/fields/consts.py
+++ b/sonic_platform_base/sonic_xcvr/fields/consts.py
@@ -299,6 +299,103 @@
 STAGED_CTRL_APPLY_IMMEDIATE_FIELD = "Staged Control Set Apply Immediate"
 STAGED_CTRL_APSEL_FIELD = "Staged Control Set ApSel"
 
+STAGED_CTRL0_TX_RX_CTRL_FIELD = "Staged Control TX RX Control"
+
+TX_INPUT_EQ_MAX = "TXInputEqMax"
+RX_OUTPUT_LEVEL_SUPPORT = "RX Output Level Supported"
+RX_OUTPUT_LEVEL_0_SUPPORTED = "RXOutputLevel0Supported"
+RX_OUTPUT_LEVEL_1_SUPPORTED = "RXOutputLevel1Supported"
+RX_OUTPUT_LEVEL_2_SUPPORTED = "RXOutputLevel2Supported"
+RX_OUTPUT_LEVEL_3_SUPPORTED = "RXOutputLevel3Supported"
+RX_OUTPUT_EQ_PRE_CURSOR_MAX = "RXOutputEqPreCursorMax"
+RX_OUTPUT_EQ_POST_CURSOR_MAX = "RXOutputEqPostCursorMax"
+
+SIGNAL_INTEGRITY_CTRL_ADVT_FIELD = "Signal Integrity Control Advertisement"
+TX_SI_CTRL_ADVT = "TX SI Control Advertisement"
+TX_CDR_SUPPORT_FIELD = "TXCDRSupported"
+TX_CDR_BYPASS_CTRL_FIELD = "TXCDRBypassSupported"
+TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD = "TXInputEqFixedManualSupported"
+TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD = "TXInputAdaptiveEqSupported"
+TX_INPUT_EQ_FREEZE_SUPPORT_FIELD = "TXInputEqFreezeSupported"
+TX_INPUT_EQ_RECALL_BUF1_SUPPORT_FIELD = "TXInputEqRecallBuf1Supported"
+TX_INPUT_EQ_RECALL_BUF2_SUPPORT_FIELD = "TXInputEqRecallBuf2Supported"
+TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD = "TXInputEqRecallBufSupported"
+RX_SI_CTRL_ADVT = "RX SI Control Advertisement"
+RX_CDR_SUPPORT_FIELD = "RxCDRSupported"
+RX_CDR_BYPASS_CTRL_FIELD = "RXCDRBypassSupported"
+RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD = "RXOutputAmpSupported"
+RX_OUTPUT_EQ_PRE_CTRL_SUPPORT_FIELD = "RXOutputEQPreSupported"
+RX_OUTPUT_EQ_POST_CTRL_SUPPORT_FIELD = "RXOutputEQPostSupported"
+RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD = "RXOutputEQSupported"
+
+ACTIVE_CTRL_FIELD = "Active Control Set"
+ADAPTIVE_INPUT_EQ_ENABLE_TX = "AdaptiveInputEqEnableTx"
+ADAPTIVE_INPUT_EQ_RECALLED_TX = "AdaptiveInputEqRecalledTx"
+ADAPTIVE_INPUT_EQ_RECALLED_TX1_4 = "AdaptiveInputEqRecalledTx1_4"
+ADAPTIVE_INPUT_EQ_RECALLED_TX1 = "AdaptiveInputEqRecalledTx1"
+ADAPTIVE_INPUT_EQ_RECALLED_TX2 = "AdaptiveInputEqRecalledTx2"
+ADAPTIVE_INPUT_EQ_RECALLED_TX3 = "AdaptiveInputEqRecalledTx3"
+ADAPTIVE_INPUT_EQ_RECALLED_TX4 = "AdaptiveInputEqRecalledTx4"
+ADAPTIVE_INPUT_EQ_RECALLED_TX5_8 = "AdaptiveInputEqRecalledTx5_8"
+ADAPTIVE_INPUT_EQ_RECALLED_TX5 = "AdaptiveInputEqRecalledTx5"
+ADAPTIVE_INPUT_EQ_RECALLED_TX6 = "AdaptiveInputEqRecalledTx6"
+ADAPTIVE_INPUT_EQ_RECALLED_TX7 = "AdaptiveInputEqRecalledTx7"
+ADAPTIVE_INPUT_EQ_RECALLED_TX8 = "AdaptiveInputEqRecalledTx8"
+FIXED_INPUT_EQ_TARGET_TX = "FixedInputEqTargetTx"
+FIXED_INPUT_EQ_TARGET_TX1_2 = "FixedInputEqTargetTx1_2"
+FIXED_INPUT_EQ_TARGET_TX1 = "FixedInputEqTargetTx1"
+FIXED_INPUT_EQ_TARGET_TX2 = "FixedInputEqTargetTx2"
+FIXED_INPUT_EQ_TARGET_TX3_4 = "FixedInputEqTargetTx3_4"
+FIXED_INPUT_EQ_TARGET_TX3 = "FixedInputEqTargetTx3"
+FIXED_INPUT_EQ_TARGET_TX4 = "FixedInputEqTargetTx4"
+FIXED_INPUT_EQ_TARGET_TX5_6 = "FixedInputEqTargetTx5_6"
+FIXED_INPUT_EQ_TARGET_TX5 = "FixedInputEqTargetTx5"
+FIXED_INPUT_EQ_TARGET_TX6 = "FixedInputEqTargetTx6"
+FIXED_INPUT_EQ_TARGET_TX7_8 = "FixedInputEqTargetTx7_8"
+FIXED_INPUT_EQ_TARGET_TX7 = "FixedInputEqTargetTx7"
+FIXED_INPUT_EQ_TARGET_TX8 = "FixedInputEqTargetTx8"
+CDR_ENABLE_TX = "CDREnableTx"
+CDR_ENABLE_RX = "CDREnableRx"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX = "OutputEqPreCursorTargetRx"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX1_2 = "OutputEqPreCursorTargetRx1_2"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX1 = "OutputEqPreCursorTargetRx1"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX2 = "OutputEqPreCursorTargetRx2"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX3_4 = "OutputEqPreCursorTargetRx3_4"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX3 = "OutputEqPreCursorTargetRx3"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX4 = "OutputEqPreCursorTargetRx4"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX5_6 = "OutputEqPreCursorTargetRx5_6"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX5 = "OutputEqPreCursorTargetRx5"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX6 = "OutputEqPreCursorTargetRx6"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX7_8 = "OutputEqPreCursorTargetRx7_8"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX7 = "OutputEqPreCursorTargetRx7"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX8 = "OutputEqPreCursorTargetRx8"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX = "OutputEqPostCursorTargetRx"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX1_2 = "OutputEqPostCursorTargetRx1_2"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX1 = "OutputEqPostCursorTargetRx1"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX2 = "OutputEqPostCursorTargetRx2"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX3_4 = "OutputEqPostCursorTargetRx3_4"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX3 = "OutputEqPostCursorTargetRx3"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX4 = "OutputEqPostCursorTargetRx4"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX5_6 = "OutputEqPostCursorTargetRx5_6"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX5 = "OutputEqPostCursorTargetRx5"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX6 = "OutputEqPostCursorTargetRx6"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX7_8 = "OutputEqPostCursorTargetRx7_8"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX7 = "OutputEqPostCursorTargetRx7"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX8 = "OutputEqPostCursorTargetRx8"
+OUTPUT_AMPLITUDE_TARGET_RX = "OutputAmplitudeTargetRx"
+OUTPUT_AMPLITUDE_TARGET_RX1_2 = "OutputAmplitudeTargetRx1_2"
+OUTPUT_AMPLITUDE_TARGET_RX1 = "OutputAmplitudeTargetRx1"
+OUTPUT_AMPLITUDE_TARGET_RX2 = "OutputAmplitudeTargetRx2"
+OUTPUT_AMPLITUDE_TARGET_RX3_4 = "OutputAmplitudeTargetRx3_4"
+OUTPUT_AMPLITUDE_TARGET_RX3 = "OutputAmplitudeTargetRx3"
+OUTPUT_AMPLITUDE_TARGET_RX4 = "OutputAmplitudeTargetRx4"
+OUTPUT_AMPLITUDE_TARGET_RX5_6 = "OutputAmplitudeTargetRx5_6"
+OUTPUT_AMPLITUDE_TARGET_RX5 = "OutputAmplitudeTargetRx5"
+OUTPUT_AMPLITUDE_TARGET_RX6 = "OutputAmplitudeTargetRx6"
+OUTPUT_AMPLITUDE_TARGET_RX7_8 = "OutputAmplitudeTargetRx7_8"
+OUTPUT_AMPLITUDE_TARGET_RX7 = "OutputAmplitudeTargetRx7"
+OUTPUT_AMPLITUDE_TARGET_RX8 = "OutputAmplitudeTargetRx8"
+
 # C-CMIS
 
 # Module configuration support fields
diff --git a/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py b/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py
index 512ed0776..140faeafd 100644
--- a/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py
+++ b/sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py
@@ -11,6 +11,7 @@
     HexRegField,
     NumberRegField,
     RegBitField,
+    RegBitsField,
     RegGroupField,
     StringRegField,
 )
@@ -195,6 +196,21 @@ def __init__(self, codes):
             NumberRegField(consts.PAGE_SUPPORT_ADVT_FIELD, self.getaddr(0x1, 142),
                 RegBitField(consts.VDM_SUPPORTED, 6),
             ),
+            NumberRegField(consts.TX_INPUT_EQ_MAX, self.getaddr(0x1, 153),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4))
+            ),
+            NumberRegField(consts.RX_OUTPUT_LEVEL_SUPPORT, self.getaddr(0x1, 153),
+                RegBitField(consts.RX_OUTPUT_LEVEL_0_SUPPORTED, 4),
+                RegBitField(consts.RX_OUTPUT_LEVEL_1_SUPPORTED, 5),
+                RegBitField(consts.RX_OUTPUT_LEVEL_2_SUPPORTED, 6),
+                RegBitField(consts.RX_OUTPUT_LEVEL_3_SUPPORTED, 7),
+            ),
+            NumberRegField(consts.RX_OUTPUT_EQ_PRE_CURSOR_MAX, self.getaddr(0x1, 154),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4))
+            ),
+            NumberRegField(consts.RX_OUTPUT_EQ_POST_CURSOR_MAX, self.getaddr(0x1, 154),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (4 , 8))
+            ),
             NumberRegField(consts.CTRLS_ADVT_FIELD, self.getaddr(0x1, 155),
                 RegBitField(consts.TX_DISABLE_SUPPORT_FIELD, 1),
                 size=2, format="<H"
@@ -461,6 +477,124 @@ def __init__(self, codes):
                 for lane in range(1, 9))
         )
 
+        self.SIGNAL_INTEGRITY_CTRL_ADVT = RegGroupField(consts.SIGNAL_INTEGRITY_CTRL_ADVT_FIELD,
+            NumberRegField(consts.TX_SI_CTRL_ADVT, self.getaddr(0x1, 161),
+                RegBitField(consts.TX_CDR_SUPPORT_FIELD, 0),
+                RegBitField(consts.TX_CDR_BYPASS_CTRL_FIELD, 1),
+                RegBitField(consts.TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD, 2),
+                RegBitField(consts.TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD, 3),
+                RegBitField(consts.TX_INPUT_EQ_FREEZE_SUPPORT_FIELD, 4),
+                RegBitField(consts.TX_INPUT_EQ_RECALL_BUF1_SUPPORT_FIELD, 5),
+                RegBitField(consts.TX_INPUT_EQ_RECALL_BUF2_SUPPORT_FIELD, 6),
+            ),
+            NumberRegField(consts.TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD, self.getaddr(0x1, 161),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (5 , 7))
+            ),
+
+            NumberRegField(consts.RX_SI_CTRL_ADVT, self.getaddr(0x1, 162),
+                RegBitField(consts.RX_CDR_SUPPORT_FIELD, 0),
+                RegBitField(consts.RX_CDR_BYPASS_CTRL_FIELD, 1),
+                RegBitField(consts.RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD, 2),
+                RegBitField(consts.RX_OUTPUT_EQ_PRE_CTRL_SUPPORT_FIELD, 3),
+                RegBitField(consts.RX_OUTPUT_EQ_POST_CTRL_SUPPORT_FIELD, 4),
+            ),
+            NumberRegField(consts.RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD, self.getaddr(0x1, 162),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (3 , 5))
+            ),
+
+        )
+
+        self.STAGED_CTRL0_TX_RX_CTRL = RegGroupField(consts.STAGED_CTRL0_TX_RX_CTRL_FIELD,
+            NumberRegField(consts.ADAPTIVE_INPUT_EQ_ENABLE_TX, self.getaddr(0x10, 153),
+                *(RegBitsField(consts.ADAPTIVE_INPUT_EQ_ENABLE_TX + str(lane), bitpos=(lane-1), ro=False, size=1)
+                for lane in range(1, 9))
+            ),
+            NumberRegField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX1_4, self.getaddr(0x10, 154),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX1, bitpos=0, ro=False, size=2),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX2, bitpos=2, ro=False, size=2),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX3, bitpos=4, ro=False, size=2),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX4, bitpos=6, ro=False, size=2),
+            ),
+            NumberRegField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX5_8, self.getaddr(0x10, 155),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX5, bitpos=0, ro=False, size=2),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX6, bitpos=2, ro=False, size=2),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX7, bitpos=4, ro=False, size=2),
+                RegBitsField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX8, bitpos=6, ro=False, size=2),
+            ),
+            NumberRegField(consts.FIXED_INPUT_EQ_TARGET_TX1_2, self.getaddr(0x10, 156),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX1, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX2, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.FIXED_INPUT_EQ_TARGET_TX3_4, self.getaddr(0x10, 157),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX3, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX4, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.FIXED_INPUT_EQ_TARGET_TX5_6, self.getaddr(0x10, 158),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX5, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX6, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.FIXED_INPUT_EQ_TARGET_TX7_8, self.getaddr(0x10, 159),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX7, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.FIXED_INPUT_EQ_TARGET_TX8, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.CDR_ENABLE_TX, self.getaddr(0x10, 160),
+                *(RegBitsField(consts.CDR_ENABLE_TX + str(lane), bitpos=(lane-1), ro=False, size=1)
+                for lane in range(1, 9))
+            ),
+            NumberRegField(consts.CDR_ENABLE_RX, self.getaddr(0x10, 161),
+                *(RegBitsField(consts.CDR_ENABLE_RX + str(lane), bitpos=(lane-1), ro=False, size=1)
+                for lane in range(1, 9))
+            ),
+            NumberRegField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX1_2, self.getaddr(0x10, 162),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX1, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX2, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX3_4, self.getaddr(0x10, 163),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX3, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX4, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX5_6, self.getaddr(0x10, 164),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX5, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX6, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX7_8, self.getaddr(0x10, 165),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX7, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX8, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX1_2, self.getaddr(0x10, 166),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX1, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX2, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX3_4, self.getaddr(0x10, 167),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX3, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX4, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX5_6, self.getaddr(0x10, 168),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX5, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX6, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX7_8, self.getaddr(0x10, 169),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX7, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX8, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_AMPLITUDE_TARGET_RX1_2, self.getaddr(0x10, 170),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX1, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX2, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_AMPLITUDE_TARGET_RX3_4, self.getaddr(0x10, 171),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX3, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX4, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_AMPLITUDE_TARGET_RX5_6, self.getaddr(0x10, 172),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX5, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX6, bitpos=4, ro=False, size=4)
+            ),
+            NumberRegField(consts.OUTPUT_AMPLITUDE_TARGET_RX7_8, self.getaddr(0x10, 173),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX7, bitpos=0, ro=False, size=4),
+                RegBitsField(consts.OUTPUT_AMPLITUDE_TARGET_RX8, bitpos=4, ro=False, size=4)
+            ),
+        )
+
         # TODO: add remaining fields
 
     def getaddr(self, page, offset, page_size=128):
diff --git a/tests/sonic_xcvr/test_cmis.py b/tests/sonic_xcvr/test_cmis.py
index a3cb0b345..5b072deb8 100644
--- a/tests/sonic_xcvr/test_cmis.py
+++ b/tests/sonic_xcvr/test_cmis.py
@@ -2196,24 +2196,120 @@ def test_set_application(self):
         self.api.xcvr_eeprom.write = MagicMock()
 
         self.api.xcvr_eeprom.write.call_count = 0
-        self.api.set_application(0x00, 1)
-        assert self.api.xcvr_eeprom.write.call_count == 1
+        self.api.set_application(0x00, 1, 0)
+        assert self.api.xcvr_eeprom.write.call_count == 0
 
         self.api.xcvr_eeprom.write.call_count = 0
-        self.api.set_application(0x01, 1)
-        assert self.api.xcvr_eeprom.write.call_count == 1 + 1
+        self.api.set_application(0x01, 1, 1)
+        assert self.api.xcvr_eeprom.write.call_count == 1
 
         self.api.xcvr_eeprom.write.call_count = 0
-        self.api.set_application(0x0f, 1)
-        assert self.api.xcvr_eeprom.write.call_count == 4 + 1
+        self.api.set_application(0x0f, 1, 1)
+        assert self.api.xcvr_eeprom.write.call_count == 4
 
         self.api.xcvr_eeprom.write.call_count = 0
-        self.api.set_application(0xff, 1)
-        assert self.api.xcvr_eeprom.write.call_count == 8 + 1
+        self.api.set_application(0xff, 1, 1)
+        assert self.api.xcvr_eeprom.write.call_count == 8
 
         self.api.xcvr_eeprom.write.call_count = 0
-        self.api.set_application(0x7fffffff, 1)
-        assert self.api.xcvr_eeprom.write.call_count == self.api.NUM_CHANNELS + 1
+        self.api.set_application(0x7fffffff, 1, 1)
+        assert self.api.xcvr_eeprom.write.call_count == self.api.NUM_CHANNELS
+
+    def test_set_module_si_eq_pre_settings(self):
+        optics_si_dict = { "OutputEqPreCursorTargetRx":{
+                             "OutputEqPreCursorTargetRx1":2, "OutputEqPreCursorTargetRx2":2, "OutputEqPreCursorTargetRx3":2, "OutputEqPreCursorTargetRx4":2,
+                             "OutputEqPreCursorTargetRx5":2, "OutputEqPreCursorTargetRx6":2, "OutputEqPreCursorTargetRx7":2, "OutputEqPreCursorTargetRx8":2 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1, 0x7]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0x01, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 1
+
+    def test_set_module_si_eq_en_settings(self):
+        optics_si_dict = { "AdaptiveInputEqEnableTx":{
+                             "AdaptiveInputEqEnableTx1": 2, "AdaptiveInputEqEnableTx2": 2, "AdaptiveInputEqEnableTx3": 2, "AdaptiveInputEqEnableTx4": 2,
+                             "AdaptiveInputEqEnableTx5": 2, "AdaptiveInputEqEnableTx6": 2, "AdaptiveInputEqEnableTx7": 2, "AdaptiveInputEqEnableTx8": 2,}
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1, 0x3]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0xff, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 8
+
+    def test_set_module_si_eq_recall_settings(self):
+        optics_si_dict = { "AdaptiveInputEqRecalledTx":{
+                             "AdaptiveInputEqRecalledTx1":1, "AdaptiveInputEqRecalledTx2":1, "AdaptiveInputEqRecalledTx3":1, "AdaptiveInputEqRecalledTx4":1,
+                             "AdaptiveInputEqRecalledTx5":1, "AdaptiveInputEqRecalledTx6":1, "AdaptiveInputEqRecalledTx7":1, "AdaptiveInputEqRecalledTx8":1 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0x0f, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 4
+
+    def test_set_module_si_eq_post_settings(self):
+        optics_si_dict = { "OutputEqPostCursorTargetRx":{
+                             "OutputEqPostCursorTargetRx1":2, "OutputEqPostCursorTargetRx2":2, "OutputEqPostCursorTargetRx3":2, "OutputEqPostCursorTargetRx4":2,
+                             "OutputEqPostCursorTargetRx5":2, "OutputEqPostCursorTargetRx6":2, "OutputEqPostCursorTargetRx7":2, "OutputEqPostCursorTargetRx8":2 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1, 0x7]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0x01, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 1
+
+    def test_set_module_si_fixed_en_settings(self):
+        optics_si_dict = { "FixedInputEqTargetTx":{
+                             "FixedInputEqTargetTx1":1, "FixedInputEqTargetTx2":1, "FixedInputEqTargetTx3":1, "FixedInputEqTargetTx4":1,
+                             "FixedInputEqTargetTx5":1, "FixedInputEqTargetTx6":1, "FixedInputEqTargetTx7":1, "FixedInputEqTargetTx8":1 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1, 0x1]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0xff, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 8
+
+    def test_set_module_cdr_enable_tx_settings(self):
+        optics_si_dict = { "CDREnableTx":{
+                              "CDREnableTx1":1, "CDREnableTx2":1, "CDREnableTx3":1, "CDREnableTx4":1,
+                              "CDREnableTx5":0, "CDREnableTx6":0, "CDREnableTx7":0, "CDREnableTx8":0 }
+                        }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0x0f, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 4
+
+    def test_set_module_cdr_enable_rx_settings(self):
+        optics_si_dict = { "CDREnableRx":{
+                              "CDREnableRx1":1, "CDREnableRx2":1, "CDREnableRx3":1, "CDREnableRx4":1,
+                              "CDREnableRx5":0, "CDREnableRx6":0, "CDREnableRx7":0, "CDREnableRx8":0 }
+                        }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0xff, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 8
+
+    def test_set_module_OutputAmplitudeTargetRx_settings(self):
+        optics_si_dict = { "OutputAmplitudeTargetRx":{
+                             "OutputAmplitudeTargetRx1":1, "OutputAmplitudeTargetRx2":1, "OutputAmplitudeTargetRx3":1, "OutputAmplitudeTargetRx4":1,
+                             "OutputAmplitudeTargetRx5":1, "OutputAmplitudeTargetRx6":1, "OutputAmplitudeTargetRx7":1, "OutputAmplitudeTargetRx8":1 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [0x1, 0x7]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.stage_custom_si_settings(0x0f, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 4
 
     def test_get_error_description(self):
         self.api.get_module_state = MagicMock()