From 0f898e7b401d3eff784d1b026405eefa91a0dea4 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 28 May 2024 18:49:40 +0200 Subject: [PATCH 1/2] [rtl] relocate f files --- rtl/core/cpu_hdl_files.f | 15 ----------- rtl/core/processor_hdl_files.f | 48 ---------------------------------- rtl/cpu_hdl_files.f | 15 +++++++++++ rtl/processor_hdl_files.f | 48 ++++++++++++++++++++++++++++++++++ 4 files changed, 63 insertions(+), 63 deletions(-) delete mode 100644 rtl/core/cpu_hdl_files.f delete mode 100644 rtl/core/processor_hdl_files.f create mode 100644 rtl/cpu_hdl_files.f create mode 100644 rtl/processor_hdl_files.f diff --git a/rtl/core/cpu_hdl_files.f b/rtl/core/cpu_hdl_files.f deleted file mode 100644 index 6f090757b..000000000 --- a/rtl/core/cpu_hdl_files.f +++ /dev/null @@ -1,15 +0,0 @@ -neorv32_package.vhd -neorv32_fifo.vhd -neorv32_cpu_decompressor.vhd -neorv32_cpu_control.vhd -neorv32_cpu_regfile.vhd -neorv32_cpu_cp_shifter.vhd -neorv32_cpu_cp_muldiv.vhd -neorv32_cpu_cp_bitmanip.vhd -neorv32_cpu_cp_fpu.vhd -neorv32_cpu_cp_cfu.vhd -neorv32_cpu_cp_cond.vhd -neorv32_cpu_alu.vhd -neorv32_cpu_lsu.vhd -neorv32_cpu_pmp.vhd -neorv32_cpu.vhd diff --git a/rtl/core/processor_hdl_files.f b/rtl/core/processor_hdl_files.f deleted file mode 100644 index 4fe7ecd81..000000000 --- a/rtl/core/processor_hdl_files.f +++ /dev/null @@ -1,48 +0,0 @@ -neorv32_package.vhd -neorv32_clockgate.vhd -neorv32_fifo.vhd -neorv32_cpu_decompressor.vhd -neorv32_cpu_control.vhd -neorv32_cpu_regfile.vhd -neorv32_cpu_cp_shifter.vhd -neorv32_cpu_cp_muldiv.vhd -neorv32_cpu_cp_bitmanip.vhd -neorv32_cpu_cp_fpu.vhd -neorv32_cpu_cp_cfu.vhd -neorv32_cpu_cp_cond.vhd -neorv32_cpu_alu.vhd -neorv32_cpu_lsu.vhd -neorv32_cpu_pmp.vhd -neorv32_cpu.vhd -neorv32_intercon.vhd -neorv32_cache.vhd -neorv32_dma.vhd -neorv32_imem.entity.vhd -neorv32_dmem.entity.vhd -neorv32_boot_rom.vhd -neorv32_xip.vhd -neorv32_xbus.vhd -neorv32_cfs.vhd -neorv32_sdi.vhd -neorv32_gpio.vhd -neorv32_wdt.vhd -neorv32_mtime.vhd -neorv32_uart.vhd -neorv32_spi.vhd -neorv32_twi.vhd -neorv32_pwm.vhd -neorv32_trng.vhd -neorv32_neoled.vhd -neorv32_xirq.vhd -neorv32_gptmr.vhd -neorv32_onewire.vhd -neorv32_slink.vhd -neorv32_crc.vhd -neorv32_sysinfo.vhd -neorv32_debug_dtm.vhd -neorv32_debug_dm.vhd -neorv32_top.vhd -neorv32_bootloader_image.vhd -neorv32_application_image.vhd -mem/neorv32_imem.default.vhd -mem/neorv32_dmem.default.vhd diff --git a/rtl/cpu_hdl_files.f b/rtl/cpu_hdl_files.f new file mode 100644 index 000000000..6d7308e1a --- /dev/null +++ b/rtl/cpu_hdl_files.f @@ -0,0 +1,15 @@ +rtl/neorv32_package.vhd +rtl/neorv32_fifo.vhd +rtl/neorv32_cpu_decompressor.vhd +rtl/neorv32_cpu_control.vhd +rtl/neorv32_cpu_regfile.vhd +rtl/neorv32_cpu_cp_shifter.vhd +rtl/neorv32_cpu_cp_muldiv.vhd +rtl/neorv32_cpu_cp_bitmanip.vhd +rtl/neorv32_cpu_cp_fpu.vhd +rtl/neorv32_cpu_cp_cfu.vhd +rtl/neorv32_cpu_cp_cond.vhd +rtl/neorv32_cpu_alu.vhd +rtl/neorv32_cpu_lsu.vhd +rtl/neorv32_cpu_pmp.vhd +rtl/neorv32_cpu.vhd diff --git a/rtl/processor_hdl_files.f b/rtl/processor_hdl_files.f new file mode 100644 index 000000000..6e9d03f96 --- /dev/null +++ b/rtl/processor_hdl_files.f @@ -0,0 +1,48 @@ +rtl/neorv32_package.vhd +rtl/neorv32_clockgate.vhd +rtl/neorv32_fifo.vhd +rtl/neorv32_cpu_decompressor.vhd +rtl/neorv32_cpu_control.vhd +rtl/neorv32_cpu_regfile.vhd +rtl/neorv32_cpu_cp_shifter.vhd +rtl/neorv32_cpu_cp_muldiv.vhd +rtl/neorv32_cpu_cp_bitmanip.vhd +rtl/neorv32_cpu_cp_fpu.vhd +rtl/neorv32_cpu_cp_cfu.vhd +rtl/neorv32_cpu_cp_cond.vhd +rtl/neorv32_cpu_alu.vhd +rtl/neorv32_cpu_lsu.vhd +rtl/neorv32_cpu_pmp.vhd +rtl/neorv32_cpu.vhd +rtl/neorv32_intercon.vhd +rtl/neorv32_cache.vhd +rtl/neorv32_dma.vhd +rtl/neorv32_imem.entity.vhd +rtl/neorv32_dmem.entity.vhd +rtl/neorv32_boot_rom.vhd +rtl/neorv32_xip.vhd +rtl/neorv32_xbus.vhd +rtl/neorv32_cfs.vhd +rtl/neorv32_sdi.vhd +rtl/neorv32_gpio.vhd +rtl/neorv32_wdt.vhd +rtl/neorv32_mtime.vhd +rtl/neorv32_uart.vhd +rtl/neorv32_spi.vhd +rtl/neorv32_twi.vhd +rtl/neorv32_pwm.vhd +rtl/neorv32_trng.vhd +rtl/neorv32_neoled.vhd +rtl/neorv32_xirq.vhd +rtl/neorv32_gptmr.vhd +rtl/neorv32_onewire.vhd +rtl/neorv32_slink.vhd +rtl/neorv32_crc.vhd +rtl/neorv32_sysinfo.vhd +rtl/neorv32_debug_dtm.vhd +rtl/neorv32_debug_dm.vhd +rtl/neorv32_top.vhd +rtl/neorv32_bootloader_image.vhd +rtl/neorv32_application_image.vhd +rtl/mem/neorv32_imem.default.vhd +rtl/mem/neorv32_dmem.default.vhd From 5a5a266b9f63f28e3befa251abba19bdef2139e0 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 28 May 2024 18:49:58 +0200 Subject: [PATCH 2/2] update f-files documentation --- docs/datasheet/overview.adoc | 57 +++++++++++++++--------------------- rtl/README.md | 6 +++- 2 files changed, 29 insertions(+), 34 deletions(-) diff --git a/docs/datasheet/overview.adoc b/docs/datasheet/overview.adoc index 642e75b01..5c01b9ca2 100644 --- a/docs/datasheet/overview.adoc +++ b/docs/datasheet/overview.adoc @@ -169,58 +169,53 @@ neorv32 - Project home folder All necessary VHDL hardware description files are located in the project's `rtl/core` folder. The top entity of the entire processor including all the required configuration generics is `neorv32_top.vhd`. -.Compile Order +.Compile Order / File-List Files [IMPORTANT] Most of the RTL sources use **entity instantiation**. Hence, the RTL compile order might be relevant. -The list below shows the hierarchical compile order srarting at the top. +Therefore, two file list files (`*.f`) are provided in the `rtl` folder that list all required rtl files +for the CPU core and for the entire processor and also represent their recommended compile order. .VHDL Library [IMPORTANT] All core VHDL files from the list below have to be assigned to a **new library** named `neorv32`. ................................... -┌neorv32_package.vhd - Processor/CPU main VHDL package file -├neorv32_clockgate.vhd - Generic clock gating switch -├neorv32_fifo.vhd - Generic FIFO component +neorv32_top.vhd - NEORV32 PROCESSOR TOP ENTITY │ -│ ┌neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.) -│ ├neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor (Zxcfu ext.) -│ ├neorv32_cpu_cp_cond.vhd - Integer conditional operations (Zicond ext.) -│ ├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.) -│ ├neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor (base ISA) -│ ├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M ext.) -│ │ -│┌neorv32_cpu_alu.vhd - Arithmetic/logic unit -│├neorv32_cpu_pmp.vhd - Physical memory protection unit (Smpmp ext.) -│├neorv32_cpu_lsu.vhd - Load/store unit -││ ┌neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.) +├neorv32_cpu.vhd - NEORV32 CPU TOP ENTIT +│├neorv32_cpu_alu.vhd - Arithmetic/logic unit +││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.) +││├neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor (Zxcfu ext.) +││├neorv32_cpu_cp_cond.vhd - Integer conditional operations (Zicond ext.) +││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.) +││├neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor (base ISA) +││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M ext.) │├neorv32_cpu_control.vhd - CPU control, exception system and CSRs -│├neorv32_cpu_regfile.vhd - Data register file -││ -├neorv32_cpu.vhd - NEORV32 CPU TOP ENTITY -│ -├mem/neorv32_dmem.default.vhd - *Default* data memory (architecture-only) -├mem/neorv32_imem.default.vhd - *Default* instruction memory (architecture-only) +││└neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.) +│├neorv32_cpu_lsu.vhd - Load/store unit +│├neorv32_cpu_pmp.vhd - Physical memory protection unit (Smpmp ext.) +│└neorv32_cpu_regfile.vhd - Data register file │ -│┌neorv32_bootloader_image.vhd - Bootloader ROM memory image ├neorv32_boot_rom.vhd - Bootloader ROM -│ -│┌neor32_application_image.vhd - IMEM application initialization image -├neorv32_imem.entity.vhd - Processor-internal instruction memory (entity-only!) -│ +│└neorv32_bootloader_image.vhd - Bootloader ROM memory image ├neorv32_cfs.vhd - Custom functions subsystem +├neorv32_clockgate.vhd - Generic clock gating switch ├neorv32_crc.vhd - Cyclic redundancy check unit ├neorv32_cache.vhd - Generic cache module ├neorv32_debug_dm.vhd - on-chip debugger: debug module ├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module ├neorv32_dma.vhd - Direct memory access controller ├neorv32_dmem.entity.vhd - Processor-internal data memory (entity-only!) +├neorv32_fifo.vhd - Generic FIFO component ├neorv32_gpio.vhd - General purpose input/output port unit ├neorv32_gptmr.vhd - General purpose 32-bit timer +├neorv32_imem.entity.vhd - Processor-internal instruction memory (entity-only!) +│└neor32_application_image.vhd - IMEM application initialization image ├neorv32_intercon.vhd - SoC bus infrastructure ├neorv32_mtime.vhd - Machine system timer ├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface ├neorv32_onewire.vhd - One-Wire serial interface controller +├neorv32_package.vhd - Main VHDL package file ├neorv32_pwm.vhd - Pulse-width modulation controller ├neorv32_sdi.vhd - Serial data interface controller (SPI device) ├neorv32_slink.vhd - Stream link interface @@ -234,7 +229,8 @@ All core VHDL files from the list below have to be assigned to a **new library** ├neorv32_xip.vhd - Execute in place module ├neorv32_xirq.vhd - External interrupt controller │ -neorv32_top.vhd - NEORV32 PROCESSOR TOP ENTITY +├mem/neorv32_dmem.default.vhd - *Default* data memory (architecture-only!) +└mem/neorv32_imem.default.vhd - *Default* instruction memory (architecture-only!) ................................... .Processor-Internal Memories @@ -246,11 +242,6 @@ _platform independent_ memory design (inferring embedded memory blocks). You can source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping and/or timing. -.File-List / Compile-Order Files -[TIP] -RTL file lists for the entire processor and for the CPU only are available in the `rtl` folder as -`processor_hdl_files.f` and `cpu_hdl_files.f`, respectively. Theses files also define the actual compile order. - <<< diff --git a/rtl/README.md b/rtl/README.md index 70bc32fbd..ed233852c 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -9,10 +9,14 @@ is [`neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/core/n > [!IMPORTANT] > The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem) -contains different _platform-agnostic_ VHDL architectures of the processor-internal instruction and +contains different _platform-agnostic_ VHDL architectures of the processor-internal instruction and data memories (IMEM & DMEM). Make sure to add only **one** of each modules to the project's HDL file list. However, these default files can also be replaced by optimized technology-specific memory modules. +> [!TIP] +> Two file list files (`*.f`) are provided that list all required rtl files for the CPU core and +for the entire processor including their recommended compile order. + #### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates) Contains pre-configured SoC templates that instantiate the processor's top entity from `core`.