From 85753b2a740aeb1f983d14a0eab49698a9586dc6 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Mon, 11 Mar 2024 17:26:42 +0100
Subject: [PATCH 1/6] [figures] update Wishbone bus examples

---
 docs/figures/wishbone_classic_read.png     | Bin 24720 -> 20153 bytes
 docs/figures/wishbone_pipelined_write.png  | Bin 26386 -> 21838 bytes
 docs/sources/wishbone_classic_read.json    |   2 --
 docs/sources/wishbone_pipelined_write.json |   2 --
 4 files changed, 4 deletions(-)

diff --git a/docs/figures/wishbone_classic_read.png b/docs/figures/wishbone_classic_read.png
index 8128f04dfac95897d074aa24d734d43eeb335455..002c9bcfe1d9cb2d847ae78b06f3732e33f1ff45 100644
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diff --git a/docs/sources/wishbone_classic_read.json b/docs/sources/wishbone_classic_read.json
index ef1e966b2..39e996b1d 100644
--- a/docs/sources/wishbone_classic_read.json
+++ b/docs/sources/wishbone_classic_read.json
@@ -1,6 +1,5 @@
 {signal: [
   {name: 'clk',       wave: 'p....|...'},
-  {name: 'wb_tag_o',  wave: 'x3...|.x.', data: ['Tag']},
   {name: 'wb_adr_o',  wave: 'x3...|.x.', data: ['Address']},
   {name: 'wb_dat_i',  wave: 'x....|3x.', data: ['rdata']},
   {name: 'wb_dat_o',  wave: 'x....|.x.', data: ['Wdata']},
@@ -8,7 +7,6 @@
   {name: 'wb_sel_o',  wave: 'x....|.x.', data: ['Byte_enable']},
   {name: 'wb_stb_o',  wave: '01...|.0.'},
   {name: 'wb_cyc_o',  wave: '01...|.0.'},
-  {name: 'wb_lock_o', wave: '0....|...'},
   {name: 'wb_ack_i',  wave: '0....|10.'},
   {name: 'wb_err_i',  wave: '0....|...'},
 ]}
diff --git a/docs/sources/wishbone_pipelined_write.json b/docs/sources/wishbone_pipelined_write.json
index 6f6344889..74adc6502 100644
--- a/docs/sources/wishbone_pipelined_write.json
+++ b/docs/sources/wishbone_pipelined_write.json
@@ -1,6 +1,5 @@
 {signal: [
   {name: 'clk',       wave: 'p....|...'},
-  {name: 'wb_tag_o',  wave: 'x3...|.x.', data: ['Tag']},
   {name: 'wb_adr_o',  wave: 'x3...|.x.', data: ['Address']},
   {name: 'wb_dat_i',  wave: 'x....|.x.'},
   {name: 'wb_dat_o',  wave: 'x3...|.x.', data: ['Wdata']},
@@ -8,7 +7,6 @@
   {name: 'wb_sel_o',  wave: 'x3...|.x.', data: ['Byte_enable']},
   {name: 'wb_stb_o',  wave: '010..|...'},
   {name: 'wb_cyc_o',  wave: '01...|.0.'},
-  {name: 'wb_lock_o', wave: '0....|...'},
   {name: 'wb_ack_i',  wave: '0....|10.'},
   {name: 'wb_err_i',  wave: '0....|...'},
 ]}

From 4f0346b236131ac2ee4363bbac591cdf488f50b5 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Mon, 11 Mar 2024 17:27:18 +0100
Subject: [PATCH 2/6] [docs] remove Wishbone Tag signal

---
 docs/datasheet/soc.adoc          |  2 --
 docs/datasheet/soc_wishbone.adoc | 16 ++--------------
 2 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
index 277797f81..444639805 100644
--- a/docs/datasheet/soc.adoc
+++ b/docs/datasheet/soc.adoc
@@ -71,7 +71,6 @@ bits/channels are hardwired to zero.
 [NOTE]
 Some interfaces (like the TWI and the 1-Wire bus) require tri-state drivers in the designs top module.
 
-
 .NEORV32 Processor Signal List
 [cols="<3,^1,^1,^1,<8"]
 [options="header",grid="rows"]
@@ -87,7 +86,6 @@ Some interfaces (like the TWI and the 1-Wire bus) require tri-state drivers in t
 | `jtag_tdo_o`     |  1 | out |   -   | serial data output
 | `jtag_tms_i`     |  1 |  in | `'L'` | mode select
 5+^| **<<_processor_external_memory_interface_wishbone>>**
-| `wb_tag_o`       |  3 | out |   -   |  tag (access type identifier)
 | `wb_adr_o`       | 32 | out |   -   |  destination address
 | `wb_dat_i`       | 32 |  in | `'L'` |  write data
 | `wb_dat_o`       | 32 | out |   -   |  read data
diff --git a/docs/datasheet/soc_wishbone.adoc b/docs/datasheet/soc_wishbone.adoc
index 22da1e944..07150735b 100644
--- a/docs/datasheet/soc_wishbone.adoc
+++ b/docs/datasheet/soc_wishbone.adoc
@@ -7,8 +7,7 @@
 |=======================
 | Hardware source file(s): | neorv32_wishbone.vhd |
 | Software driver file(s): | none                 | _implicitly used_
-| Top entity port:         | `wb_tag_o`  | request tag output (3-bit)
-|                          | `wb_adr_o`  | address output (32-bit)
+| Top entity port:         | `wb_adr_o`  | address output (32-bit)
 |                          | `wb_dat_i`  | data input (32-bit)
 |                          | `wb_dat_o`  | data output (32-bit)
 |                          | `wb_we_o`   | write enable (1-bit)
@@ -17,14 +16,12 @@
 |                          | `wb_cyc_o`  | valid cycle (1-bit)
 |                          | `wb_ack_i`  | acknowledge (1-bit)
 |                          | `wb_err_i`  | bus error (1-bit)
-|                          | `fence_o`   | an executed `fence` instruction
-|                          | `fencei_o`  | an executed `fence.i` instruction
 | Configuration generics:  | `MEM_EXT_EN`         | enable external memory interface when `true`
 |                          | `MEM_EXT_TIMEOUT`    | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
 |                          | `MEM_EXT_PIPE_MODE`  | when `false` (default): classic/standard Wishbone protocol; when `true`: pipelined Wishbone protocol
 |                          | `MEM_EXT_BIG_ENDIAN` | byte-order (Endianness) of external memory interface; `true`=BIG, `false`=little (default)
 |                          | `MEM_EXT_ASYNC_RX`   | use registered RX path when `false` (default); use async/direct RX path when `true`
-|                          | `MEM_EXT_ASYNC_TX_`  | use registered TX path when `false` (default); use async/direct TX path when `true`
+|                          | `MEM_EXT_ASYNC_TX`   | use registered TX path when `false` (default); use async/direct TX path when `true`
 | CPU interrupts:          | none |
 |=======================
 
@@ -85,15 +82,6 @@ or terminate (via `wb_err_i`) the transfer within `MEM_EXT_TIMEOUT` clock cycles
 setting `wb_cyc_o` low again and a CPU load/store/instruction fetch bus access fault exception is raised.
 
 
-**Wishbone Tag**
-
-The 3-bit wishbone `wb_tag_o` signal provides additional information regarding the access type:
-
-* `wb_tag_o(0)`: `1` = privileged access (CPU is in machine mode); `0` = unprivileged access (CPU is not in machine mode)
-* `wb_tag_o(1)`: always zero
-* `wb_tag_o(2)`: `1` = instruction fetch access, `0` = data access
-
-
 **Endianness**
 
 The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection

From 933b842e7172d8d3c63dee30a06ff7797f1fd85b Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Mon, 11 Mar 2024 17:29:27 +0100
Subject: [PATCH 3/6] [rtl] :warning: remove Wishbone tag signal

---
 rtl/core/neorv32_package.vhd                         |  3 +--
 rtl/core/neorv32_wishbone.vhd                        | 12 ------------
 .../neorv32_SystemTop_AvalonMM.vhd                   |  2 --
 .../neorv32_SystemTop_axi4lite.vhd                   | 12 ++----------
 .../neorv32_litex_core_complex.vhd                   |  1 -
 sim/neorv32_tb.vhd                                   |  6 ------
 sim/simple/neorv32_tb.simple.vhd                     |  6 ------
 7 files changed, 3 insertions(+), 39 deletions(-)

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
index 00ca301f2..b5bec914f 100644
--- a/rtl/core/neorv32_package.vhd
+++ b/rtl/core/neorv32_package.vhd
@@ -53,7 +53,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090602"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090603"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -843,7 +843,6 @@ package neorv32_package is
       jtag_tdo_o     : out std_ulogic;
       jtag_tms_i     : in  std_ulogic := 'L';
       -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-      wb_tag_o       : out std_ulogic_vector(02 downto 0);
       wb_adr_o       : out std_ulogic_vector(31 downto 0);
       wb_dat_i       : in  std_ulogic_vector(31 downto 0) := (others => 'L');
       wb_dat_o       : out std_ulogic_vector(31 downto 0);
diff --git a/rtl/core/neorv32_wishbone.vhd b/rtl/core/neorv32_wishbone.vhd
index fd8a2e69b..1a29fb2da 100644
--- a/rtl/core/neorv32_wishbone.vhd
+++ b/rtl/core/neorv32_wishbone.vhd
@@ -60,7 +60,6 @@ entity neorv32_wishbone is
     bus_req_i : in  bus_req_t;  -- bus request
     bus_rsp_o : out bus_rsp_t;  -- bus response
     --
-    wb_tag_o  : out std_ulogic_vector(02 downto 0); -- request tag
     wb_adr_o  : out std_ulogic_vector(31 downto 0); -- address
     wb_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
     wb_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
@@ -93,8 +92,6 @@ architecture neorv32_wishbone_rtl of neorv32_wishbone is
     ack      : std_ulogic;
     err      : std_ulogic;
     timeout  : std_ulogic_vector(index_size_f(BUS_TIMEOUT) downto 0);
-    src      : std_ulogic;
-    priv     : std_ulogic;
   end record;
   signal ctrl    : ctrl_t;
   signal stb_int : std_ulogic;
@@ -147,8 +144,6 @@ begin
       ctrl.timeout  <= (others => '0');
       ctrl.ack      <= '0';
       ctrl.err      <= '0';
-      ctrl.src      <= '0';
-      ctrl.priv     <= '0';
     elsif rising_edge(clk_i) then
       -- defaults --
       ctrl.state_ff <= ctrl.state;
@@ -164,8 +159,6 @@ begin
           -- buffer (and gate) all outgoing signals --
           ctrl.we    <= bus_req_i.rw;
           ctrl.adr   <= bus_req_i.addr;
-          ctrl.src   <= bus_req_i.src;
-          ctrl.priv  <= bus_req_i.priv;
           ctrl.wdat  <= end_wdata;
           ctrl.sel   <= end_byteen;
           ctrl.state <= '1';
@@ -205,11 +198,6 @@ begin
   bus_rsp_o.ack  <= ctrl.ack when (async_rx_c = false) else ack_gated;
   bus_rsp_o.err  <= ctrl.err when (async_rx_c = false) else err_gated;
 
-  -- wishbone interface --
-  wb_tag_o(0) <= bus_req_i.priv when (ASYNC_TX = true) else ctrl.priv; -- 0 = unprivileged (U-mode), 1 = privileged (M-mode)
-  wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
-  wb_tag_o(2) <= bus_req_i.src when (ASYNC_TX = true) else ctrl.src; -- 0 = data access, 1 = instruction access
-
   stb_int <=  bus_req_i.stb                when (ASYNC_TX = true) else (ctrl.state and (not ctrl.state_ff));
   cyc_int <= (bus_req_i.stb or ctrl.state) when (ASYNC_TX = true) else  ctrl.state;
 
diff --git a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
index 606a9c2ce..91b88fc82 100644
--- a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
+++ b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
@@ -212,7 +212,6 @@ end neorv32_top_avalonmm;
 architecture neorv32_top_avalonmm_rtl of neorv32_top_avalonmm is
 
   -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-  signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag
   signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address
   signal wb_dat_i : std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
   signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data
@@ -335,7 +334,6 @@ begin
     jtag_tms_i => jtag_tms_i,
 
     -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-    wb_tag_o => wb_tag_o,
     wb_adr_o => wb_adr_o,
     wb_dat_i => wb_dat_i,
     wb_dat_o => wb_dat_o,
diff --git a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
index 908e3eb10..537db2f3f 100644
--- a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
+++ b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
@@ -321,7 +321,6 @@ architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is
     cyc : std_ulogic; -- valid cycle
     ack : std_ulogic; -- transfer acknowledge
     err : std_ulogic; -- transfer error
-    tag : std_ulogic_vector(02 downto 0); -- tag
   end record;
   signal wb_core : wb_bus_t;
 
@@ -447,7 +446,6 @@ begin
     jtag_tdo_o     => jtag_tdo_o_int,  -- serial data output
     jtag_tms_i     => jtag_tms_i_int,  -- mode select
     -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-    wb_tag_o       => wb_core.tag,     -- tag
     wb_adr_o       => wb_core.adr,     -- address
     wb_dat_i       => wb_core.di,      -- read data
     wb_dat_o       => wb_core.do,      -- write data
@@ -618,10 +616,7 @@ begin
   -- AXI4-Lite Read Address Channel --
   m_axi_araddr  <= std_logic_vector(wb_core.adr);
   m_axi_arvalid <= std_logic((wb_core.cyc and (not wb_core.we)) and (not ctrl.radr_received));
---m_axi_arprot  <= "000"; -- recommended by AMD
-  m_axi_arprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access
-  m_axi_arprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access
-  m_axi_arprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access
+  m_axi_arprot  <= "000"; -- recommended by AMD
 
   -- AXI4-Lite Read Data Channel --
   m_axi_rready <= std_logic(wb_core.cyc and (not wb_core.we));
@@ -632,10 +627,7 @@ begin
   -- AXI4-Lite Write Address Channel --
   m_axi_awaddr  <= std_logic_vector(wb_core.adr);
   m_axi_awvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wadr_received));
---m_axi_awprot  <= "000"; -- recommended by AMD
-  m_axi_awprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access
-  m_axi_awprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access
-  m_axi_awprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access
+  m_axi_awprot  <= "000"; -- recommended by AMD
 
   -- AXI4-Lite Write Data Channel --
   m_axi_wdata  <= std_logic_vector(wb_core.do);
diff --git a/rtl/system_integration/neorv32_litex_core_complex.vhd b/rtl/system_integration/neorv32_litex_core_complex.vhd
index 376484d5c..9172692c4 100644
--- a/rtl/system_integration/neorv32_litex_core_complex.vhd
+++ b/rtl/system_integration/neorv32_litex_core_complex.vhd
@@ -217,7 +217,6 @@ begin
     jtag_tdo_o  => jtag_tdo_o,  -- serial data output
     jtag_tms_i  => jtag_tms_i,  -- mode select
     -- Wishbone bus interface --
-    wb_tag_o    => open,        -- request tag
     wb_adr_o    => wb_adr_o,    -- address
     wb_dat_i    => wb_dat_i,    -- read data
     wb_dat_o    => wb_dat_o,    -- write data
diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd
index 123c643f2..a8d045f43 100644
--- a/sim/neorv32_tb.vhd
+++ b/sim/neorv32_tb.vhd
@@ -140,7 +140,6 @@ architecture neorv32_tb_rtl of neorv32_tb is
     cyc   : std_ulogic; -- valid cycle
     ack   : std_ulogic; -- transfer acknowledge
     err   : std_ulogic; -- transfer error
-    tag   : std_ulogic_vector(02 downto 0); -- request tag
   end record;
   signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
 
@@ -322,7 +321,6 @@ begin
     jtag_tdo_o     => open,            -- serial data output
     jtag_tms_i     => '0',             -- mode select
     -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-    wb_tag_o       => wb_cpu.tag,      -- request tag
     wb_adr_o       => wb_cpu.addr,     -- address
     wb_dat_i       => wb_cpu.rdata,    -- read data
     wb_dat_o       => wb_cpu.wdata,    -- write data
@@ -439,28 +437,24 @@ begin
   wb_mem_a.wdata <= wb_cpu.wdata;
   wb_mem_a.we    <= wb_cpu.we;
   wb_mem_a.sel   <= wb_cpu.sel;
-  wb_mem_a.tag   <= wb_cpu.tag;
   wb_mem_a.cyc   <= wb_cpu.cyc;
 
   wb_mem_b.addr  <= wb_cpu.addr;
   wb_mem_b.wdata <= wb_cpu.wdata;
   wb_mem_b.we    <= wb_cpu.we;
   wb_mem_b.sel   <= wb_cpu.sel;
-  wb_mem_b.tag   <= wb_cpu.tag;
   wb_mem_b.cyc   <= wb_cpu.cyc;
 
   wb_mem_c.addr  <= wb_cpu.addr;
   wb_mem_c.wdata <= wb_cpu.wdata;
   wb_mem_c.we    <= wb_cpu.we;
   wb_mem_c.sel   <= wb_cpu.sel;
-  wb_mem_c.tag   <= wb_cpu.tag;
   wb_mem_c.cyc   <= wb_cpu.cyc;
 
   wb_irq.addr    <= wb_cpu.addr;
   wb_irq.wdata   <= wb_cpu.wdata;
   wb_irq.we      <= wb_cpu.we;
   wb_irq.sel     <= wb_cpu.sel;
-  wb_irq.tag     <= wb_cpu.tag;
   wb_irq.cyc     <= wb_cpu.cyc;
 
   -- CPU read-back signals (no mux here since peripherals have "output gates") --
diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd
index a4c72c99c..6fce5188f 100644
--- a/sim/simple/neorv32_tb.simple.vhd
+++ b/sim/simple/neorv32_tb.simple.vhd
@@ -131,7 +131,6 @@ architecture neorv32_tb_simple_rtl of neorv32_tb_simple is
     cyc   : std_ulogic; -- valid cycle
     ack   : std_ulogic; -- transfer acknowledge
     err   : std_ulogic; -- transfer error
-    tag   : std_ulogic_vector(02 downto 0); -- request tag
   end record;
   signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
 
@@ -270,7 +269,6 @@ begin
     jtag_tdo_o     => open,            -- serial data output
     jtag_tms_i     => '0',             -- mode select
     -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-    wb_tag_o       => wb_cpu.tag,      -- request tag
     wb_adr_o       => wb_cpu.addr,     -- address
     wb_dat_i       => wb_cpu.rdata,    -- read data
     wb_dat_o       => wb_cpu.wdata,    -- write data
@@ -398,28 +396,24 @@ begin
   wb_mem_a.wdata <= wb_cpu.wdata;
   wb_mem_a.we    <= wb_cpu.we;
   wb_mem_a.sel   <= wb_cpu.sel;
-  wb_mem_a.tag   <= wb_cpu.tag;
   wb_mem_a.cyc   <= wb_cpu.cyc;
 
   wb_mem_b.addr  <= wb_cpu.addr;
   wb_mem_b.wdata <= wb_cpu.wdata;
   wb_mem_b.we    <= wb_cpu.we;
   wb_mem_b.sel   <= wb_cpu.sel;
-  wb_mem_b.tag   <= wb_cpu.tag;
   wb_mem_b.cyc   <= wb_cpu.cyc;
 
   wb_mem_c.addr  <= wb_cpu.addr;
   wb_mem_c.wdata <= wb_cpu.wdata;
   wb_mem_c.we    <= wb_cpu.we;
   wb_mem_c.sel   <= wb_cpu.sel;
-  wb_mem_c.tag   <= wb_cpu.tag;
   wb_mem_c.cyc   <= wb_cpu.cyc;
 
   wb_irq.addr    <= wb_cpu.addr;
   wb_irq.wdata   <= wb_cpu.wdata;
   wb_irq.we      <= wb_cpu.we;
   wb_irq.sel     <= wb_cpu.sel;
-  wb_irq.tag     <= wb_cpu.tag;
   wb_irq.cyc     <= wb_cpu.cyc;
 
   -- CPU read-back signals (no mux here since peripherals have "output gates") --

From 473327a0c5886c4c3c174a17b5692bc1d849786d Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Mon, 11 Mar 2024 17:33:00 +0100
Subject: [PATCH 4/6] [top] minor rtl / coding style edits

---
 rtl/core/neorv32_top.vhd | 176 +++++++++++++++++++--------------------
 1 file changed, 88 insertions(+), 88 deletions(-)

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
index b8ed22fbb..f4e0c8b6e 100644
--- a/rtl/core/neorv32_top.vhd
+++ b/rtl/core/neorv32_top.vhd
@@ -171,7 +171,6 @@ entity neorv32_top is
     jtag_tms_i     : in  std_ulogic := 'L'; -- mode select
 
     -- Wishbone bus interface (available if MEM_EXT_EN = true) --
-    wb_tag_o       : out std_ulogic_vector(02 downto 0); -- request tag
     wb_adr_o       : out std_ulogic_vector(31 downto 0); -- address
     wb_dat_i       : in  std_ulogic_vector(31 downto 0) := (others => 'L'); -- read data
     wb_dat_o       : out std_ulogic_vector(31 downto 0); -- write data
@@ -292,9 +291,10 @@ architecture neorv32_top_rtl of neorv32_top is
   signal clk_gen                   : std_ulogic_vector(07 downto 0);
   signal clk_gen_en, clk_gen_en_ff : std_ulogic;
   --
-  type cg_en_t is record
-    wdt, uart0, uart1, spi, twi, pwm, cfs, neoled, gptmr, xip, onewire : std_ulogic;
-  end record;
+  type cg_en_enum_t is (
+    CG_CFS, CG_UART0, CG_UART1, CG_SPI, CG_TWI, CG_PWM, CG_WDT, CG_NEOLED, CG_GPTMR, CG_XIP, CG_ONEWIRE
+  );
+  type cg_en_t is array (cg_en_enum_t) of std_ulogic;
   signal cg_en : cg_en_t;
 
   -- CPU status --
@@ -324,22 +324,24 @@ architecture neorv32_top_rtl of neorv32_top is
   signal imem_rsp, dmem_rsp, xip_rsp, boot_rsp, io_rsp, xbus_rsp : bus_rsp_t;
 
   -- bus: IO devices --
-  type io_devices_t is (
+  type io_devices_enum_t is (
     IODEV_OCD, IODEV_SYSINFO, IODEV_NEOLED, IODEV_GPIO, IODEV_WDT, IODEV_TRNG, IODEV_TWI,
     IODEV_SPI, IODEV_SDI, IODEV_UART1, IODEV_UART0, IODEV_MTIME, IODEV_XIRQ, IODEV_ONEWIRE,
     IODEV_GPTMR, IODEV_PWM, IODEV_XIP, IODEV_CRC, IODEV_DMA, IODEV_SLINK, IODEV_CFS
   );
-  type iodev_req_t is array (io_devices_t) of bus_req_t;
-  type iodev_rsp_t is array (io_devices_t) of bus_rsp_t;
+  type iodev_req_t is array (io_devices_enum_t) of bus_req_t;
+  type iodev_rsp_t is array (io_devices_enum_t) of bus_rsp_t;
   signal iodev_req : iodev_req_t;
   signal iodev_rsp : iodev_rsp_t;
 
   -- IRQs --
-  signal cpu_firq : std_ulogic_vector(15 downto 0);
-  type irq_t is record
-    wdt, uart0_rx, uart0_tx, uart1_rx, uart1_tx, spi, sdi, twi, cfs, neoled, xirq, gptmr, onewire, dma, trng, slink : std_ulogic;
-  end record;
-  signal firq      : irq_t;
+  type firq_enum_t is (
+    FIRQ_WDT, FIRQ_UART0_RX, FIRQ_UART0_TX, FIRQ_UART1_RX, FIRQ_UART1_TX, FIRQ_SPI, FIRQ_SDI, FIRQ_TWI,
+    FIRQ_CFS, FIRQ_NEOLED, FIRQ_XIRQ, FIRQ_GPTMR, FIRQ_ONEWIRE, FIRQ_DMA, FIRQ_TRNG, FIRQ_SLINK
+  );
+  type firq_t is array (firq_enum_t) of std_ulogic;
+  signal firq      : firq_t;
+  signal cpu_firq  : std_ulogic_vector(15 downto 0);
   signal mtime_irq : std_ulogic;
 
   -- misc --
@@ -479,8 +481,9 @@ begin
     clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- clk/4096
 
     -- fresh clocks anyone? --
-    clk_gen_en <= cg_en.wdt or cg_en.uart0  or cg_en.uart1 or cg_en.spi or cg_en.twi or cg_en.pwm or
-                  cg_en.cfs or cg_en.neoled or cg_en.gptmr or cg_en.xip or cg_en.onewire;
+    clk_gen_en <= cg_en(CG_WDT)   or cg_en(CG_UART0) or cg_en(CG_UART1) or cg_en(CG_SPI)    or
+                  cg_en(CG_TWI)   or cg_en(CG_PWM)   or cg_en(CG_WDT)   or cg_en(CG_NEOLED) or
+                  cg_en(CG_GPTMR) or cg_en(CG_XIP)   or cg_en(CG_ONEWIRE);
 
 
     -- Clock Gating ---------------------------------------------------------------------------
@@ -570,22 +573,22 @@ begin
     );
 
     -- fast interrupt requests (FIRQs) --
-    cpu_firq(00) <= firq.wdt; -- highest priority
-    cpu_firq(01) <= firq.cfs;
-    cpu_firq(02) <= firq.uart0_rx;
-    cpu_firq(03) <= firq.uart0_tx;
-    cpu_firq(04) <= firq.uart1_rx;
-    cpu_firq(05) <= firq.uart1_tx;
-    cpu_firq(06) <= firq.spi;
-    cpu_firq(07) <= firq.twi;
-    cpu_firq(08) <= firq.xirq;
-    cpu_firq(09) <= firq.neoled;
-    cpu_firq(10) <= firq.dma;
-    cpu_firq(11) <= firq.sdi;
-    cpu_firq(12) <= firq.gptmr;
-    cpu_firq(13) <= firq.onewire;
-    cpu_firq(14) <= firq.slink;
-    cpu_firq(15) <= firq.trng; -- lowest priority
+    cpu_firq(00) <= firq(FIRQ_WDT); -- highest priority
+    cpu_firq(01) <= firq(FIRQ_CFS);
+    cpu_firq(02) <= firq(FIRQ_UART0_RX);
+    cpu_firq(03) <= firq(FIRQ_UART0_TX);
+    cpu_firq(04) <= firq(FIRQ_UART1_RX);
+    cpu_firq(05) <= firq(FIRQ_UART1_TX);
+    cpu_firq(06) <= firq(FIRQ_SPI);
+    cpu_firq(07) <= firq(FIRQ_TWI);
+    cpu_firq(08) <= firq(FIRQ_XIRQ);
+    cpu_firq(09) <= firq(FIRQ_NEOLED);
+    cpu_firq(10) <= firq(FIRQ_DMA);
+    cpu_firq(11) <= firq(FIRQ_SDI);
+    cpu_firq(12) <= firq(FIRQ_GPTMR);
+    cpu_firq(13) <= firq(FIRQ_ONEWIRE);
+    cpu_firq(14) <= firq(FIRQ_SLINK);
+    cpu_firq(15) <= firq(FIRQ_TRNG); -- lowest priority
 
 
     -- CPU Instruction Cache ------------------------------------------------------------------
@@ -681,7 +684,7 @@ begin
       dma_req_o => dma_req,
       dma_rsp_i => dma_rsp,
       firq_i    => cpu_firq,
-      irq_o     => firq.dma
+      irq_o     => firq(FIRQ_DMA)
     );
 
 
@@ -710,7 +713,7 @@ begin
     iodev_rsp(IODEV_DMA) <= rsp_terminate_c;
     main_req             <= core_req;
     core_rsp             <= main_rsp;
-    firq.dma             <= '0';
+    firq(FIRQ_DMA)       <= '0';
   end generate;
 
 
@@ -876,14 +879,13 @@ begin
         XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE
       )
       port map (
-        -- global control --
         clk_i       => clk_i,
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_XIP),
         bus_rsp_o   => iodev_rsp(IODEV_XIP),
         xip_req_i   => xip_req,
         xip_rsp_o   => xip_rsp,
-        clkgen_en_o => cg_en.xip,
+        clkgen_en_o => cg_en(CG_XIP),
         clkgen_i    => clk_gen,
         spi_csn_o   => xip_csn_o,
         spi_clk_o   => xip_clk_o,
@@ -896,14 +898,14 @@ begin
     if not XIP_EN generate
       iodev_rsp(IODEV_XIP) <= rsp_terminate_c;
       xip_rsp              <= rsp_terminate_c;
-      cg_en.xip            <= '0';
+      cg_en(CG_XIP)        <= '0';
       xip_csn_o            <= '1';
       xip_clk_o            <= '0';
       xip_dat_o            <= '0';
     end generate;
 
 
-    -- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
+    -- External Bus (WISHBONE) ----------------------------------------------------------------
     -- -------------------------------------------------------------------------------------------
     neorv32_wishbone_inst_true:
     if MEM_EXT_EN generate
@@ -921,7 +923,6 @@ begin
         bus_req_i => xbus_req,
         bus_rsp_o => xbus_rsp,
         --
-        wb_tag_o  => wb_tag_o,
         wb_adr_o  => wb_adr_o,
         wb_dat_i  => wb_dat_i,
         wb_dat_o  => wb_dat_o,
@@ -943,7 +944,6 @@ begin
       wb_sel_o <= (others => '0');
       wb_stb_o <= '0';
       wb_cyc_o <= '0';
-      wb_tag_o <= (others => '0');
     end generate;
 
   end generate; -- /memory_system
@@ -1027,9 +1027,9 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_CFS),
         bus_rsp_o   => iodev_rsp(IODEV_CFS),
-        clkgen_en_o => cg_en.cfs,
+        clkgen_en_o => cg_en(CG_CFS),
         clkgen_i    => clk_gen,
-        irq_o       => firq.cfs,
+        irq_o       => firq(FIRQ_CFS),
         cfs_in_i    => cfs_in_i,
         cfs_out_o   => cfs_out_o
       );
@@ -1038,8 +1038,8 @@ begin
     neorv32_cfs_inst_false:
     if not IO_CFS_EN generate
       iodev_rsp(IODEV_CFS) <= rsp_terminate_c;
-      cg_en.cfs            <= '0';
-      firq.cfs             <= '0';
+      cg_en(CG_CFS)        <= '0';
+      firq(FIRQ_CFS)       <= '0';
       cfs_out_o            <= (others => '0');
     end generate;
 
@@ -1061,7 +1061,7 @@ begin
         sdi_clk_i => sdi_clk_i,
         sdi_dat_i => sdi_dat_i,
         sdi_dat_o => sdi_dat_o,
-        irq_o     => firq.sdi
+        irq_o     => firq(FIRQ_SDI)
       );
     end generate;
 
@@ -1069,7 +1069,7 @@ begin
     if not IO_SDI_EN generate
       iodev_rsp(IODEV_SDI) <= rsp_terminate_c;
       sdi_dat_o            <= '0';
-      firq.sdi             <= '0';
+      firq(FIRQ_SDI)       <= '0';
     end generate;
 
 
@@ -1111,9 +1111,9 @@ begin
         bus_rsp_o   => iodev_rsp(IODEV_WDT),
         cpu_debug_i => cpu_debug,
         cpu_sleep_i => cpu_sleep,
-        clkgen_en_o => cg_en.wdt,
+        clkgen_en_o => cg_en(CG_WDT),
         clkgen_i    => clk_gen,
-        irq_o       => firq.wdt,
+        irq_o       => firq(FIRQ_WDT),
         rstn_o      => rstn_wdt
       );
     end generate;
@@ -1121,9 +1121,9 @@ begin
     neorv32_wdt_inst_false:
     if not IO_WDT_EN generate
       iodev_rsp(IODEV_WDT) <= rsp_terminate_c;
-      firq.wdt             <= '0';
+      firq(FIRQ_WDT)       <= '0';
+      cg_en(CG_WDT)        <= '0';
       rstn_wdt             <= '1';
-      cg_en.wdt            <= '0';
     end generate;
 
 
@@ -1179,14 +1179,14 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_UART0),
         bus_rsp_o   => iodev_rsp(IODEV_UART0),
-        clkgen_en_o => cg_en.uart0,
+        clkgen_en_o => cg_en(CG_UART0),
         clkgen_i    => clk_gen,
         uart_txd_o  => uart0_txd_o,
         uart_rxd_i  => uart0_rxd_i,
         uart_rts_o  => uart0_rts_o,
         uart_cts_i  => uart0_cts_i,
-        irq_rx_o    => firq.uart0_rx,
-        irq_tx_o    => firq.uart0_tx
+        irq_rx_o    => firq(FIRQ_UART0_RX),
+        irq_tx_o    => firq(FIRQ_UART0_TX)
       );
     end generate;
 
@@ -1195,9 +1195,9 @@ begin
       iodev_rsp(IODEV_UART0) <= rsp_terminate_c;
       uart0_txd_o            <= '0';
       uart0_rts_o            <= '1';
-      cg_en.uart0            <= '0';
-      firq.uart0_rx          <= '0';
-      firq.uart0_tx          <= '0';
+      cg_en(CG_UART0)        <= '0';
+      firq(FIRQ_UART0_RX)    <= '0';
+      firq(FIRQ_UART0_TX)    <= '0';
     end generate;
 
 
@@ -1216,14 +1216,14 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_UART1),
         bus_rsp_o   => iodev_rsp(IODEV_UART1),
-        clkgen_en_o => cg_en.uart1,
+        clkgen_en_o => cg_en(CG_UART1),
         clkgen_i    => clk_gen,
         uart_txd_o  => uart1_txd_o,
         uart_rxd_i  => uart1_rxd_i,
         uart_rts_o  => uart1_rts_o,
         uart_cts_i  => uart1_cts_i,
-        irq_rx_o    => firq.uart1_rx,
-        irq_tx_o    => firq.uart1_tx
+        irq_rx_o    => firq(FIRQ_UART1_RX),
+        irq_tx_o    => firq(FIRQ_UART1_TX)
       );
     end generate;
 
@@ -1232,9 +1232,9 @@ begin
       iodev_rsp(IODEV_UART1) <= rsp_terminate_c;
       uart1_txd_o            <= '0';
       uart1_rts_o            <= '1';
-      cg_en.uart1            <= '0';
-      firq.uart1_rx          <= '0';
-      firq.uart1_tx          <= '0';
+      cg_en(CG_UART1)        <= '0';
+      firq(FIRQ_UART1_RX)    <= '0';
+      firq(FIRQ_UART1_TX)    <= '0';
     end generate;
 
 
@@ -1251,13 +1251,13 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_SPI),
         bus_rsp_o   => iodev_rsp(IODEV_SPI),
-        clkgen_en_o => cg_en.spi,
+        clkgen_en_o => cg_en(CG_SPI),
         clkgen_i    => clk_gen,
         spi_clk_o   => spi_clk_o,
         spi_dat_o   => spi_dat_o,
         spi_dat_i   => spi_dat_i,
         spi_csn_o   => spi_csn_o,
-        irq_o       => firq.spi
+        irq_o       => firq(FIRQ_SPI)
       );
     end generate;
 
@@ -1267,8 +1267,8 @@ begin
       spi_clk_o            <= '0';
       spi_dat_o            <= '0';
       spi_csn_o            <= (others => '1');
-      cg_en.spi            <= '0';
-      firq.spi             <= '0';
+      cg_en(CG_SPI)        <= '0';
+      firq(FIRQ_SPI)       <= '0';
     end generate;
 
 
@@ -1282,13 +1282,13 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_TWI),
         bus_rsp_o   => iodev_rsp(IODEV_TWI),
-        clkgen_en_o => cg_en.twi,
+        clkgen_en_o => cg_en(CG_TWI),
         clkgen_i    => clk_gen,
         twi_sda_i   => twi_sda_i,
         twi_sda_o   => twi_sda_o,
         twi_scl_i   => twi_scl_i,
         twi_scl_o   => twi_scl_o,
-        irq_o       => firq.twi
+        irq_o       => firq(FIRQ_TWI)
       );
     end generate;
 
@@ -1297,8 +1297,8 @@ begin
       iodev_rsp(IODEV_TWI) <= rsp_terminate_c;
       twi_sda_o            <= '1';
       twi_scl_o            <= '1';
-      cg_en.twi            <= '0';
-      firq.twi             <= '0';
+      cg_en(CG_TWI)        <= '0';
+      firq(FIRQ_TWI)       <= '0';
     end generate;
 
 
@@ -1315,7 +1315,7 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_PWM),
         bus_rsp_o   => iodev_rsp(IODEV_PWM),
-        clkgen_en_o => cg_en.pwm,
+        clkgen_en_o => cg_en(CG_PWM),
         clkgen_i    => clk_gen,
         pwm_o       => pwm_o
       );
@@ -1324,7 +1324,7 @@ begin
     neorv32_pwm_inst_false:
     if not io_pwm_en_c generate
       iodev_rsp(IODEV_PWM) <= rsp_terminate_c;
-      cg_en.pwm            <= '0';
+      cg_en(CG_PWM)        <= '0';
       pwm_o                <= (others => '0');
     end generate;
 
@@ -1342,14 +1342,14 @@ begin
         rstn_i    => rstn_sys,
         bus_req_i => iodev_req(IODEV_TRNG),
         bus_rsp_o => iodev_rsp(IODEV_TRNG),
-        irq_o     => firq.trng
+        irq_o     => firq(FIRQ_TRNG)
       );
     end generate;
 
     neorv32_trng_inst_false:
     if not IO_TRNG_EN generate
       iodev_rsp(IODEV_TRNG) <= rsp_terminate_c;
-      firq.trng             <= '0';
+      firq(FIRQ_TRNG)       <= '0';
     end generate;
 
 
@@ -1366,9 +1366,9 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_NEOLED),
         bus_rsp_o   => iodev_rsp(IODEV_NEOLED),
-        clkgen_en_o => cg_en.neoled,
+        clkgen_en_o => cg_en(CG_NEOLED),
         clkgen_i    => clk_gen,
-        irq_o       => firq.neoled,
+        irq_o       => firq(FIRQ_NEOLED),
         neoled_o    => neoled_o
       );
     end generate;
@@ -1376,8 +1376,8 @@ begin
     neorv32_neoled_inst_false:
     if not IO_NEOLED_EN generate
       iodev_rsp(IODEV_NEOLED) <= rsp_terminate_c;
-      cg_en.neoled            <= '0';
-      firq.neoled             <= '0';
+      cg_en(CG_NEOLED)        <= '0';
+      firq(FIRQ_NEOLED)       <= '0';
       neoled_o                <= '0';
     end generate;
 
@@ -1399,14 +1399,14 @@ begin
         bus_req_i => iodev_req(IODEV_XIRQ),
         bus_rsp_o => iodev_rsp(IODEV_XIRQ),
         xirq_i    => xirq_i,
-        cpu_irq_o => firq.xirq
+        cpu_irq_o => firq(FIRQ_XIRQ)
       );
     end generate;
 
     neorv32_xirq_inst_false:
     if not io_xirq_en_c generate
       iodev_rsp(IODEV_XIRQ) <= rsp_terminate_c;
-      firq.xirq             <= '0';
+      firq(FIRQ_XIRQ)       <= '0';
     end generate;
 
 
@@ -1420,9 +1420,9 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_GPTMR),
         bus_rsp_o   => iodev_rsp(IODEV_GPTMR),
-        clkgen_en_o => cg_en.gptmr,
+        clkgen_en_o => cg_en(CG_GPTMR),
         clkgen_i    => clk_gen,
-        irq_o       => firq.gptmr,
+        irq_o       => firq(FIRQ_GPTMR),
         capture_i   => gptmr_trig_i
       );
     end generate;
@@ -1430,8 +1430,8 @@ begin
     neorv32_gptmr_inst_false:
     if not IO_GPTMR_EN generate
       iodev_rsp(IODEV_GPTMR) <= rsp_terminate_c;
-      cg_en.gptmr            <= '0';
-      firq.gptmr             <= '0';
+      cg_en(CG_GPTMR)        <= '0';
+      firq(FIRQ_GPTMR)       <= '0';
     end generate;
 
 
@@ -1445,11 +1445,11 @@ begin
         rstn_i      => rstn_sys,
         bus_req_i   => iodev_req(IODEV_ONEWIRE),
         bus_rsp_o   => iodev_rsp(IODEV_ONEWIRE),
-        clkgen_en_o => cg_en.onewire,
+        clkgen_en_o => cg_en(CG_ONEWIRE),
         clkgen_i    => clk_gen,
         onewire_i   => onewire_i,
         onewire_o   => onewire_o,
-        irq_o       => firq.onewire
+        irq_o       => firq(FIRQ_ONEWIRE)
       );
     end generate;
 
@@ -1457,8 +1457,8 @@ begin
     if not IO_ONEWIRE_EN generate
       iodev_rsp(IODEV_ONEWIRE) <= rsp_terminate_c;
       onewire_o                <= '1';
-      cg_en.onewire            <= '0';
-      firq.onewire             <= '0';
+      cg_en(CG_ONEWIRE)        <= '0';
+      firq(FIRQ_ONEWIRE)       <= '0';
     end generate;
 
 
@@ -1477,7 +1477,7 @@ begin
         rstn_i           => rstn_sys,
         bus_req_i        => iodev_req(IODEV_SLINK),
         bus_rsp_o        => iodev_rsp(IODEV_SLINK),
-        irq_o            => firq.slink,
+        irq_o            => firq(FIRQ_SLINK),
         -- RX stream interface --
         slink_rx_data_i  => slink_rx_dat_i,
         slink_rx_valid_i => slink_rx_val_i,
@@ -1494,7 +1494,7 @@ begin
     neorv32_slink_inst_false:
     if not IO_SLINK_EN generate
       iodev_rsp(IODEV_SLINK) <= rsp_terminate_c;
-      firq.slink             <= '0';
+      firq(FIRQ_SLINK)       <= '0';
       slink_rx_rdy_o         <= '0';
       slink_tx_dat_o         <= (others => '0');
       slink_tx_val_o         <= '0';

From b2192976571e7dbee82e93fc9354c613a95ece01 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Mon, 11 Mar 2024 17:43:38 +0100
Subject: [PATCH 5/6] [cache] code clean-ups and optimizations

---
 rtl/core/neorv32_cache.vhd | 56 ++++++++++++++++++--------------------
 1 file changed, 26 insertions(+), 30 deletions(-)

diff --git a/rtl/core/neorv32_cache.vhd b/rtl/core/neorv32_cache.vhd
index 8ac9d5ee6..ed78e7daf 100644
--- a/rtl/core/neorv32_cache.vhd
+++ b/rtl/core/neorv32_cache.vhd
@@ -830,18 +830,16 @@ architecture neorv32_cache_bus_rtl of neorv32_cache_bus is
   constant index_size_c  : natural := index_size_f(NUM_BLOCKS);
   constant tag_size_c    : natural := 32 - (offset_size_c + index_size_c + 2);
 
-  -- host request buffer --
-  signal hreq : bus_req_t;
-
   -- control fsm --
-  type state_t is (S_IDLE, S_CHECK, S_DOWNLOAD_REQ, S_DOWNLOAD_RSP, S_UPLOAD_GET, S_UPLOAD_REQ, S_UPLOAD_RSP, S_FLUSH_START, S_FLUSH_READ, S_FLUSH_CHECK);
+  type state_t is (S_IDLE, S_CHECK, S_DOWNLOAD_REQ, S_DOWNLOAD_RSP, S_UPLOAD_GET,
+                   S_UPLOAD_REQ, S_UPLOAD_RSP, S_FLUSH_START, S_FLUSH_READ, S_FLUSH_CHECK);
   signal state, upret, state_nxt, upret_nxt: state_t;
 
   -- address generator --
   type addr_t is record
     tag : std_ulogic_vector(tag_size_c-1 downto 0);
-    ind : std_ulogic_vector(index_size_c-1 downto 0);
-    off : std_ulogic_vector(offset_size_c-1 downto 0); -- WORD offset!
+    idx : std_ulogic_vector(index_size_c-1 downto 0);
+    ofs : std_ulogic_vector(offset_size_c-1 downto 0); -- WORD offset!
   end record;
   signal haddr, baddr, addr, addr_nxt : addr_t;
 
@@ -851,13 +849,13 @@ begin
   -- -------------------------------------------------------------------------------------------
   -- base address of original host access --
   haddr.tag <= host_req_i.addr(31 downto (32-tag_size_c));
-  haddr.ind <= host_req_i.addr((offset_size_c+2+index_size_c)-1 downto offset_size_c+2);
-  haddr.off <= (others => '0'); -- unused
+  haddr.idx <= (others => '0'); -- unused
+  haddr.ofs <= (others => '0'); -- unused
 
   -- base address of indexed cache block --
   baddr.tag <= base_i(31 downto (32-tag_size_c));
-  baddr.ind <= base_i((offset_size_c+2+index_size_c)-1 downto offset_size_c+2);
-  baddr.off <= (others => '0'); -- unused
+  baddr.idx <= base_i((offset_size_c+2+index_size_c)-1 downto offset_size_c+2);
+  baddr.ofs <= (others => '0'); -- unused
 
 
   -- Control Engine FSM Sync ----------------------------------------------------------------
@@ -868,21 +866,19 @@ begin
       state    <= S_IDLE;
       upret    <= S_IDLE;
       addr.tag <= (others => '0');
-      addr.ind <= (others => '0');
-      addr.off <= (others => '0');
-      hreq     <= req_terminate_c;
+      addr.idx <= (others => '0');
+      addr.ofs <= (others => '0');
     elsif rising_edge(clk_i) then
       state <= state_nxt;
       upret <= upret_nxt;
       addr  <= addr_nxt;
-      hreq  <= host_req_i;
     end if;
   end process ctrl_engine_sync;
 
 
   -- Control Engine FSM Comb ----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  ctrl_engine_comb: process(state, upret, addr, hreq, haddr, baddr, bus_rsp_i, cmd_sync_i, cmd_miss_i, rdata_i, dirty_i)
+  ctrl_engine_comb: process(state, upret, addr, haddr, baddr, bus_rsp_i, cmd_sync_i, cmd_miss_i, rdata_i, dirty_i)
   begin
     -- control engine defaults --
     state_nxt <= state;
@@ -890,7 +886,7 @@ begin
     addr_nxt  <= addr;
 
     -- cache defaults --
-    addr_o  <= addr.tag & addr.ind & addr.off & "00"; -- always word-aligned
+    addr_o  <= addr.tag & addr.idx & addr.ofs & "00"; -- always word-aligned
     we_o    <= (others => '0');
     swe_o   <= '0';
     wdata_o <= bus_rsp_i.data;
@@ -902,17 +898,18 @@ begin
 
     -- bus interface defaults --
     bus_req_o      <= req_terminate_c; -- all-zero
-    bus_req_o.addr <= addr.tag & addr.ind & addr.off & "00"; -- always word-aligned
+    bus_req_o.addr <= addr.tag & addr.idx & addr.ofs & "00"; -- always word-aligned
     bus_req_o.data <= rdata_i;
     bus_req_o.ben  <= (others => '1'); -- full-word writes only
-    bus_req_o.priv <= hreq.priv; -- keep original privilege level
+    bus_req_o.src  <= '0'; -- cache accesses are always "data" accesses
+    bus_req_o.priv <= '0'; -- cache accesses are always "unprivileged" accesses
 
     -- fsm --
     case state is
 
       when S_IDLE => -- wait for request
       -- ------------------------------------------------------------
-        addr_nxt.off <= (others => '0'); -- align block base address for upload/download (and flush)
+        addr_nxt.ofs <= (others => '0'); -- align block base address for upload/download (and flush)
         if (cmd_sync_i = '1') then -- cache sync
           state_nxt <= S_FLUSH_START;
         elsif (cmd_miss_i = '1') then -- cache miss
@@ -921,14 +918,13 @@ begin
 
       when S_CHECK => -- check if accessed block is dirty (cache address is still applied by host controller!)
       -- ------------------------------------------------------------
-        upret_nxt <= S_DOWNLOAD_REQ; -- go straight to S_DOWNLOAD_REQ when S_UPLOAD_GET has completed (if executed)
+        upret_nxt    <= S_DOWNLOAD_REQ; -- go straight to S_DOWNLOAD_REQ when S_UPLOAD_GET has completed (if executed)
+        addr_nxt.idx <= baddr.idx; -- index of reference cache block
         if (dirty_i = '1') then -- block is dirty, upload first
           addr_nxt.tag <= baddr.tag; -- base address (tag + index) of accessed block
-          addr_nxt.ind <= baddr.ind;
           state_nxt    <= S_UPLOAD_GET;
-        else -- block is clean, download new block and override
+        else -- block is clean, download new block
           addr_nxt.tag <= haddr.tag; -- base address (tag + index) of requested block
-          addr_nxt.ind <= haddr.ind;
           state_nxt    <= S_DOWNLOAD_REQ;
         end if;
 
@@ -946,8 +942,8 @@ begin
         swe_o        <= '1'; -- cache: write status bit (bus error response)
         new_o        <= '1'; -- set new block (set tag, make valid, make clean)
         if (bus_rsp_i.ack = '1') or (bus_rsp_i.err = '1') then -- wait for response
-          addr_nxt.off <= std_ulogic_vector(unsigned(addr.off) + 1);
-          if (and_reduce_f(addr.off) = '1') then -- block completed? offset will be all-zero again after block completion
+          addr_nxt.ofs <= std_ulogic_vector(unsigned(addr.ofs) + 1);
+          if (and_reduce_f(addr.ofs) = '1') then -- block completed? offset will be all-zero again after block completion
             state_nxt <= S_IDLE;
           else -- get next word
             state_nxt <= S_DOWNLOAD_REQ;
@@ -971,8 +967,8 @@ begin
         bus_req_o.rw <= '1'; -- write access
         new_o        <= '1'; -- set new block (set tag, make valid, make clean)
         if (bus_rsp_i.ack = '1') or (bus_rsp_i.err = '1') then -- wait for response
-          addr_nxt.off <= std_ulogic_vector(unsigned(addr.off) + 1);
-          if (and_reduce_f(addr.off) = '1') then -- block completed? offset will be all-zero again after block completion
+          addr_nxt.ofs <= std_ulogic_vector(unsigned(addr.ofs) + 1);
+          if (and_reduce_f(addr.ofs) = '1') then -- block completed? offset will be all-zero again after block completion
             state_nxt <= upret; -- go back to "upload-done return state"
           else -- get next word
             state_nxt <= S_UPLOAD_GET;
@@ -982,7 +978,7 @@ begin
 
       when S_FLUSH_START => -- start checking for dirty blocks
       -- ------------------------------------------------------------
-        addr_nxt.ind <= (others => '0'); -- start with index 0
+        addr_nxt.idx <= (others => '0'); -- start with index 0
         upret_nxt    <= S_FLUSH_CHECK; -- come back to S_FLUSH_CHECK after block upload
         state_nxt    <= S_FLUSH_READ;
 
@@ -997,8 +993,8 @@ begin
         if (dirty_i = '1') then -- block dirty?
           state_nxt    <= S_UPLOAD_GET;
         else -- move on to next block
-          addr_nxt.ind <= std_ulogic_vector(unsigned(addr.ind) + 1);
-          if (and_reduce_f(addr.ind) = '1') then -- all blocks done?
+          addr_nxt.idx <= std_ulogic_vector(unsigned(addr.idx) + 1);
+          if (and_reduce_f(addr.idx) = '1') then -- all blocks done?
             bus_req_o.fence <= '1'; -- forward fence request to downstream memories
             state_nxt       <= S_IDLE;
           else -- go to next block

From 5a905349de667b1ec1d495aff4bdb32bfbf2a435 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Mon, 11 Mar 2024 18:20:44 +0100
Subject: [PATCH 6/6] [changelog] add v1.9.6.3

---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index b9c4063f8..b0977c2bc 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Link |
 |:----:|:-------:|:--------|:----:|
+| 11.03.2024 | 1.9.6.3 | :warning: remove Wishbone tag signal; minor rtl edits and optimizations | [#845](https://github.com/stnolting/neorv32/pull/845) |
 | 10.03.2024 | 1.9.6.2 | minor rtl clean-ups, optimizations and fixes | [#843](https://github.com/stnolting/neorv32/pull/843) |
 | 09.03.2024 | 1.9.6.1 | add generic cache module (not used yet) | [#842](https://github.com/stnolting/neorv32/pull/842) |
 | 01.03.2024 | [**:rocket:1.9.6**](https://github.com/stnolting/neorv32/releases/tag/v1.9.6) | **New release** | |