diff --git a/CHANGELOG.md b/CHANGELOG.md index 6758d6da2..e040fcd24 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -31,6 +31,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12 | Date (*dd.mm.yyyy*) | Version | Comment | |:-------------------:|:-------:|:--------| +| 24.02.2023 | 1.8.1.2 | :warning: rename top interface signals of **XIP** and **SIP** modules; [#504](https://github.com/stnolting/neorv32/pull/504) | | 23.02.2023 | 1.8.1.1 | CFS: add another 32 interface register (now having 64 memory-mapped registers for custom usage); [#503](https://github.com/stnolting/neorv32/pull/503) | | 23.02.2023 | [**:rocket:1.8.1**](https://github.com/stnolting/neorv32/releases/tag/v1.8.1) | **New release** | | 22.02.2023 | 1.8.0.10 | :warning: **remove stream link interface (SLINK)**; [#502](https://github.com/stnolting/neorv32/pull/502) | diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index c0d1ebc2c..987cef0f0 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -94,8 +94,8 @@ bits/channels are hardwired to zero. 4+^| **Execute In Place Interface (<<_execute_in_place_module_xip,**XIP**>>)** | `xip_csn_o` | 1 | out | chi select, low-active | `xip_clk_o` | 1 | out | serial clock -| `xip_sdi_i` | 1 | in | serial data input -| `xip_sdo_o` | 1 | out | serial data output +| `xip_dat_i` | 1 | in | serial data input +| `xip_dat_o` | 1 | out | serial data output 4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)** | `gpio_o` | 64 | out | general purpose parallel output | `gpio_i` | 64 | in | general purpose parallel input @@ -110,9 +110,9 @@ bits/channels are hardwired to zero. | `uart1_rts_o` | 1 | out | RX ready to receive new char | `uart1_cts_i` | 1 | in | TX allowed to start sending 4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)** -| `spi_sck_o` | 1 | out | controller clock line -| `spi_sdo_o` | 1 | out | serial data output -| `spi_sdi_i` | 1 | in | serial data input +| `spi_clk_o` | 1 | out | controller clock line +| `spi_dat_o` | 1 | out | serial data output +| `spi_dat_i` | 1 | in | serial data input | `spi_csn_o` | 8 | out | dedicated chip select (low-active) 4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)** | `twi_sda_io` | 1 | inout | serial data line diff --git a/docs/datasheet/soc_spi.adoc b/docs/datasheet/soc_spi.adoc index f98beff56..79edda1f6 100644 --- a/docs/datasheet/soc_spi.adoc +++ b/docs/datasheet/soc_spi.adoc @@ -8,9 +8,9 @@ | Hardware source file(s): | neorv32_spi.vhd | | Software driver file(s): | neorv32_spi.c | | | neorv32_spi.h | -| Top entity port: | `spi_sck_o` | 1-bit serial clock output -| | `spi_sdo_o` | 1-bit serial data output -| | `spi_sdi_i` | 1-bit serial data input +| Top entity port: | `spi_clk_o` | 1-bit serial clock output +| | `spi_dat_o` | 1-bit serial data output +| | `spi_dat_i` | 1-bit serial data input | | `spi_csn_i` | 8-bit dedicated chip select (low-active) | Configuration generics: | _IO_SPI_EN_ | implement SPI controller when _true_ | | _IO_SPI_FIFO_ | data FIFO size, has to be zero or a power of two @@ -90,7 +90,7 @@ image::SPI_timing_diagram2.wikimedia.png[] | _SPI_CTRL_CPHA_ | `0` | `1` | `0` | `1` |======================= -The SPI clock frequency (`spi_sck_o`) is programmed by the 3-bit _SPI_CTRL_PRSCx_ clock prescaler for a coarse selection +The SPI clock frequency (`spi_clk_o`) is programmed by the 3-bit _SPI_CTRL_PRSCx_ clock prescaler for a coarse selection and a 4-bit clock divider _SPI_CTRL_CDIVx_ for a fine selection. The following pre-scalers (_SPI_CTRL_PRSCx_) are available: diff --git a/docs/datasheet/soc_xip.adoc b/docs/datasheet/soc_xip.adoc index bd954bae2..0dff8d2e7 100644 --- a/docs/datasheet/soc_xip.adoc +++ b/docs/datasheet/soc_xip.adoc @@ -10,8 +10,8 @@ | | neorv32_xip.h | | Top entity port: | `xip_csn_o` | 1-bit chip select, low-active | | `xip_clk_o` | 1-bit serial clock output -| | `xip_sdi_i` | 1-bit serial data input -| | `xip_sdo_o` | 1-bit serial data output +| | `xip_dat_i` | 1-bit serial data input +| | `xip_dat_o` | 1-bit serial data output | Configuration generics: | _IO_XIP_EN_ | implement XIP module when _true_ | CPU interrupts: | none | |======================= diff --git a/rtl/core/neorv32_application_image.vhd b/rtl/core/neorv32_application_image.vhd index e489f30a6..407d21e6f 100644 --- a/rtl/core/neorv32_application_image.vhd +++ b/rtl/core/neorv32_application_image.vhd @@ -2,7 +2,7 @@ -- Auto-generated memory initialization file (for APPLICATION) from source file -- Size: 1076 bytes -- MARCH: default --- Built: 21.01.2023 15:20:33 +-- Built: 24.02.2023 18:13:22 -- prototype defined in 'neorv32_package.vhd' package body neorv32_application_image is diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index b80af1ba1..2693a185a 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -65,7 +65,7 @@ package neorv32_package is -- Architecture Constants (do not modify!) ------------------------------------------------ -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080101"; -- NEORV32 version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080102"; -- NEORV32 version constant archid_c : natural := 19; -- official RISC-V architecture ID -- Check if we're inside the Matrix ------------------------------------------------------- @@ -224,7 +224,19 @@ package neorv32_package is -- reserved -- --constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff00"; -- base address ---constant reserved_size_c : natural := 16*4; -- module's address space size in bytes +--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff08"; -- base address +--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff10"; -- base address +--constant reserved_size_c : natural := 4*4; -- module's address space size in bytes + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff20"; -- base address +--constant reserved_size_c : natural := 8*4; -- module's address space size in bytes -- Execute In Place Module (XIP) -- constant xip_base_c : std_ulogic_vector(31 downto 0) := x"ffffff40"; -- base address @@ -1057,8 +1069,8 @@ package neorv32_package is -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o : out std_ulogic; -- chip-select, low-active xip_clk_o : out std_ulogic; -- serial clock - xip_sdi_i : in std_ulogic := 'L'; -- device data input - xip_sdo_o : out std_ulogic; -- controller data output + xip_dat_i : in std_ulogic := 'L'; -- device data input + xip_dat_o : out std_ulogic; -- controller data output -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input @@ -1073,9 +1085,9 @@ package neorv32_package is uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o : out std_ulogic; -- SPI serial clock - spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in - spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_clk_o : out std_ulogic; -- SPI serial clock + spi_dat_o : out std_ulogic; -- controller data out, peripheral data in + spi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS -- TWI (available if IO_TWI_EN = true) -- twi_sda_io : inout std_logic; -- twi serial data line @@ -1770,9 +1782,9 @@ package neorv32_package is clkgen_en_o : out std_ulogic; -- enable clock generator clkgen_i : in std_ulogic_vector(07 downto 0); -- com lines -- - spi_sck_o : out std_ulogic; -- SPI serial clock - spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in - spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out + spi_clk_o : out std_ulogic; -- SPI serial clock + spi_dat_o : out std_ulogic; -- controller data out, peripheral data in + spi_dat_i : in std_ulogic; -- controller data in, peripheral data out spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS -- interrupt -- irq_o : out std_ulogic -- transmission done interrupt @@ -2033,8 +2045,8 @@ package neorv32_package is -- SPI device interface -- spi_csn_o : out std_ulogic; -- chip-select, low-active spi_clk_o : out std_ulogic; -- serial clock - spi_data_i : in std_ulogic; -- device data output - spi_data_o : out std_ulogic -- controller data output + spi_dat_i : in std_ulogic; -- device data output + spi_dat_o : out std_ulogic -- controller data output ); end component; diff --git a/rtl/core/neorv32_spi.vhd b/rtl/core/neorv32_spi.vhd index ff6684702..d731ef631 100644 --- a/rtl/core/neorv32_spi.vhd +++ b/rtl/core/neorv32_spi.vhd @@ -7,7 +7,7 @@ -- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # --- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # +-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # @@ -61,9 +61,9 @@ entity neorv32_spi is clkgen_en_o : out std_ulogic; -- enable clock generator clkgen_i : in std_ulogic_vector(07 downto 0); -- com lines -- - spi_sck_o : out std_ulogic; -- SPI serial clock - spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in - spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out + spi_clk_o : out std_ulogic; -- SPI serial clock + spi_dat_o : out std_ulogic; -- controller data out, peripheral data in + spi_dat_i : in std_ulogic; -- controller data in, peripheral data out spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS -- interrupt -- irq_o : out std_ulogic -- transmission done interrupt @@ -275,7 +275,7 @@ begin tx_fifo_inst: neorv32_fifo generic map ( FIFO_DEPTH => IO_SPI_FIFO, -- number of fifo entries; has to be a power of two; min 1 - FIFO_WIDTH => 32, -- size of data elements in fifo (32-bit only for simulation) + FIFO_WIDTH => 32, -- size of data elements in fifo FIFO_RSYNC => false, -- async read FIFO_SAFE => true, -- safe access FIFO_GATE => false -- no output gate required @@ -312,7 +312,7 @@ begin rx_fifo_inst: neorv32_fifo generic map ( FIFO_DEPTH => IO_SPI_FIFO, -- number of fifo entries; has to be a power of two; min 1 - FIFO_WIDTH => 32, -- size of data elements in fifo (32-bit only for simulation) + FIFO_WIDTH => 32, -- size of data elements in fifo FIFO_RSYNC => false, -- async read FIFO_SAFE => true, -- safe access FIFO_GATE => false -- no output gate required @@ -412,7 +412,7 @@ begin when "100" => -- enabled but idle, waiting for new transmission trigger -- ------------------------------------------------------------ - spi_sck_o <= ctrl.cpol; + spi_clk_o <= ctrl.cpol; rtx_engine.bitcnt <= (others => '0'); if (rtx_engine.start = '1') then -- trigger new transmission rtx_engine.sreg <= tx_fifo.rdata; @@ -423,7 +423,7 @@ begin -- ------------------------------------------------------------ if (spi_clk_en = '1') then if (ctrl.cpha = '1') then -- clock phase shift - spi_sck_o <= not ctrl.cpol; + spi_clk_o <= not ctrl.cpol; end if; rtx_engine.state(1 downto 0) <= "10"; end if; @@ -431,8 +431,8 @@ begin when "110" => -- first half of bit transmission -- ------------------------------------------------------------ if (spi_clk_en = '1') then - spi_sck_o <= not (ctrl.cpha xor ctrl.cpol); - rtx_engine.sdi_sync <= spi_sdi_i; -- sample data input + spi_clk_o <= not (ctrl.cpha xor ctrl.cpol); + rtx_engine.sdi_sync <= spi_dat_i; -- sample data input rtx_engine.bitcnt <= std_ulogic_vector(unsigned(rtx_engine.bitcnt) + 1); rtx_engine.state(1 downto 0) <= "11"; end if; @@ -442,18 +442,18 @@ begin if (spi_clk_en = '1') then rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync; -- shift and set output if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then -- all bits transferred? - spi_sck_o <= ctrl.cpol; + spi_clk_o <= ctrl.cpol; rtx_engine.done <= '1'; -- done! rtx_engine.state(1 downto 0) <= "00"; -- transmission done else - spi_sck_o <= ctrl.cpha xor ctrl.cpol; + spi_clk_o <= ctrl.cpha xor ctrl.cpol; rtx_engine.state(1 downto 0) <= "10"; end if; end if; when others => -- "0--": SPI deactivated -- ------------------------------------------------------------ - spi_sck_o <= ctrl.cpol; + spi_clk_o <= ctrl.cpol; rtx_engine.sreg <= (others => '0'); rtx_engine.state(1 downto 0) <= "00"; @@ -468,10 +468,10 @@ begin data_size: process(ctrl, rtx_engine) begin case ctrl.rtx_size is - when "00" => rtx_engine.bytecnt <= "001"; spi_sdo_o <= rtx_engine.sreg(07); -- 8-bit mode - when "01" => rtx_engine.bytecnt <= "010"; spi_sdo_o <= rtx_engine.sreg(15); -- 16-bit mode - when "10" => rtx_engine.bytecnt <= "011"; spi_sdo_o <= rtx_engine.sreg(23); -- 24-bit mode - when others => rtx_engine.bytecnt <= "100"; spi_sdo_o <= rtx_engine.sreg(31); -- 32-bit mode + when "00" => rtx_engine.bytecnt <= "001"; spi_dat_o <= rtx_engine.sreg(07); -- 8-bit mode + when "01" => rtx_engine.bytecnt <= "010"; spi_dat_o <= rtx_engine.sreg(15); -- 16-bit mode + when "10" => rtx_engine.bytecnt <= "011"; spi_dat_o <= rtx_engine.sreg(23); -- 24-bit mode + when others => rtx_engine.bytecnt <= "100"; spi_dat_o <= rtx_engine.sreg(31); -- 32-bit mode end case; end process data_size; diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index f70e896be..21f9d56aa 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -166,8 +166,8 @@ entity neorv32_top is -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o : out std_ulogic; -- chip-select, low-active xip_clk_o : out std_ulogic; -- serial clock - xip_sdi_i : in std_ulogic := 'L'; -- device data input - xip_sdo_o : out std_ulogic; -- controller data output + xip_dat_i : in std_ulogic := 'L'; -- device data input + xip_dat_o : out std_ulogic; -- controller data output -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output @@ -186,9 +186,9 @@ entity neorv32_top is uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o : out std_ulogic; -- SPI serial clock - spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in - spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_clk_o : out std_ulogic; -- SPI serial clock + spi_dat_o : out std_ulogic; -- controller data out, peripheral data in + spi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select -- TWI (available if IO_TWI_EN = true) -- @@ -600,7 +600,7 @@ begin fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX - fast_irq(06) <= spi_irq; -- SPI transfer done + fast_irq(06) <= spi_irq; -- SPI interrupt fast_irq(07) <= twi_irq; -- TWI transfer done fast_irq(08) <= xirq_irq; -- external interrupt controller fast_irq(09) <= neoled_irq; -- NEOLED buffer IRQ @@ -951,8 +951,8 @@ begin -- SPI device interface -- spi_csn_o => xip_csn_o, -- chip-select, low-active spi_clk_o => xip_clk_o, -- serial clock - spi_data_i => xip_sdi_i, -- device data output - spi_data_o => xip_sdo_o -- controller data output + spi_dat_i => xip_dat_i, -- device data output + spi_dat_o => xip_dat_o -- controller data output ); resp_bus(RESP_XIP_CT).err <= '0'; -- no access error possible end generate; @@ -968,7 +968,7 @@ begin xip_cg_en <= '0'; xip_csn_o <= '1'; xip_clk_o <= '0'; - xip_sdo_o <= '0'; + xip_dat_o <= '0'; end generate; @@ -1246,9 +1246,9 @@ begin clkgen_en_o => spi_cg_en, -- enable clock generator clkgen_i => clk_gen, -- com lines -- - spi_sck_o => spi_sck_o, -- SPI serial clock - spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in - spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out + spi_clk_o => spi_clk_o, -- SPI serial clock + spi_dat_o => spi_dat_o, -- controller data out, peripheral data in + spi_dat_i => spi_dat_i, -- controller data in, peripheral data out spi_csn_o => spi_csn_o, -- SPI CS -- interrupt -- irq_o => spi_irq -- transmission done interrupt @@ -1260,8 +1260,8 @@ begin if (IO_SPI_EN = false) generate resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c; -- - spi_sck_o <= '0'; - spi_sdo_o <= '0'; + spi_clk_o <= '0'; + spi_dat_o <= '0'; spi_csn_o <= (others => '1'); -- CS lines are low-active spi_cg_en <= '0'; spi_irq <= '0'; diff --git a/rtl/core/neorv32_xip.vhd b/rtl/core/neorv32_xip.vhd index 2f82cf0b4..f0bbf49ae 100644 --- a/rtl/core/neorv32_xip.vhd +++ b/rtl/core/neorv32_xip.vhd @@ -9,7 +9,7 @@ -- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # --- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # +-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # @@ -74,8 +74,8 @@ entity neorv32_xip is -- SPI device interface -- spi_csn_o : out std_ulogic; -- chip-select, low-active spi_clk_o : out std_ulogic; -- serial clock - spi_data_i : in std_ulogic; -- device data output - spi_data_o : out std_ulogic -- controller data output + spi_dat_i : in std_ulogic; -- device data output + spi_dat_o : out std_ulogic -- controller data output ); end neorv32_xip; @@ -160,8 +160,8 @@ architecture neorv32_xip_rtl of neorv32_xip is -- SPI interface -- spi_csn_o : out std_ulogic; spi_clk_o : out std_ulogic; - spi_data_i : in std_ulogic; - spi_data_o : out std_ulogic + spi_dat_i : in std_ulogic; + spi_dat_o : out std_ulogic ); end component; @@ -420,8 +420,8 @@ begin -- SPI interface -- spi_csn_o => spi_csn_o, spi_clk_o => spi_clk_o, - spi_data_i => spi_data_i, - spi_data_o => spi_data_o + spi_dat_i => spi_dat_i, + spi_dat_o => spi_dat_o ); @@ -437,7 +437,7 @@ end neorv32_xip_rtl; -- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # --- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # +-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # @@ -493,8 +493,8 @@ entity neorv32_xip_phy is -- SPI interface -- spi_csn_o : out std_ulogic; spi_clk_o : out std_ulogic; - spi_data_i : in std_ulogic; - spi_data_o : out std_ulogic + spi_dat_i : in std_ulogic; + spi_dat_o : out std_ulogic ); end neorv32_xip_phy; @@ -571,7 +571,7 @@ begin -- ------------------------------------------------------------ if (spi_clk_en_i = '1') then spi_clk_o <= not (cf_cpha_i xor cf_cpol_i); - ctrl.di_sync <= spi_data_i; + ctrl.di_sync <= spi_dat_i; ctrl.bitcnt <= std_ulogic_vector(unsigned(ctrl.bitcnt) - 1); ctrl.state <= S_RTX_B; end if; @@ -608,7 +608,7 @@ begin op_busy_o <= '0' when (ctrl.state = S_IDLE) or (ctrl.state = S_WAIT) else '1'; -- serial data output -- - spi_data_o <= ctrl.sreg(ctrl.sreg'left); + spi_dat_o <= ctrl.sreg(ctrl.sreg'left); -- RX data -- op_rdata_o <= ctrl.sreg(31 downto 0); diff --git a/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd b/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd index e436192ce..295cde416 100644 --- a/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd +++ b/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd @@ -235,9 +235,9 @@ begin uart0_cts_i => uart_cts_i, -- hw flow control: UART0.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => con_spi_sck, -- SPI serial clock - spi_sdo_o => con_spi_sdo, -- controller data out, peripheral data in - spi_sdi_i => con_spi_sdi, -- controller data in, peripheral data out + spi_clk_o => con_spi_sck, -- SPI serial clock + spi_dat_o => con_spi_sdo, -- controller data out, peripheral data in + spi_dat_i => con_spi_sdi, -- controller data in, peripheral data out spi_csn_o => con_spi_csn, -- SPI CS -- TWI (available if IO_TWI_EN = true) -- diff --git a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd index 6e1369043..841245c60 100644 --- a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd +++ b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd @@ -153,8 +153,8 @@ entity neorv32_top_avalonmm is -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o : out std_ulogic; -- chip-select, low-active xip_clk_o : out std_ulogic; -- serial clock - xip_sdi_i : in std_ulogic := 'L'; -- device data input - xip_sdo_o : out std_ulogic; -- controller data output + xip_dat_i : in std_ulogic := 'L'; -- device data input + xip_dat_o : out std_ulogic; -- controller data output -- GPIO (available if IO_GPIO_EN = true) -- gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output @@ -173,9 +173,9 @@ entity neorv32_top_avalonmm is uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o : out std_ulogic; -- SPI serial clock - spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in - spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_clk_o : out std_ulogic; -- SPI serial clock + spi_dat_o : out std_ulogic; -- controller data out, peripheral data in + spi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select -- TWI (available if IO_TWI_EN = true) -- @@ -343,8 +343,8 @@ begin -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o => xip_csn_o, xip_clk_o => xip_clk_o, - xip_sdi_i => xip_sdi_i, - xip_sdo_o => xip_sdo_o, + xip_dat_i => xip_dat_i, + xip_dat_o => xip_dat_o, -- GPIO (available if IO_GPIO_EN = true) -- gpio_o => gpio_o, @@ -363,9 +363,9 @@ begin uart1_cts_i => uart1_cts_i, -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => spi_sck_o, - spi_sdo_o => spi_sdo_o, - spi_sdi_i => spi_sdi_i, + spi_clk_o => spi_clk_o, + spi_dat_o => spi_dat_o, + spi_dat_i => spi_dat_i, spi_csn_o => spi_csn_o, -- TWI (available if IO_TWI_EN = true) -- diff --git a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd index 9ca374b0a..a357bbdee 100644 --- a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd +++ b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd @@ -162,8 +162,8 @@ entity neorv32_SystemTop_axi4lite is -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o : out std_logic; -- chip-select, low-active xip_clk_o : out std_logic; -- serial clock - xip_sdi_i : in std_logic := '0'; -- device data input - xip_sdo_o : out std_logic; -- controller data output + xip_dat_i : in std_logic := '0'; -- device data input + xip_dat_o : out std_logic; -- controller data output -- GPIO (available if IO_GPIO_EN = true) -- gpio_o : out std_logic_vector(63 downto 0); -- parallel output gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input @@ -178,9 +178,9 @@ entity neorv32_SystemTop_axi4lite is uart1_rts_o : out std_logic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional uart1_cts_i : in std_logic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o : out std_logic; -- SPI serial clock - spi_sdo_o : out std_logic; -- controller data out, peripheral data in - spi_sdi_i : in std_logic := '0'; -- controller data in, peripheral data out + spi_clk_o : out std_logic; -- SPI serial clock + spi_dat_o : out std_logic; -- controller data out, peripheral data in + spi_dat_i : in std_logic := '0'; -- controller data in, peripheral data out spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS -- TWI (available if IO_TWI_EN = true) -- twi_sda_io : inout std_logic; -- twi serial data line @@ -221,8 +221,8 @@ architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is -- signal xip_csn_o_int : std_ulogic; signal xip_clk_o_int : std_ulogic; - signal xip_sdi_i_int : std_ulogic; - signal xip_sdo_o_int : std_ulogic; + signal xip_dat_i_int : std_ulogic; + signal xip_dat_o_int : std_ulogic; -- signal gpio_o_int : std_ulogic_vector(63 downto 0); signal gpio_i_int : std_ulogic_vector(63 downto 0); @@ -237,9 +237,9 @@ architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is signal uart1_rts_o_int : std_ulogic; signal uart1_cts_i_int : std_ulogic; -- - signal spi_sck_o_int : std_ulogic; - signal spi_sdo_o_int : std_ulogic; - signal spi_sdi_i_int : std_ulogic; + signal spi_clk_o_int : std_ulogic; + signal spi_dat_o_int : std_ulogic; + signal spi_dat_i_int : std_ulogic; signal spi_csn_o_int : std_ulogic_vector(07 downto 0); -- signal pwm_o_int : std_ulogic_vector(11 downto 0); @@ -391,8 +391,8 @@ begin -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o => xip_csn_o_int, -- chip-select, low-active xip_clk_o => xip_clk_o_int, -- serial clock - xip_sdi_i => xip_sdi_i_int, -- device data input - xip_sdo_o => xip_sdo_o_int, -- controller data output + xip_dat_i => xip_dat_i_int, -- device data input + xip_dat_o => xip_dat_o_int, -- controller data output -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => gpio_o_int, -- parallel output gpio_i => gpio_i_int, -- parallel input @@ -407,9 +407,9 @@ begin uart1_rts_o => uart1_rts_o_int, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional uart1_cts_i => uart1_cts_i_int, -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => spi_sck_o_int, -- SPI serial clock - spi_sdo_o => spi_sdo_o_int, -- controller data out, peripheral data in - spi_sdi_i => spi_sdi_i_int, -- controller data in, peripheral data out + spi_clk_o => spi_clk_o_int, -- SPI serial clock + spi_dat_o => spi_dat_o_int, -- controller data out, peripheral data in + spi_dat_i => spi_dat_i_int, -- controller data in, peripheral data out spi_csn_o => spi_csn_o_int, -- SPI CS -- TWI (available if IO_TWI_EN = true) -- twi_sda_io => twi_sda_io, -- twi serial data line @@ -434,8 +434,8 @@ begin -- type conversion -- xip_csn_o <= std_logic(xip_csn_o_int); xip_clk_o <= std_logic(xip_clk_o_int); - xip_sdi_i_int <= std_ulogic(xip_sdi_i); - xip_sdo_o <= std_logic(xip_sdo_o_int); + xip_dat_i_int <= std_ulogic(xip_dat_i); + xip_dat_o <= std_logic(xip_dat_o_int); gpio_o <= std_logic_vector(gpio_o_int); gpio_i_int <= std_ulogic_vector(gpio_i); @@ -455,9 +455,9 @@ begin uart1_rts_o <= std_logic(uart1_rts_o_int); uart1_cts_i_int <= std_ulogic(uart1_cts_i); - spi_sck_o <= std_logic(spi_sck_o_int); - spi_sdo_o <= std_logic(spi_sdo_o_int); - spi_sdi_i_int <= std_ulogic(spi_sdi_i); + spi_clk_o <= std_logic(spi_clk_o_int); + spi_dat_o <= std_logic(spi_dat_o_int); + spi_dat_i_int <= std_ulogic(spi_dat_i); spi_csn_o <= std_logic_vector(spi_csn_o_int); pwm_o <= std_logic_vector(pwm_o_int); diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd index 2dea756ab..5b2f823d3 100644 --- a/sim/neorv32_tb.vhd +++ b/sim/neorv32_tb.vhd @@ -316,8 +316,8 @@ begin -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o => open, -- chip-select, low-active xip_clk_o => open, -- serial clock - xip_sdi_i => '1', -- device data input - xip_sdo_o => open, -- controller data output + xip_dat_i => '1', -- device data input + xip_dat_o => open, -- controller data output -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => gpio, -- parallel output gpio_i => gpio, -- parallel input @@ -332,9 +332,9 @@ begin uart1_rts_o => uart1_cts, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional uart1_cts_i => uart1_cts, -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => open, -- SPI serial clock - spi_sdo_o => spi_data, -- controller data out, peripheral data in - spi_sdi_i => spi_data, -- controller data in, peripheral data out + spi_clk_o => open, -- SPI serial clock + spi_dat_o => spi_data, -- controller data out, peripheral data in + spi_dat_i => spi_data, -- controller data in, peripheral data out spi_csn_o => open, -- SPI CS -- TWI (available if IO_TWI_EN = true) -- twi_sda_io => twi_sda, -- twi serial data line diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd index 0710c90cd..1f21695b8 100644 --- a/sim/simple/neorv32_tb.simple.vhd +++ b/sim/simple/neorv32_tb.simple.vhd @@ -268,8 +268,8 @@ begin -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o => open, -- chip-select, low-active xip_clk_o => open, -- serial clock - xip_sdi_i => '0', -- device data input - xip_sdo_o => open, -- controller data output + xip_dat_i => '0', -- device data input + xip_dat_o => open, -- controller data output -- GPIO (available if IO_GPIO_NUM > true) -- gpio_o => gpio, -- parallel output gpio_i => gpio, -- parallel input @@ -284,9 +284,9 @@ begin uart1_rts_o => uart1_cts, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional uart1_cts_i => uart1_cts, -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => open, -- SPI serial clock - spi_sdo_o => spi_data, -- controller data out, peripheral data in - spi_sdi_i => spi_data, -- controller data in, peripheral data out + spi_clk_o => open, -- SPI serial clock + spi_dat_o => spi_data, -- controller data out, peripheral data in + spi_dat_i => spi_data, -- controller data in, peripheral data out spi_csn_o => open, -- SPI CS -- TWI (available if IO_TWI_EN = true) -- twi_sda_io => twi_sda, -- twi serial data line