From 8c8fa516fd6e33438aceb4e2c971e0dbf5a57b9b Mon Sep 17 00:00:00 2001 From: NikLeberg Date: Tue, 31 Jan 2023 20:20:17 +0000 Subject: [PATCH] [docs] add note about platform specific DTMs --- docs/datasheet/on_chip_debugger.adoc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/datasheet/on_chip_debugger.adoc b/docs/datasheet/on_chip_debugger.adoc index 6a0c77456..cb69252fe 100644 --- a/docs/datasheet/on_chip_debugger.adoc +++ b/docs/datasheet/on_chip_debugger.adoc @@ -150,6 +150,12 @@ register. The following table shows the available data registers and their addre See the https://github.com/riscv/riscv-debug-spec[RISC-V debug specification] for more information regarding the data registers and operations. A local copy can be found in `docs/references`. +[NOTE] +Most FPGAs are programmed over a JTAG connection itself and support the use of it in user designs with instantiation of +platform-specific entities. So instead of two JTAG connections, one to program the FPGA and one to debug the core, +only one connection is needed. See the setups in [`neorv32-setups`](https://github.com/stnolting/neorv32-setups) +for example implementations. + <<<