From da7a59986ec7b273341de22c1ea1e177ff64017d Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 7 Aug 2021 16:33:04 +0200 Subject: [PATCH 01/13] added rtl/test_setups * README to illustrate test setups * test setups VHDL files (can be uses as TOPs) * adapted GHDL setup script --- rtl/test_setups/README.md | 53 +++++++++ rtl/test_setups/neorv32_test_setup_approm.vhd | 97 ++++++++++++++++ .../neorv32_test_setup_bootloader.vhd | 104 ++++++++++++++++++ sim/ghdl.setup.sh | 1 + 4 files changed, 255 insertions(+) create mode 100644 rtl/test_setups/README.md create mode 100644 rtl/test_setups/neorv32_test_setup_approm.vhd create mode 100644 rtl/test_setups/neorv32_test_setup_bootloader.vhd diff --git a/rtl/test_setups/README.md b/rtl/test_setups/README.md new file mode 100644 index 000000000..4842941d2 --- /dev/null +++ b/rtl/test_setups/README.md @@ -0,0 +1,53 @@ +# Test Setups + +This folder contains very simple test setups that are intended for project beginners +to setup a minimal NEORV32 SoC. These setups are used in the :books: +[NEORV32 User Guide](https://stnolting.github.io/neorv32/ug/). + +:information_source: Note that these setups provides a minimalistic configuration to keep +things at a simple level at first. Additional CPU ISA extensions, performance options and +optional peripheral modules can be enabled by specifying the according :book: +[configuration generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics). + + +### Setup's Top Entity + +#### Clocking and Reset + +All test setups require an external clock (via `clk_i` signal) and an external +low-active reset (via `rstn_i` signal). + +#### Configuration Generics + +Each setup provides three elementary generics that can/should be adapted to fit +your FPGA/board. + +* The clock speed in Hz **has to be specified** via the `CLOCK_SPEED` generic to fit your clock source. +* The processor-internal instruction memory (IMEM) size _can be modified_ via the `MEM_INT_IMEM_SIZE` generic. +* The processor-internal data memory (DMEM) size _can be modified_ via the `MEM_INT_DMEM_SIZE` generic. +Note that this might require adaption of the NEORV32 linker script. + + +### [`neorv32_test_setup_approm.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_approm.vhd) + +This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as pre-initialized ROM), +8kB DMEM and includes the GPIO module to drive 8 external signals (`gpio_o`) +and the MTIME module for generating timer interrupts. +The setup uses the [indidrect boot](https://stnolting.github.io/neorv32/#_indirect_boot) +configuration, so software applications are "installed" directly into the +processor-internal IMEM during synthesis. + +:books: See User Guide section +[_Uploading and Starting of a Binary Executable Image via UART_](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart). + + +### [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) + +This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as RAM), 8kB DMEM +and includes the GPIO module to drive 8 external signals (`gpio_o`), the MTIME +module for generating timer interrupts and UART0 to interface with the bootloader +(via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal. +The setup uses the [direct boot](https://stnolting.github.io/neorv32/#_direct_boot) +configuration, so software applications can be uploaded and run at any timer via a serial terminal. + +:books: See User Guide section [_Installing an Executable Directly Into Memory_](https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory). diff --git a/rtl/test_setups/neorv32_test_setup_approm.vhd b/rtl/test_setups/neorv32_test_setup_approm.vhd new file mode 100644 index 000000000..d90e9d6e0 --- /dev/null +++ b/rtl/test_setups/neorv32_test_setup_approm.vhd @@ -0,0 +1,97 @@ +-- ################################################################################################# +-- # << NEORV32 - Test Setup using the internal IMEM as ROM to run pre-installed executables >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_testsetup_approm is + generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 100000000; -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0) -- parallel output + ); +end entity; + +architecture neorv32_testsetup_approm_rtl of neorv32_testsetup_approm is + + signal con_gpio_o : std_ulogic_vector(63 downto 0); + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => true, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true -- implement machine system timer (MTIME)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o -- parallel output + ); + + -- GPIO output -- + gpio_o <= con_gpio_o(7 downto 0); + + +end architecture; diff --git a/rtl/test_setups/neorv32_test_setup_bootloader.vhd b/rtl/test_setups/neorv32_test_setup_bootloader.vhd new file mode 100644 index 000000000..ca50dbe3c --- /dev/null +++ b/rtl/test_setups/neorv32_test_setup_bootloader.vhd @@ -0,0 +1,104 @@ +-- ################################################################################################# +-- # << NEORV32 - Test Setup using the UART-Bootloader to upload and run executables >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_testsetup_bootloader is + generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 100000000; -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output + -- UART0 -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic -- UART0 receive data + ); +end entity; + +architecture neorv32_testsetup_bootloader_rtl of neorv32_testsetup_bootloader is + + signal con_gpio_o : std_ulogic_vector(63 downto 0); + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => true, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o, -- UART0 send data + uart0_rxd_i => uart0_rxd_i -- UART0 receive data + ); + + -- GPIO output -- + gpio_o <= con_gpio_o(7 downto 0); + + +end architecture; diff --git a/sim/ghdl.setup.sh b/sim/ghdl.setup.sh index 43c15b430..81e1261e0 100755 --- a/sim/ghdl.setup.sh +++ b/sim/ghdl.setup.sh @@ -10,5 +10,6 @@ ghdl -i --work=neorv32 --workdir=build \ ../rtl/core/*.vhd \ ../rtl/templates/processor/*.vhd \ ../rtl/templates/system/*.vhd \ + ../rtl/test_setups/*.vhd \ neorv32_tb.simple.vhd \ uart_rx.simple.vhd From c05b9f05c9fd4a90abd2dd238f3b57843e08f1e5 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 7 Aug 2021 16:38:00 +0200 Subject: [PATCH 02/13] [docs/userguide] now using test_setups + minor edits --- docs/userguide/content.adoc | 167 ++++++++++++++++++++---------------- 1 file changed, 92 insertions(+), 75 deletions(-) diff --git a/docs/userguide/content.adoc b/docs/userguide/content.adoc index 480536133..6d12e3f4f 100644 --- a/docs/userguide/content.adoc +++ b/docs/userguide/content.adoc @@ -1,7 +1,15 @@ Let's Get It Started! -To make your NEORV32 project run, follow the guides from the upcoming sections. Follow these guides -step by step and in the presented order. +This user guide uses the NEORV32 project _as is_ from the official `neorv32` repository. +To make your first NEORV32 project run, follow the guides from the upcoming sections. It is recommended to +follow these guides step by step and eventually in the presented order. + +[TIP] +This guide uses the minimalistic and platform/toolchain agnostic SoC test setups from +`rtl/test_setups` for illustration. You can use one of the provided test setups for +your first FPGA tests. Alternatively, have a look at the `setups` folder, +which provides more sophisticated example setups for various FPGAs/FPGA boards and toolchains. + :sectnums: == Software Toolchain Setup @@ -9,18 +17,13 @@ step by step and in the presented order. To compile (and debug) executables for the NEORV32 a RISC-V toolchain is required. There are two possibilities to get this: -1. Download and _build_ the official RISC-V GNU toolchain yourself +1. Download and _build_ the official RISC-V GNU toolchain yourself. 2. Download and install a prebuilt version of the toolchain; this might also done via the package manager / app store of your OS -[TIP] -The default toolchain prefix for this project is **`riscv32-unknown-elf-`**. Of course you can use any other RISC-V -toolchain (like `riscv64-unknown-elf-`) that is capable to emit code for a `rv32` architecture. Just change the _RISCV_PREFIX_ variable in the application -makefile(s) according to your needs or define this variable when invoking the makefile. - -[IMPORTANT] -Keep in mind that – for instance – a rv32imc toolchain only provides library code compiled with -compressed (_C_) and `mul`/`div` instructions (_M_)! Hence, this code cannot be executed (without -emulation) on an architecture without these extensions! +[NOTE] +The default toolchain prefix (`RISCV_PREFIX` variable) for this project is **`riscv32-unknown-elf-`**. Of course you can use any other RISC-V +toolchain (like `riscv64-unknown-elf-`) that is capable to emit code for a `rv32` architecture. Just change `RISCV_PREFIX` +according to your needs. :sectnums: @@ -39,6 +42,11 @@ riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i –-with- riscv-gnu-toolchain$ make ---- +[IMPORTANT] +Keep in mind that – for instance – a toolchain build with `--with-arch=rv32imc` only provides library code compiled with +compressed (`C`) and `mul`/`div` instructions (`M`)! Hence, this code cannot be executed (without +emulation) on an architecture without these extensions! + :sectnums: === Downloading and Installing a Prebuilt Toolchain @@ -103,114 +111,123 @@ Everything is working fine if `Toolchain check OK` appears at the end. :sectnums: == General Hardware Setup -This guide will setup a NEORV32 project for FPGA implementation (or simulation only) _from scratch_ +This guide shows the basics of setting up a NEORV32 project for FPGA implementation (or simulation only) +_from scratch_. It uses a _simplified_ test "SoC" setup of the processor to keeps things simple at the beginning. +This simple setup is intended for evaluation or as "hello world" project to check out the NEORV32 +on _your_ FPGA board. [TIP] -If you want to use a complete pre-defined setup to start with, check out the -project's `setups` folder (https://github.com/stnolting/neorv32/tree/master/setups), -which provides (script-based) demo setups for various FPGA boards and toolchains. +If you want to use a more sophisticated pre-defined setup to start with, check out the +`setups` folder, which provides example setups for various FPGA, boards and toolchains. + +The NEORV32 project features two minimalistic pre-built test setups. Both test setups only implements +some very basic processor and CPU features. +The main difference is the processor boot concept - so how to get a software executable +into the processor: + +* **`rtl/test_setups/neorv32_testsetup_approm.vhd`**: this setup does not require a connection via UART. The +software executable is "installed" into the bitstream to initialize a read-only memory. Use this setup +if your FPGA board does not provide a UART interface. +* **`rtl/test_setups/neorv32_testsetup_bootloader.vhd`**: this setups uses the UART and the default NEORV32 +bootloader to upload new software executables. Use this setup if your board provides a UART interface. -This tutorial uses a _simplified_ test setup of the processor -to keeps things simple at the beginning as this setup is intended as -evaluation or "hello world" project to check out the NEORV32. +.NEORV32 "hello world" test setup (`rtl/test_setups/neorv32_testsetup_bootloader.vhd`) +image::neorv32_test_setup.png[align=center] [start=1] . Create a new project with your FPGA EDA tool of choice. -. Add all VHDL files from the project's `rtl/core` folder to your project. Make sure to _reference_ the -files only – do not copy them. +. Add all VHDL files from the project's `rtl/core` folder to your project. . Make sure to add all the rtl files to a new library called `neorv32`. If your FPGA tools does not provide a field to enter the library name, check out the "properties" menu of the added rtl files. -. The `rtl/core/neorv32_top.vhd` VHDL file is the top entity of the NEORV32 processor. If you -already have a design, instantiate this unit into your design and proceed. +. The `rtl/core/neorv32_top.vhd` VHDL file is the top entity of the NEORV32 processor, which can be +instantiated into the "real" project. However, in this tutorial we will use one of the pre-defined +test setups from `rtl/test_setups` (see above). [IMPORTANT] Make sure to include the `neorv32` package into your design when instantiating the processor: add `library neorv32;` and `use neorv32.neorv32_package.all;` to your design unit. [start=5] -. If you do not have a design yet and just want to check out the NEORV32 – no problem! This guide -uses a simplified top entity, that encapsulates the actual processor top entity: add the -`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` VHDL file to your project, too, and -select it as _top entity_. -. This test setup provides a minimal test hardware setup: - -.NEORV32 "hello world" test setup -image::neorv32_test_setup.png[align=center] +. Add the pre-defined test setup of choice to the project, too, and select it as _top entity_. +. The entity of both test setups +provide a minimal set of configuration generics, that might have to be adapted to match your FPGA and board: -[start=7] -. It only implements some very basic processor and CPU features. Also, only the -minimum number of signals is propagated to the outer world. -. However, a minimal setup-specific configuration of the NEORV32 processor is required to make it run -on your FPGA board of choice. Only the absolutely required modifications will be made while -keeping the default configuration for the remaining configuration options: - -.Cut-out of `neorv32_ProcessorTop_Test.vhd` showing the processor instance and its configuration +.Test setup entity - configuration generics [source,vhdl] ---- -neorv32_top_inst: neorv32_top -generic map ( - -- General -- - CLOCK_FREQUENCY => 100000000, -- in Hz # <1> - INT_BOOTLOADER_EN => true, - ... - -- Internal instruction memory -- - MEM_INT_IMEM_EN => true, - MEM_INT_IMEM_SIZE => 16*1024, # <2> - -- Internal data memory -- - MEM_INT_DMEM_EN => true, - MEM_INT_DMEM_SIZE => 8*1024, # <3> - ... + generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 100000000; <1> + MEM_INT_IMEM_SIZE : natural := 16*1024; <2> + MEM_INT_DMEM_SIZE : natural := 8*1024 <3> + ); ---- <1> Clock frequency of `clk_i` signal in Hertz <2> Default size of internal instruction memory: 16kB <3> Default size of internal data memory: 8kB -[start=9] -. There is one generic that has to be set according to your FPGA board setup: the actual clock frequency -of the top's clock input signal (`clk_i`). Use the _CLOCK_FREQUENC_Y generic to specify your clock source's -frequency in Hertz (Hz) (note "1"). -. If you feel like it – or if your FPGA does not provide many resources – you can modify the -**memory sizes** (_MEM_INT_IMEM_SIZE_ and _MEM_INT_DMEM_SIZE_ – marked with notes "2" and "3") or even -exclude certain ISA extensions and peripheral modules from implementation - but as mentioned above, let's keep things -simple at first and use the standard configuration for now. +[start=7] +. If you feel like it – or if your FPGA does not provide sufficient resources – you can modify the +_memory sizes_ (`MEM_INT_IMEM_SIZE` and `MEM_INT_DMEM_SIZE` – marked with notes "2" and "3"). But as mentioned +above, let's keep things simple at first and use the standard configuration for now. +. There is one generic that _has to be set according to your FPGA board_ setup: the actual clock frequency +of the top's clock input signal (`clk_i`). Use the `CLOCK_FREQUENCY` generic to specify your clock source's +frequency in Hertz (Hz). [NOTE] -If you have changed the default memory configuration (_MEM_INT_IMEM_SIZE_ and _MEM_INT_DMEM_SIZE_ generics) +If you have changed the default memory configuration (`MEM_INT_IMEM_SIZE` and `MEM_INT_DMEM_SIZE` generics) keep those new sizes in mind – these values are required for setting up the software framework in the next section <<_general_software_framework_setup>>. -[start=11] +[start=9] . Depending on your FPGA tool of choice, it is time to assign the signals of the test setup top entity to -the according pins of your FPGA board. All the signals can be found in the entity declaration: +the according pins of your FPGA board. All the signals can be found in the entity declaration of the +corresponding test setup: + +.Entity signals of `neorv32_testsetup_approm.vhd` +[source,vhdl] +---- + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0) -- parallel output + ); +---- -.Entity signals of `neorv32_test_setup.vhd` +.Entity signals of `neorv32_testsetup_bootloader.vhd` [source,vhdl] ---- -entity neorv32_test_setup is port ( -- Global control -- - clk_i : in std_ulogic := '0'; -- global clock, rising edge - rstn_i : in std_ulogic := '0'; -- global reset, low-active, async + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async -- GPIO -- gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output -- UART0 -- uart0_txd_o : out std_ulogic; -- UART0 send data - uart0_rxd_i : in std_ulogic := '0' -- UART0 receive data -); -end neorv32_test_setup; + uart0_rxd_i : in std_ulogic -- UART0 receive data + ); ---- -[start=12] +[start=10] . Attach the clock input `clk_i` to your clock source and connect the reset line `rstn_i` to a button of your FPGA board. Check whether it is low-active or high-active – the reset signal of the processor is **low-active**, so maybe you need to invert the input signal. . If possible, connected at least bit `0` of the GPIO output port `gpio_o` to a high-active LED (invert -the signal when your LEDs are low-active). This LED will be used as status LED for the setup. -. Finally, if your FPGA board provides a serial host interface (USB-to-serial converter) interface, -connect the UART communication signals `uart0_txd_o` and `uart0_rxd_i`. +the signal when your LEDs are low-active). +. Finally, if your are using the UART-based test setup (`neorv32_testsetup_bootloader.vhd`) +connect the UART communication signals `uart0_txd_o` and `uart0_rxd_i` to the host interface (e.g. USB-UART converter). . Perform the project HDL compilation (synthesis, mapping, bitstream generation). . Program the generated bitstream into your FPGA and press the button connected to the reset signal. -. Done! The assigned status LED should be flashing now for some sections before permanently lighting up. +. Done! The LED at `gpio_o(0)` should be flashing now. + +[TIP] +After the GCC toolchain for compiling RISC-V source code is ready (chapter <<_general_software_framework_setup>>), +you can advance to one of these chapters to learn how to get a software executable into your processor setup: +* If you are using the `neorv32_testsetup_approm.vhd` setup: See section <<_installing_an_executable_directly_into_memory>>. +* If you are using the `neorv32_testsetup_bootloader.vhd` setup: See section <<_uploading_and_starting_of_a_binary_executable_image_via_uart>>. From 80f7f2c00f26a023acb201e8b303dd01c3025577 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 7 Aug 2021 16:40:57 +0200 Subject: [PATCH 03/13] [rtl] added test_setups to rtl/README.md --- rtl/README.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/rtl/README.md b/rtl/README.md index b537860a7..c92e4d8aa 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -1,11 +1,21 @@ ## VHDL Source Folders + ### [`core`](https://github.com/stnolting/neorv32/tree/master/rtl/core) This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor. When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a *new design library* called `neorv32`. + +### [`test_setups`](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups`) + +Minimal test setups (FPGA- and board-independent) for the processor. See the +[README](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups`) +in that folder for more information. Note that these test setups are used in the +[NEORV32 USer Guide](https://stnolting.github.io/neorv32/ug). + + ### [`templates`](https://github.com/stnolting/neorv32/tree/master/rtl/templates) Alternative top entities / wrappers for the NEORV32 Processor. From 837e1f173ddc28961c861852636487ec32dd5237 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 7 Aug 2021 16:44:02 +0200 Subject: [PATCH 04/13] [docs/datasheet/overview] added test_setups folder --- docs/datasheet/overview.adoc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/datasheet/overview.adoc b/docs/datasheet/overview.adoc index 5abb9f47c..222296585 100644 --- a/docs/datasheet/overview.adoc +++ b/docs/datasheet/overview.adoc @@ -157,7 +157,8 @@ neorv32 - Project home folder │├core - Core sources of the CPU & SoC │└templates - Alternate/additional top entities & wrappers │ ├processor - Processor SoC wrappers -│ └system - System wrappers for advanced connectivity +│ ├system - System wrappers for advanced connectivity +│ └test_setups - Minimal test setup "SoCs" used in the User Guide │ ├setups - Example setups for various FPGAs, boards and toolchains │└... From b961af3c79f16ae13d8d0298373323c8c4fe576b Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 7 Aug 2021 16:58:09 +0200 Subject: [PATCH 05/13] minor typo fix in README --- rtl/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/README.md b/rtl/README.md index c92e4d8aa..baf17c271 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -11,7 +11,7 @@ When creating a new synthesis/simulation project make sure that all `*.vhd` file ### [`test_setups`](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups`) Minimal test setups (FPGA- and board-independent) for the processor. See the -[README](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups`) +[README](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups) in that folder for more information. Note that these test setups are used in the [NEORV32 USer Guide](https://stnolting.github.io/neorv32/ug). From 8e02127153055ff51d1b371f582a4c54c2b17f40 Mon Sep 17 00:00:00 2001 From: stnolting Date: Mon, 9 Aug 2021 17:42:07 +0200 Subject: [PATCH 06/13] [rtl/test_setups/README] fixed links to user guide --- rtl/test_setups/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/test_setups/README.md b/rtl/test_setups/README.md index 4842941d2..f1f2dea01 100644 --- a/rtl/test_setups/README.md +++ b/rtl/test_setups/README.md @@ -37,8 +37,7 @@ The setup uses the [indidrect boot](https://stnolting.github.io/neorv32/#_indire configuration, so software applications are "installed" directly into the processor-internal IMEM during synthesis. -:books: See User Guide section -[_Uploading and Starting of a Binary Executable Image via UART_](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart). +:books: See User Guide section [_Installing an Executable Directly Into Memory_](https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory). ### [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) @@ -50,4 +49,5 @@ module for generating timer interrupts and UART0 to interface with the bootloade The setup uses the [direct boot](https://stnolting.github.io/neorv32/#_direct_boot) configuration, so software applications can be uploaded and run at any timer via a serial terminal. -:books: See User Guide section [_Installing an Executable Directly Into Memory_](https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory). +:books: See User Guide section +[_Uploading and Starting of a Binary Executable Image via UART_](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart). From 7c3967f074e3a3c9dbe0a33ab1926b1dc71dc2a3 Mon Sep 17 00:00:00 2001 From: stnolting Date: Mon, 9 Aug 2021 17:54:20 +0200 Subject: [PATCH 07/13] [docs/userguide] added signal polarity note --- docs/userguide/content.adoc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/docs/userguide/content.adoc b/docs/userguide/content.adoc index 6d12e3f4f..affc57a4e 100644 --- a/docs/userguide/content.adoc +++ b/docs/userguide/content.adoc @@ -211,12 +211,18 @@ corresponding test setup: ); ---- +.Signal Polarity +[NOTE] +If your FPGA board has inverse polarity for certain input/output you can add `not` gates. Example: The reset signal +`rstn_i` is low-active by default; the LEDs connected to `gpio_o` high-active by default. +You can do this in your board top if you instantiate the test setup, +or _inside_ the test setup if this is your top entity (low-active LEDs example: `gpio_o <= NOT con_gpio_o(7 downto 0);`). + [start=10] . Attach the clock input `clk_i` to your clock source and connect the reset line `rstn_i` to a button of your FPGA board. Check whether it is low-active or high-active – the reset signal of the processor is **low-active**, so maybe you need to invert the input signal. -. If possible, connected at least bit `0` of the GPIO output port `gpio_o` to a high-active LED (invert -the signal when your LEDs are low-active). +. If possible, connected _at least_ bit `0` of the GPIO output port `gpio_o` to a LED (see "Signal Polarity" note above). . Finally, if your are using the UART-based test setup (`neorv32_testsetup_bootloader.vhd`) connect the UART communication signals `uart0_txd_o` and `uart0_rxd_i` to the host interface (e.g. USB-UART converter). . Perform the project HDL compilation (synthesis, mapping, bitstream generation). From b3797af5790a8c547e41d5d983f3677c1cd860b1 Mon Sep 17 00:00:00 2001 From: stnolting Date: Mon, 9 Aug 2021 18:06:32 +0200 Subject: [PATCH 08/13] [docs/userguide] added note: (too fast) external clock --- docs/userguide/content.adoc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/docs/userguide/content.adoc b/docs/userguide/content.adoc index affc57a4e..c86f1f686 100644 --- a/docs/userguide/content.adoc +++ b/docs/userguide/content.adoc @@ -134,6 +134,13 @@ bootloader to upload new software executables. Use this setup if your board prov .NEORV32 "hello world" test setup (`rtl/test_setups/neorv32_testsetup_bootloader.vhd`) image::neorv32_test_setup.png[align=center] +.External Clock Source +[NOTE] +These test setups are intended to be directly used as **design top entity**. Of course you can also instantiate them +into another design unit. If your FPGA board only provides _very fast_ external clock sources (like on the FOMU board) +you might need to add clock management components (PLLs, DCMs, MMCMs, ...) to the test setup or to the according top entity +if you instantiate one of the test setups. + [start=1] . Create a new project with your FPGA EDA tool of choice. . Add all VHDL files from the project's `rtl/core` folder to your project. From 9c593549c1e1e288cce50abba0e5c2a0e2e7be21 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 14 Aug 2021 09:08:27 +0200 Subject: [PATCH 09/13] [userguide] added link to new test_setups folder --- docs/userguide/content.adoc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/docs/userguide/content.adoc b/docs/userguide/content.adoc index c86f1f686..6a80a5259 100644 --- a/docs/userguide/content.adoc +++ b/docs/userguide/content.adoc @@ -120,16 +120,17 @@ on _your_ FPGA board. If you want to use a more sophisticated pre-defined setup to start with, check out the `setups` folder, which provides example setups for various FPGA, boards and toolchains. -The NEORV32 project features two minimalistic pre-built test setups. Both test setups only implements -some very basic processor and CPU features. -The main difference is the processor boot concept - so how to get a software executable -into the processor: +The NEORV32 project features two minimalistic pre-configured test setups in +https://github.com/stnolting/neorv32/blob/master/rtl/test_setups[`rtl/test_setups`]. +Both test setups only implement very basic processor and CPU features. +The main difference between the two setups is the processor boot concept - so how to get a software executable +_into_ the processor: * **`rtl/test_setups/neorv32_testsetup_approm.vhd`**: this setup does not require a connection via UART. The software executable is "installed" into the bitstream to initialize a read-only memory. Use this setup -if your FPGA board does not provide a UART interface. +if your FPGA board does _not_ provide a UART interface. * **`rtl/test_setups/neorv32_testsetup_bootloader.vhd`**: this setups uses the UART and the default NEORV32 -bootloader to upload new software executables. Use this setup if your board provides a UART interface. +bootloader to upload new software executables. Use this setup if your board _does_ provide a UART interface. .NEORV32 "hello world" test setup (`rtl/test_setups/neorv32_testsetup_bootloader.vhd`) image::neorv32_test_setup.png[align=center] From 31475399bcb58619f0b69c8ffda18294e3b9c477 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 14 Aug 2021 09:22:08 +0200 Subject: [PATCH 10/13] [rtl] removed deprecated templates/test_setup rtl/test_setups/neorv32_test_setup_bootloader.vhd provides the same functionality and is illustrated in the user guide --- rtl/templates/README.md | 6 - .../processor/neorv32_ProcessorTop_Test.vhd | 194 ------------------ 2 files changed, 200 deletions(-) delete mode 100644 rtl/templates/processor/neorv32_ProcessorTop_Test.vhd diff --git a/rtl/templates/README.md b/rtl/templates/README.md index e7fe6a3e7..e4cf73184 100644 --- a/rtl/templates/README.md +++ b/rtl/templates/README.md @@ -16,12 +16,6 @@ This setup provides the minimal I/O, for testing the smallest possible design on This processor setup provides 64kB of data and instruction memory, an RTOS-capable CPU (privileged architecture) and a set of standard peripherals like UART, TWI and SPI. -#### [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) - -This entity is intended as "FPGA hello world" example for playing with the NEORV32. It uses only some of the -provided peripherals and provides a very simple and basic interface - only the clock, reset, UART and a subset -of the GPIO output port are propagated to the outer world. - #### [`neorv32_ProcessorTop_stdlogic.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_stdlogic.vhd) Same entity (generics and interface ports) as the default NEORV32 Processor top entity (`rtl/core/neorv32_top.vhd`), diff --git a/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd b/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd deleted file mode 100644 index d6dce1f80..000000000 --- a/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Simple Test Setup >> # --- # ********************************************************************************************* # --- # This test setup instantiates the NEORV32 processor with a rather small configuration and only # --- # propagates the UART and GPIO.out signals to the outer world. # --- # Only internal memories are used and the address space for instructions/data is constrained to # --- # these memories. # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library neorv32; -use neorv32.neorv32_package.all; - -entity neorv32_ProcessorTop_Test is - port ( - -- Global control -- - clk_i : in std_ulogic := '0'; -- global clock, rising edge - rstn_i : in std_ulogic := '0'; -- global reset, low-active, async - -- GPIO -- - gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output - -- UART0 -- - uart0_txd_o : out std_ulogic; -- UART0 send data - uart0_rxd_i : in std_ulogic := '0' -- UART0 receive data - ); -end entity; - -architecture neorv32_ProcessorTop_Test_rtl of neorv32_ProcessorTop_Test is - - -- gpio output -- - signal gpio_out : std_ulogic_vector(63 downto 0); - -begin - - -- The Core Of The Problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_top_inst: neorv32_top - generic map ( - -- General -- - CLOCK_FREQUENCY => 100000000, -- clock frequency of clk_i in Hz - INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM - USER_CODE => x"00000000", -- custom user code - HW_THREAD_ID => 0, -- hardware thread id (hartid) - -- On-Chip Debugger (OCD) -- - ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger - -- RISC-V CPU Extensions -- - CPU_EXTENSION_RISCV_A => false, -- implement atomic extension? - CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? - CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? - CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension? - CPU_EXTENSION_RISCV_U => true, -- implement user mode extension? - CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!) - CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? - CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.? - -- Extension Options -- - FAST_MUL_EN => false, -- use DSPs for M extension's multiplier - FAST_SHIFT_EN => false, -- use barrel shifter for shift operations - CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64) - -- Physical Memory Protection (PMP) -- - PMP_NUM_REGIONS => 0, -- number of regions (0..64) - PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes - -- Hardware Performance Monitors (HPM) -- - HPM_NUM_CNTS => 4, -- number of implemented HPM counters (0..29) - HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64) - -- Internal Instruction memory -- - MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory - MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes - -- Internal Data memory -- - MEM_INT_DMEM_EN => true, -- implement processor-internal data memory - MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes - -- Internal Cache memory -- - ICACHE_EN => false, -- implement instruction cache - ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2 - ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 - ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 - -- External memory interface -- - MEM_EXT_EN => false, -- implement external memory bus interface? - MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) - -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? - IO_MTIME_EN => true, -- implement machine system timer (MTIME)? - IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? - IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? - IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? - IO_TWI_EN => false, -- implement two-wire interface (TWI)? - IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled - IO_WDT_EN => true, -- implement watch dog timer (WDT)? - IO_TRNG_EN => false, -- implement true random number generator (TRNG)? - IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? - IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic - IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits - IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits - IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? - ) - port map ( - -- Global control -- - clk_i => clk_i, -- global clock, rising edge - rstn_i => rstn_i, -- global reset, low-active, async - -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- - jtag_trst_i => '0', -- low-active TAP reset (optional) - jtag_tck_i => '0', -- serial clock - jtag_tdi_i => '0', -- serial data input - jtag_tdo_o => open, -- serial data output - jtag_tms_i => '0', -- mode select - -- Wishbone bus interface (available if MEM_EXT_EN = true) -- - wb_tag_o => open, -- tag - wb_adr_o => open, -- address - wb_dat_i => (others => '0'), -- read data - wb_dat_o => open, -- write data - wb_we_o => open, -- read/write - wb_sel_o => open, -- byte enable - wb_stb_o => open, -- strobe - wb_cyc_o => open, -- valid cycle - wb_lock_o => open, -- exclusive access request - wb_ack_i => '0', -- transfer acknowledge - wb_err_i => '0', -- transfer error - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => open, -- indicates an executed FENCE operation - fencei_o => open, -- indicates an executed FENCEI operation - -- GPIO (available if IO_GPIO_EN = true) -- - gpio_o => gpio_out, -- parallel output - gpio_i => (others => '0'), -- parallel input - -- primary UART0 (available if IO_UART0_EN = true) -- - uart0_txd_o => uart0_txd_o, -- UART0 send data - uart0_rxd_i => uart0_rxd_i, -- UART0 receive data - uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - -- secondary UART1 (available if IO_UART1_EN = true) -- - uart1_txd_o => open, -- UART1 send data - uart1_rxd_i => '0', -- UART1 receive data - uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional - uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional - -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => open, -- SPI serial clock - spi_sdo_o => open, -- controller data out, peripheral data in - spi_sdi_i => '0', -- controller data in, peripheral data out - spi_csn_o => open, -- SPI CS - -- TWI (available if IO_TWI_EN = true) -- - twi_sda_io => open, -- twi serial data line - twi_scl_io => open, -- twi serial clock line - -- PWM (available if IO_PWM_NUM_CH > 0) -- - pwm_o => open, -- pwm channels - -- Custom Functions Subsystem IO -- - cfs_in_i => (others => '0'), -- custom inputs - cfs_out_o => open, -- custom outputs - -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- - neoled_o => open, -- async serial data line - -- System time -- - mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) - mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) - -- Interrupts -- - nm_irq_i => '0', -- non-maskable interrupt - mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false - msw_irq_i => '0', -- machine software interrupt - mext_irq_i => '0' -- machine external interrupt - ); - - -- output -- - gpio_o <= gpio_out(7 downto 0); - - -end architecture; From 795a40e8b20e3cc95ac1a4ff4d69f9966d81542c Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 14 Aug 2021 09:24:42 +0200 Subject: [PATCH 11/13] [rtl/test_setup] typo fix --- rtl/test_setups/neorv32_test_setup_approm.vhd | 4 ++-- rtl/test_setups/neorv32_test_setup_bootloader.vhd | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/test_setups/neorv32_test_setup_approm.vhd b/rtl/test_setups/neorv32_test_setup_approm.vhd index d90e9d6e0..59440b572 100644 --- a/rtl/test_setups/neorv32_test_setup_approm.vhd +++ b/rtl/test_setups/neorv32_test_setup_approm.vhd @@ -39,7 +39,7 @@ use ieee.numeric_std.all; library neorv32; use neorv32.neorv32_package.all; -entity neorv32_testsetup_approm is +entity neorv32_test_setup_approm is generic ( -- adapt these for your setup -- CLOCK_FREQUENCY : natural := 100000000; -- clock frequency of clk_i in Hz @@ -55,7 +55,7 @@ entity neorv32_testsetup_approm is ); end entity; -architecture neorv32_testsetup_approm_rtl of neorv32_testsetup_approm is +architecture neorv32_test_setup_approm_rtl of neorv32_test_setup_approm is signal con_gpio_o : std_ulogic_vector(63 downto 0); diff --git a/rtl/test_setups/neorv32_test_setup_bootloader.vhd b/rtl/test_setups/neorv32_test_setup_bootloader.vhd index ca50dbe3c..31496cfa2 100644 --- a/rtl/test_setups/neorv32_test_setup_bootloader.vhd +++ b/rtl/test_setups/neorv32_test_setup_bootloader.vhd @@ -39,7 +39,7 @@ use ieee.numeric_std.all; library neorv32; use neorv32.neorv32_package.all; -entity neorv32_testsetup_bootloader is +entity neorv32_test_setup_bootloader is generic ( -- adapt these for your setup -- CLOCK_FREQUENCY : natural := 100000000; -- clock frequency of clk_i in Hz @@ -58,7 +58,7 @@ entity neorv32_testsetup_bootloader is ); end entity; -architecture neorv32_testsetup_bootloader_rtl of neorv32_testsetup_bootloader is +architecture neorv32_test_setup_bootloader_rtl of neorv32_test_setup_bootloader is signal con_gpio_o : std_ulogic_vector(63 downto 0); From c2b1bfff549f4050c31c5768dece92bf1f3c6c5b Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 14 Aug 2021 09:25:05 +0200 Subject: [PATCH 12/13] [quartus] now using new neorv32_test_setup_bootloader.vhd --- setups/quartus/de0-nano-test-setup/README.md | 6 +++--- setups/quartus/de0-nano-test-setup/create_project.tcl | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/setups/quartus/de0-nano-test-setup/README.md b/setups/quartus/de0-nano-test-setup/README.md index d4d64cdba..39ffe2cae 100644 --- a/setups/quartus/de0-nano-test-setup/README.md +++ b/setups/quartus/de0-nano-test-setup/README.md @@ -1,7 +1,7 @@ # NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board. -It uses the simplified [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity, which is a wrapper for the actual processor +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). * FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) @@ -11,7 +11,7 @@ top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs ### NEORV32 Configuration -:information_source: See the top entity [`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) for +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for configuration and entity details and `create_project.tcl` for the according FPGA pin mapping. * CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide) @@ -25,7 +25,7 @@ configuration and entity details and `create_project.tcl` for the according FPGA * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") -:warning: The default [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity +:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified. This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file (in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual diff --git a/setups/quartus/de0-nano-test-setup/create_project.tcl b/setups/quartus/de0-nano-test-setup/create_project.tcl index 59cea0afe..09af4c859 100644 --- a/setups/quartus/de0-nano-test-setup/create_project.tcl +++ b/setups/quartus/de0-nano-test-setup/create_project.tcl @@ -1,6 +1,6 @@ -# make a local copy of original "./../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd" file +# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file # and modify the default clock frequency: set to 50MHz -set shell_script "cp -f ./../../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd . && sed -i '/CLOCK_FREQUENCY/c\CLOCK_FREQUENCY => 50000000,' neorv32_ProcessorTop_Test.vhd" +set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd " exec sh -c $shell_script # Copyright (C) 2020 Intel Corporation. All rights reserved. @@ -48,7 +48,7 @@ if {[is_project_open]} { if {$make_assignments} { set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE22F17C6 - set_global_assignment -name TOP_LEVEL_ENTITY neorv32_ProcessorTop_Test + set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" @@ -64,7 +64,7 @@ if {$make_assignments} { } # top entity: use local modified copy of the original test setup - set_global_assignment -name VHDL_FILE "neorv32_ProcessorTop_Test.vhd" + set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" From a482d2153c00b7fa47a63209e0e06f93c97118d2 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sat, 14 Aug 2021 09:25:30 +0200 Subject: [PATCH 13/13] [vivado] now using new neorv32_test_setup_bootloader.vhd --- setups/vivado/arty-a7-test-setup/README.md | 4 ++-- setups/vivado/arty-a7-test-setup/create_project.tcl | 2 +- setups/vivado/nexys-a7-test-setup/README.md | 4 ++-- setups/vivado/nexys-a7-test-setup/create_project.tcl | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/setups/vivado/arty-a7-test-setup/README.md b/setups/vivado/arty-a7-test-setup/README.md index def0a0fd9..f241c329f 100644 --- a/setups/vivado/arty-a7-test-setup/README.md +++ b/setups/vivado/arty-a7-test-setup/README.md @@ -1,7 +1,7 @@ # NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board. -It uses the simplified [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity, which is a wrapper for the actual processor +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs). * FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual) @@ -11,7 +11,7 @@ top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs ## NEORV32 Configuration -:information_source: See the top entity [`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) for +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc) for the according FPGA pin mapping. diff --git a/setups/vivado/arty-a7-test-setup/create_project.tcl b/setups/vivado/arty-a7-test-setup/create_project.tcl index 1c6ec3179..7fd6f30fa 100644 --- a/setups/vivado/arty-a7-test-setup/create_project.tcl +++ b/setups/vivado/arty-a7-test-setup/create_project.tcl @@ -31,7 +31,7 @@ set_property target_language VHDL [current_project] set fileset_neorv32 [glob ./../../../rtl/core/*.vhd] ## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources -set fileset_design ./../../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd +set fileset_design ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd ## Constraints set fileset_constraints [glob ./*.xdc] diff --git a/setups/vivado/nexys-a7-test-setup/README.md b/setups/vivado/nexys-a7-test-setup/README.md index ff533b475..b41dc103d 100644 --- a/setups/vivado/nexys-a7-test-setup/README.md +++ b/setups/vivado/nexys-a7-test-setup/README.md @@ -1,7 +1,7 @@ # NEORV32 Test Setup for the Digilent Nexys A7 and Nexys 4 DDR FPGA Boards This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Nexys A7 and Nexys 4 DDR boards. -It uses the simplified [`neorv32_ProcessorTop_Test.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) top entity, which is a wrapper for the actual processor +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs). * FPGA Boards: @@ -15,7 +15,7 @@ top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs ## NEORV32 Configuration -:information_source: See the top entity [`rtl/templates/processor/neorv32_ProcessorTop_Test.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/templates/processor/neorv32_ProcessorTop_Test.vhd) for +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for configuration and entity details and [`nexys_a7_test_setup.xdc`](https://github.com/AWenzel83/neorv32/blob/nexys_a7_example/boards/nexys-a7-test-setup/nexys_a7_test_setup.xdc) for the according FPGA pin mapping. diff --git a/setups/vivado/nexys-a7-test-setup/create_project.tcl b/setups/vivado/nexys-a7-test-setup/create_project.tcl index 87c344133..c0b63f1d1 100644 --- a/setups/vivado/nexys-a7-test-setup/create_project.tcl +++ b/setups/vivado/nexys-a7-test-setup/create_project.tcl @@ -31,7 +31,7 @@ add_files [glob ./../../../rtl/core/*.vhd] set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]] # add source file: top entity -add_files [glob ./../../../rtl/templates/processor/neorv32_ProcessorTop_Test.vhd] +add_files [glob ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd] # add source files: simulation-only add_files -fileset sim_1 [list ./../../../sim/neorv32_tb.simple.vhd ./../../../sim/uart_rx.simple.vhd]