❌ MixedLanguage Implementation keeps failing

[stnolting]

The MixedLanguage setup (VHDL + Verilog) keeps failing. I do not think this is a code problem - there were no relevant code changes there. I think this might be a regression issue with GHDL?!

GHDL fails to import the neorv32_Fomu_MixedLanguage_ClkGen module:

3. Executing GHDL.
./board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd:87:3:warning: instance "clk_inst" of component "neorv32_fomu_mixedlanguage_clkgen" is not bound [-Wbinding]
  Clk_inst : neorv32_Fomu_MixedLanguage_ClkGen

Yosys then fails to handle that module:

ERROR: cell type 'neorv32_Fomu_MixedLanguage_ClkGen' is unsupported (instantiated as 'clk_inst')

[umarcor]

Yes. This is something I saw in fomu-workshop 1-2 weeks ago. It's happening with mixed language examples only. I will have a look at it in the upcoming week.