diff --git a/CHANGELOG.md b/CHANGELOG.md index 6ce0f0308..c22ba71a8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Link | |:----:|:-------:|:--------|:----:| +| 01.03.2024 | [**:rocket:1.9.6**](https://github.com/stnolting/neorv32/releases/tag/v1.9.6) | **New release** | | | 25.02.2024 | 1.9.5.10 | :bug: fix minor GPTMR threshold configuration issue | [#834](https://github.com/stnolting/neorv32/pull/834) | | 23.02.2024 | 1.9.5.9 | :bug: fix atomic write/clear/set accesses of clear-only CSR bits (re-fix of v1.9.5.6) | [#829](https://github.com/stnolting/neorv32/pull/829) | | 23.02.2024 | 1.9.5.8 | optimize FIFO component to improve technology mapping (inferring blockRAM for "async read" configuration); :bug: fix SLINK status flag delay | [#828](https://github.com/stnolting/neorv32/pull/828) | diff --git a/docs/attrs.adoc b/docs/attrs.adoc index 788d25143..03745dbf9 100644 --- a/docs/attrs.adoc +++ b/docs/attrs.adoc @@ -1,6 +1,6 @@ :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. -:revnumber: v1.9.5 +:revnumber: v1.9.6 :doctype: book :sectnums: :stem: diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index adc5f4c32..05288633e 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -53,7 +53,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090510"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090600"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index b6b31e9b2..2dbdaaa49 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.9.5 + 1.9.6 The NEORV32 RISC-V Processor