From b8d3e20d24050cf4239e8e7cc97fe71ce65130bc Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 2 May 2023 20:46:10 +0200 Subject: [PATCH 1/5] [rtl] update test_setup wrappers --- rtl/test_setups/neorv32_test_setup_approm.vhd | 2 ++ rtl/test_setups/neorv32_test_setup_bootloader.vhd | 2 ++ rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd | 2 ++ 3 files changed, 6 insertions(+) diff --git a/rtl/test_setups/neorv32_test_setup_approm.vhd b/rtl/test_setups/neorv32_test_setup_approm.vhd index 24f65abed..1458be571 100644 --- a/rtl/test_setups/neorv32_test_setup_approm.vhd +++ b/rtl/test_setups/neorv32_test_setup_approm.vhd @@ -72,6 +72,8 @@ begin CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + -- Tuning Options -- + CPU_IPB_ENTRIES => 2, -- entries in instruction prefetch buffer, has to be a power of 2, min 1 -- Internal Instruction memory -- MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes diff --git a/rtl/test_setups/neorv32_test_setup_bootloader.vhd b/rtl/test_setups/neorv32_test_setup_bootloader.vhd index 50d9abffe..358cd1d8e 100644 --- a/rtl/test_setups/neorv32_test_setup_bootloader.vhd +++ b/rtl/test_setups/neorv32_test_setup_bootloader.vhd @@ -75,6 +75,8 @@ begin CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + -- Tuning Options -- + CPU_IPB_ENTRIES => 2, -- entries in instruction prefetch buffer, has to be a power of 2, min 1 -- Internal Instruction memory -- MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes diff --git a/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd b/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd index 77b800ca1..11c7cf51f 100644 --- a/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd +++ b/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd @@ -84,6 +84,8 @@ begin CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.? (required for the on-chip debugger) + -- Tuning Options -- + CPU_IPB_ENTRIES => 2, -- entries in instruction prefetch buffer, has to be a power of 2, min 1 -- Internal Instruction memory -- MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes From 247f6603d6c47096955524e438bf610928124cae Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 2 May 2023 20:50:24 +0200 Subject: [PATCH 2/5] [CHANGELOG] add v1.8.4.6 --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 6ab67508e..a065f9c77 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -33,6 +33,7 @@ mimpid = 0x01080200 => Version 01.08.02.00 => v1.8.2 | Date (*dd.mm.yyyy*) | Version | Comment | |:-------------------:|:-------:|:--------| +| 02.05.2023 | 1.8.4.6 | make SDI FIFO access entirely synchronous; upgrade processor memory modules; update test setup wrappers; [#608]((https://github.com/stnolting/neorv32/pull/608) | | 30.04.2023 | 1.8.4.5 | rework processor-internal bus system; [#607](https://github.com/stnolting/neorv32/pull/607) | | 27.04.2023 | 1.8.4.4 | minor hardware edits and switching activity optimizations of CPU bus unit; [#605](https://github.com/stnolting/neorv32/pull/605) | | 25.04.2023 | 1.8.4.3 | :bug: fix bug in **DMA** (corrupted write-back when there are bus wait cycles - e.g. when no caches are implemented); [#601](https://github.com/stnolting/neorv32/pull/601) | From 74f49177046c38fe890efcfd067fe50aa2aa007b Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 2 May 2023 20:50:38 +0200 Subject: [PATCH 3/5] [rtl] update version --- rtl/core/neorv32_package.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 64010d3c2..1f0372bf9 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -60,7 +60,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080405"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080406"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width, do not change! From 381e778c76a73f9b7a1f5f7ed50464adcb6abeab Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 2 May 2023 20:51:20 +0200 Subject: [PATCH 4/5] [SDI] add *sync* FIFO read access --- rtl/core/neorv32_sdi.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/core/neorv32_sdi.vhd b/rtl/core/neorv32_sdi.vhd index 9779ec04e..c0c220eb7 100644 --- a/rtl/core/neorv32_sdi.vhd +++ b/rtl/core/neorv32_sdi.vhd @@ -224,7 +224,7 @@ begin generic map ( FIFO_DEPTH => RTX_FIFO, -- number of fifo entries; has to be a power of two; min 1 FIFO_WIDTH => 8, -- size of data elements in fifo (32-bit only for simulation) - FIFO_RSYNC => false, -- async read + FIFO_RSYNC => true, -- sync read FIFO_SAFE => true -- safe access ) port map ( @@ -256,7 +256,7 @@ begin generic map ( FIFO_DEPTH => RTX_FIFO, -- number of fifo entries; has to be a power of two; min 1 FIFO_WIDTH => 8, -- size of data elements in fifo (32-bit only for simulation) - FIFO_RSYNC => false, -- async read + FIFO_RSYNC => true, -- sync read FIFO_SAFE => true -- safe access ) port map ( From 16f35c4d611c28ed96d041a6c672bcad4a4d3a1c Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Tue, 2 May 2023 21:00:43 +0200 Subject: [PATCH 5/5] [rtl/core/mem] upgrade default memory modules Improve FPGA BRAM mapping --- rtl/core/mem/neorv32_dmem.default.vhd | 39 +++++++++++-------------- rtl/core/mem/neorv32_dmem.legacy.vhd | 25 ++++++++-------- rtl/core/mem/neorv32_imem.default.vhd | 41 +++++++++++---------------- rtl/core/mem/neorv32_imem.legacy.vhd | 27 +++++++++--------- 4 files changed, 58 insertions(+), 74 deletions(-) diff --git a/rtl/core/mem/neorv32_dmem.default.vhd b/rtl/core/mem/neorv32_dmem.default.vhd index d19dff252..604456eb9 100644 --- a/rtl/core/mem/neorv32_dmem.default.vhd +++ b/rtl/core/mem/neorv32_dmem.default.vhd @@ -54,6 +54,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is -- -------------------------------------------------------------------------------------------------------------- -- -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. -- -- -------------------------------------------------------------------------------------------------------------- -- -- RAM - not initialized at all -- @@ -88,30 +89,22 @@ begin mem_access: process(clk_i) begin if rising_edge(clk_i) then - -- this RAM style should not require "no_rw_check" attributes as the read-after-write behavior - -- is intended to be defined implicitly via the if-WRITE-else-READ construct - if (acc_en = '1') then -- reduce switching activity when not accessed - if (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 - mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); - else - mem_ram_b0_rd <= mem_ram_b0(to_integer(unsigned(addr))); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 - mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); - else - mem_ram_b1_rd <= mem_ram_b1(to_integer(unsigned(addr))); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 - mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); - else - mem_ram_b2_rd <= mem_ram_b2(to_integer(unsigned(addr))); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 - mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); - else - mem_ram_b3_rd <= mem_ram_b3(to_integer(unsigned(addr))); - end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); + end if; + mem_ram_b0_rd <= mem_ram_b0(to_integer(unsigned(addr))); + mem_ram_b1_rd <= mem_ram_b1(to_integer(unsigned(addr))); + mem_ram_b2_rd <= mem_ram_b2(to_integer(unsigned(addr))); + mem_ram_b3_rd <= mem_ram_b3(to_integer(unsigned(addr))); end if; end process mem_access; diff --git a/rtl/core/mem/neorv32_dmem.legacy.vhd b/rtl/core/mem/neorv32_dmem.legacy.vhd index 51ecc658d..990fbdbb9 100644 --- a/rtl/core/mem/neorv32_dmem.legacy.vhd +++ b/rtl/core/mem/neorv32_dmem.legacy.vhd @@ -55,6 +55,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is -- -------------------------------------------------------------------------------------------------------------- -- -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. -- -- -------------------------------------------------------------------------------------------------------------- -- -- RAM - not initialized at all -- @@ -90,19 +91,17 @@ begin begin if rising_edge(clk_i) then addr_ff <= addr; - if (acc_en = '1') then -- reduce switching activity when not accessed - if (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 - mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 - mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 - mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 - mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); - end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); end if; end if; end process mem_access; diff --git a/rtl/core/mem/neorv32_imem.default.vhd b/rtl/core/mem/neorv32_imem.default.vhd index be54c2619..4d35dec10 100644 --- a/rtl/core/mem/neorv32_imem.default.vhd +++ b/rtl/core/mem/neorv32_imem.default.vhd @@ -71,6 +71,7 @@ architecture neorv32_imem_rtl of neorv32_imem is -- -------------------------------------------------------------------------------------------------------------- -- -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. -- -- -------------------------------------------------------------------------------------------------------------- -- -- RAM - not initialized at all -- @@ -125,37 +126,29 @@ begin end generate; - -- Implement IMEM as not-initialized RAM -------------------------------------------------- + -- Implement IMEM as non-initialized RAM -------------------------------------------------- -- ------------------------------------------------------------------------------------------- imem_ram: if (IMEM_AS_IROM = false) generate mem_access: process(clk_i) begin if rising_edge(clk_i) then - -- this RAM style should not require "no_rw_check" attributes as the read-after-write behavior - -- is intended to be defined implicitly via the if-WRITE-else-READ construct - if (acc_en = '1') then -- reduce switching activity when not accessed - if (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 - mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); - else - mem_b0_rd <= mem_ram_b0(to_integer(unsigned(addr))); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 - mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); - else - mem_b1_rd <= mem_ram_b1(to_integer(unsigned(addr))); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 - mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); - else - mem_b2_rd <= mem_ram_b2(to_integer(unsigned(addr))); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 - mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); - else - mem_b3_rd <= mem_ram_b3(to_integer(unsigned(addr))); - end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); end if; + mem_b0_rd <= mem_ram_b0(to_integer(unsigned(addr))); + mem_b1_rd <= mem_ram_b1(to_integer(unsigned(addr))); + mem_b2_rd <= mem_ram_b2(to_integer(unsigned(addr))); + mem_b3_rd <= mem_ram_b3(to_integer(unsigned(addr))); end if; end process mem_access; -- read data -- diff --git a/rtl/core/mem/neorv32_imem.legacy.vhd b/rtl/core/mem/neorv32_imem.legacy.vhd index b09457df5..295977ebd 100644 --- a/rtl/core/mem/neorv32_imem.legacy.vhd +++ b/rtl/core/mem/neorv32_imem.legacy.vhd @@ -72,6 +72,7 @@ architecture neorv32_imem_rtl of neorv32_imem is -- -------------------------------------------------------------------------------------------------------------- -- -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. -- -- -------------------------------------------------------------------------------------------------------------- -- -- RAM - not initialized at all -- @@ -126,7 +127,7 @@ begin end generate; - -- Implement IMEM as not-initialized RAM -------------------------------------------------- + -- Implement IMEM as non-initialized RAM -------------------------------------------------- -- ------------------------------------------------------------------------------------------- imem_ram: if (IMEM_AS_IROM = false) generate @@ -134,19 +135,17 @@ begin begin if rising_edge(clk_i) then addr_ff <= addr; - if (acc_en = '1') then -- reduce switching activity when not accessed - if (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 - mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 - mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 - mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); - end if; - if (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 - mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); - end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16); + end if; + if (acc_en = '1') and (bus_req_i.we = '1') and (bus_req_i.ben(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24); end if; end if; end process mem_access;