From d04f154e6bbf94a41d01685954b0df7253fb6f53 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Tue, 21 May 2024 21:38:56 +0200
Subject: [PATCH] [sw/lib] update SLINK HAL

---
 sw/lib/include/neorv32_slink.h | 18 ++++++++++++++----
 sw/lib/source/neorv32_slink.c  | 25 +++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/sw/lib/include/neorv32_slink.h b/sw/lib/include/neorv32_slink.h
index 28c7fb53e..05ec99b8f 100644
--- a/sw/lib/include/neorv32_slink.h
+++ b/sw/lib/include/neorv32_slink.h
@@ -22,10 +22,10 @@
 /**@{*/
 /** SLINK module prototype */
 typedef volatile struct __attribute__((packed,aligned(4))) {
-  uint32_t CTRL;           /**< offset 0: control register (#NEORV32_SLINK_CTRL_enum) */
-  const uint32_t reserved; /**< offset 4: reserved */
-  uint32_t DATA;           /**< offset 8: RX/TX data register */
-  uint32_t DATA_LAST;      /**< offset 12: RX/TX data register (+ TX end-of-stream) */
+  uint32_t CTRL;      /**< offset 0: control register (#NEORV32_SLINK_CTRL_enum) */
+  uint32_t ROUTE;     /**< offset 4: routing information (#NEORV32_SLINK_ROUTE_enum) */
+  uint32_t DATA;      /**< offset 8: RX/TX data register */
+  uint32_t DATA_LAST; /**< offset 12: RX/TX data register (+ TX end-of-stream) */
 } neorv32_slink_t;
 
 /** SLINK module hardware access (#neorv32_slink_t) */
@@ -59,6 +59,14 @@ enum NEORV32_SLINK_CTRL_enum {
   SLINK_CTRL_TX_FIFO_MSB   = 31  /**< SLINK control register(31) (r/-): log2(TX FIFO size) MSB */
 };
 
+/** ROUTE register bits */
+enum NEORV32_SLINK_ROUTE_enum {
+  SLINK_ROUTE_DST_LSB = 0, /**< SLINK routing register(0) (r/w): Destination routing information LSB */
+  SLINK_ROUTE_DST_MSB = 3, /**< SLINK routing register(3) (r/w): Destination routing information MSB */ 
+  SLINK_ROUTE_SRC_LSB = 4, /**< SLINK routing register(4) (r/-): Source routing information LSB */
+  SLINK_ROUTE_SRC_MSB = 7  /**< SLINK routing register(7) (r/-): Source routing information MSB */ 
+};
+
 enum NEORV32_SLINK_STATUS_enum {
   SLINK_FIFO_EMPTY = 0, /**< FIFO is empty */
   SLINK_FIFO_HALF  = 1, /**< FIFO is at least half full */
@@ -79,6 +87,8 @@ int      neorv32_slink_get_rx_fifo_depth(void);
 int      neorv32_slink_get_tx_fifo_depth(void);
 uint32_t neorv32_slink_get(void);
 uint32_t neorv32_slink_check_last(void);
+void     neorv32_slink_set_dst(uint32_t dst);
+uint32_t neorv32_slink_get_src(void);
 void     neorv32_slink_put(uint32_t tx_data);
 void     neorv32_slink_put_last(uint32_t tx_data);
 int      neorv32_slink_rx_status(void);
diff --git a/sw/lib/source/neorv32_slink.c b/sw/lib/source/neorv32_slink.c
index 867e4bd91..49e1f92fb 100644
--- a/sw/lib/source/neorv32_slink.c
+++ b/sw/lib/source/neorv32_slink.c
@@ -127,6 +127,31 @@ inline uint32_t __attribute__((always_inline)) neorv32_slink_check_last(void) {
 }
 
 
+/**********************************************************************//**
+ * Set TX link routing destination
+ *
+ * @param[in] dst Routing destination ID (4-bit, LSB-aligned).
+ **************************************************************************/
+inline void __attribute__((always_inline)) neorv32_slink_set_dst(uint32_t dst) {
+
+  NEORV32_SLINK->ROUTE = dst;
+}
+
+
+/**********************************************************************//**
+ * Get RX link routing source
+ *
+ * @note This needs has to be called AFTER reading the actual data word
+ * using #neorv32_slink_get(void).
+ *
+ * @return 4-bit source routing ID.
+ **************************************************************************/
+inline uint32_t __attribute__((always_inline)) neorv32_slink_get_src(void) {
+
+  return (NEORV32_SLINK->ROUTE >> SLINK_ROUTE_SRC_LSB) & 0xF;
+}
+
+
 /**********************************************************************//**
  * Write data to TX link (non-blocking)
  *