From a9d28f3430cd32a49e0b856f17cb0704bed3f600 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Fri, 16 Feb 2024 05:54:37 +0100
Subject: [PATCH] =?UTF-8?q?=F0=9F=9A=80=20preparing=20release=20v1.9.5?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
CHANGELOG.md | 3 ++-
docs/attrs.adoc | 2 +-
rtl/core/neorv32_package.vhd | 2 +-
sw/svd/neorv32.svd | 2 +-
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 22be90b62..cf1c2c1e0 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -30,7 +30,8 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Link |
|:----:|:-------:|:--------|:----:|
-| 15.01.2023 | 1.9.4.13 | allow the DMA to issue a FENCE operation | [#807](https://github.com/stnolting/neorv32/pull/807) |
+| 16.02.2024 | [**:rocket:1.9.5**](https://github.com/stnolting/neorv32/releases/tag/v1.9.5) | **New release** | |
+| 15.02.2023 | 1.9.4.13 | allow the DMA to issue a FENCE operation | [#807](https://github.com/stnolting/neorv32/pull/807) |
| 14.02.2024 | 1.9.4.12 | :bug: close another illegal compressed instruction encoding loophole | [#806](https://github.com/stnolting/neorv32/pull/806) |
| 11.02.2024 | 1.9.4.11 | :bug: fix several FPU bugs and design flaws | [#794](https://github.com/stnolting/neorv32/pull/794) |
| 11.02.2024 | 1.9.4.10 | minor additions to previous version (1.9.4.9): fix HPM configuration read-back | [#804](https://github.com/stnolting/neorv32/pull/804) |
diff --git a/docs/attrs.adoc b/docs/attrs.adoc
index 9a122c457..788d25143 100644
--- a/docs/attrs.adoc
+++ b/docs/attrs.adoc
@@ -1,6 +1,6 @@
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.9.3
+:revnumber: v1.9.5
:doctype: book
:sectnums:
:stem:
diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
index 961963d62..8199b2376 100644
--- a/rtl/core/neorv32_package.vhd
+++ b/rtl/core/neorv32_package.vhd
@@ -53,7 +53,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
- constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090413"; -- hardware version
+ constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090500"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width
diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd
index 8260dd808..73b3933c6 100644
--- a/sw/svd/neorv32.svd
+++ b/sw/svd/neorv32.svd
@@ -4,7 +4,7 @@
stnolting
neorv32
RISC-V
- 1.9.4
+ 1.9.5
The NEORV32 RISC-V Processor