From a87d1df087c186664949eb378163c47d55b36417 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Nov 2023 07:45:53 +0100 Subject: [PATCH] [rtl] code cleanups --- rtl/core/neorv32_cpu.vhd | 34 +++++++++---------- rtl/core/neorv32_fifo.vhd | 71 +++++++++++++++++---------------------- 2 files changed, 47 insertions(+), 58 deletions(-) diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd index c7adcea52..b83c20e09 100644 --- a/rtl/core/neorv32_cpu.vhd +++ b/rtl/core/neorv32_cpu.vhd @@ -140,23 +140,23 @@ begin -- ------------------------------------------------------------------------------------------- -- CPU ISA configuration -- assert false report - "NEORV32 CPU Configuration: RV32" & - cond_sel_string_f(CPU_EXTENSION_RISCV_E, "E", "I") & - cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "" ) & - cond_sel_string_f(true, "_Zicsr", "" ) & -- always enabled - cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "" ) & - cond_sel_string_f(true, "_Zifencei", "" ) & -- always enabled - cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_Sdext", "" ) & - cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_Sdtrig", "" ) & - cond_sel_string_f(pmp_enable_c, "_Smpmp", "" ) + "NEORV32 CPU Configuration: rv32" & + cond_sel_string_f(CPU_EXTENSION_RISCV_E, "e", "i") & + cond_sel_string_f(CPU_EXTENSION_RISCV_M, "m", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_A, "a", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_C, "c", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_B, "b", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_U, "u", "" ) & + cond_sel_string_f(true, "_zicsr", "" ) & -- always enabled + cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_zicntr", "" ) & + cond_sel_string_f(true, "_zifencei", "" ) & -- always enabled + cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_zfinx", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_zihpm", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_zmmul", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_zxcfu", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_sdext", "" ) & + cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_sdtrig", "" ) & + cond_sel_string_f(pmp_enable_c, "_smpmp", "" ) severity note; -- simulation notifier -- diff --git a/rtl/core/neorv32_fifo.vhd b/rtl/core/neorv32_fifo.vhd index 908883b0e..d0a1f635b 100644 --- a/rtl/core/neorv32_fifo.vhd +++ b/rtl/core/neorv32_fifo.vhd @@ -76,7 +76,6 @@ architecture neorv32_fifo_rtl of neorv32_fifo is w_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- write pointer r_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- read pointer data : fifo_data_t; -- fifo memory - buf : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- if single-entry FIFO match : std_ulogic; empty : std_ulogic; full : std_ulogic; @@ -120,9 +119,6 @@ begin end if; end process pointer_update; - - -- FIFO Status ---------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- check_large: if (fifo_depth_c > 1) generate fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) else '0'; @@ -144,73 +140,52 @@ begin fifo.avail <= not fifo.empty; - -- Status Output -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - status_async: -- asynchronous - if (FIFO_RSYNC = false) generate - free_o <= fifo.free; - avail_o <= fifo.avail; - half_o <= fifo.half; - end generate; - - status_sync: -- synchronous - if (FIFO_RSYNC = true) generate - sync_status_flags: process(rstn_i, clk_i) - begin - if (rstn_i = '0') then - free_o <= '0'; - avail_o <= '0'; - half_o <= '0'; - elsif rising_edge(clk_i) then - free_o <= fifo.free; - avail_o <= fifo.avail; - half_o <= fifo.half; - end if; - end process sync_status_flags; - end generate; - - - -- FIFO Memory - Write -------------------------------------------------------------------- + -- FIFO Write ----------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- fifo_memory: -- real FIFO memory (several entries) if (fifo_depth_c > 1) generate sync_read: process(clk_i) begin - if rising_edge(clk_i) then + if rising_edge(clk_i) then -- no reset to infer block RAM if (fifo.we = '1') then fifo.data(to_integer(unsigned(fifo.w_pnt(fifo.w_pnt'left-1 downto 0)))) <= wdata_i; end if; end if; end process sync_read; - fifo.buf <= (others => '0'); -- unused end generate; fifo_buffer: -- simple register (single entry) if (fifo_depth_c = 1) generate - sync_read: process(clk_i) + sync_read: process(rstn_i, clk_i) begin - if rising_edge(clk_i) then + if (rstn_i = '0') then + fifo.data(0) <= (others => '0'); + elsif rising_edge(clk_i) then if (fifo.we = '1') then - fifo.buf <= wdata_i; + fifo.data(0) <= wdata_i; end if; end if; end process sync_read; - fifo.data <= (others => (others => '0')); -- unused end generate; - -- FIFO Memory - Read --------------------------------------------------------------------- + -- FIFO Read ------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------------- - fifo_read_async: -- "asynchronous" read + fifo_read_async: -- asynchronous read if (FIFO_RSYNC = false) generate async_read: process(fifo) begin if (fifo_depth_c = 1) then - rdata_o <= fifo.buf; + rdata_o <= fifo.data(0); else rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0)))); end if; end process async_read; + + -- status -- + free_o <= fifo.free; + avail_o <= fifo.avail; + half_o <= fifo.half; end generate; fifo_read_sync: -- synchronous read @@ -219,12 +194,26 @@ begin begin if rising_edge(clk_i) then if (fifo_depth_c = 1) then - rdata_o <= fifo.buf; + rdata_o <= fifo.data(0); else rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0)))); end if; end if; end process async_read; + + -- status -- + sync_status_flags: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + free_o <= '0'; + avail_o <= '0'; + half_o <= '0'; + elsif rising_edge(clk_i) then + free_o <= fifo.free; + avail_o <= fifo.avail; + half_o <= fifo.half; + end if; + end process sync_status_flags; end generate;