diff --git a/CHANGELOG.md b/CHANGELOG.md index f2a6bdbd7..5be51a823 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 21.06.2024 | 1.10.0.2 | minor code rtl clean-ups; fix some missing TOP defaults | [#929](https://github.com/stnolting/neorv32/pull/929) | | 17.05.2024 | 1.10.0.1 | :warning: remove (optional and redundant) JTAG reset signal `jtag_trst_i` | [#928](https://github.com/stnolting/neorv32/pull/928) | | 16.05.2024 | [**:rocket:1.10.0**](https://github.com/stnolting/neorv32/releases/tag/v1.10.0) | **New release** | | | 15.06.2024 | 1.9.9.9 | :sparkles: add pre-configured example project for Eclipse IDE | [#926](https://github.com/stnolting/neorv32/pull/926) | diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd index 41d0b2913..4f386da75 100644 --- a/rtl/core/neorv32_cpu_control.vhd +++ b/rtl/core/neorv32_cpu_control.vhd @@ -381,7 +381,7 @@ begin fetch_engine.resp <= bus_rsp_i.ack or bus_rsp_i.err; -- IPB instruction data and status -- - ipb.wdata(0) <= (bus_rsp_i.err or i_pmp_fault_i) & bus_rsp_i.data(15 downto 00); + ipb.wdata(0) <= (bus_rsp_i.err or i_pmp_fault_i) & bus_rsp_i.data(15 downto 0); ipb.wdata(1) <= (bus_rsp_i.err or i_pmp_fault_i) & bus_rsp_i.data(31 downto 16); -- IPB write enable -- @@ -526,29 +526,29 @@ begin elsif rising_edge(clk_i) then -- default I-immediate: ALU-immediate, load, jump-and-link with register -- imm_o(XLEN-1 downto 11) <= (others => execute_engine.ir(31)); -- sign extension - imm_o(10 downto 01) <= execute_engine.ir(30 downto 21); - imm_o(00) <= execute_engine.ir(20); + imm_o(10 downto 1) <= execute_engine.ir(30 downto 21); + imm_o(0) <= execute_engine.ir(20); -- case decode_aux.opcode is when opcode_store_c => -- S-immediate: store imm_o(XLEN-1 downto 11) <= (others => execute_engine.ir(31)); -- sign extension - imm_o(10 downto 05) <= execute_engine.ir(30 downto 25); - imm_o(04 downto 00) <= execute_engine.ir(11 downto 07); + imm_o(10 downto 5) <= execute_engine.ir(30 downto 25); + imm_o(4 downto 0) <= execute_engine.ir(11 downto 7); when opcode_branch_c => -- B-immediate: conditional branch imm_o(XLEN-1 downto 12) <= (others => execute_engine.ir(31)); -- sign extension - imm_o(11) <= execute_engine.ir(07); - imm_o(10 downto 05) <= execute_engine.ir(30 downto 25); - imm_o(04 downto 01) <= execute_engine.ir(11 downto 08); - imm_o(00) <= '0'; + imm_o(11) <= execute_engine.ir(7); + imm_o(10 downto 5) <= execute_engine.ir(30 downto 25); + imm_o(4 downto 1) <= execute_engine.ir(11 downto 8); + imm_o(0) <= '0'; when opcode_lui_c | opcode_auipc_c => -- U-immediate: lui, auipc imm_o(XLEN-1 downto 12) <= execute_engine.ir(31 downto 12); - imm_o(11 downto 00) <= (others => '0'); + imm_o(11 downto 0) <= (others => '0'); when opcode_jal_c => -- J-immediate: unconditional jump imm_o(XLEN-1 downto 20) <= (others => execute_engine.ir(31)); -- sign extension imm_o(19 downto 12) <= execute_engine.ir(19 downto 12); imm_o(11) <= execute_engine.ir(20); - imm_o(10 downto 01) <= execute_engine.ir(30 downto 21); - imm_o(00) <= '0'; + imm_o(10 downto 1) <= execute_engine.ir(30 downto 21); + imm_o(0) <= '0'; when opcode_amo_c => -- atomic memory access if CPU_EXTENSION_RISCV_A then imm_o <= (others => '0'); @@ -1059,7 +1059,7 @@ begin ctrl_o.alu_unsigned <= ctrl.alu_unsigned; ctrl_o.alu_cp_trig <= ctrl.alu_cp_trig; - -- data bus interface -- + -- load/store unit -- ctrl_o.lsu_req <= ctrl.lsu_req; ctrl_o.lsu_rw <= ctrl.lsu_rw; ctrl_o.lsu_mo_we <= '1' when (execute_engine.state = MEM_REQ) else '0'; -- write memory output registers (data & address) @@ -1654,8 +1654,8 @@ begin -- machine trap setup -- -- -------------------------------------------------------------------- when csr_mstatus_c => -- machine status register - csr.mstatus_mie <= csr.wdata(03); - csr.mstatus_mpie <= csr.wdata(07); + csr.mstatus_mie <= csr.wdata(3); + csr.mstatus_mpie <= csr.wdata(7); if CPU_EXTENSION_RISCV_U then csr.mstatus_mpp <= csr.wdata(11) or csr.wdata(12); -- everything /= U will fall back to M csr.mstatus_mprv <= csr.wdata(17); @@ -1663,8 +1663,8 @@ begin end if; when csr_mie_c => -- machine interrupt enable register - csr.mie_msi <= csr.wdata(03); - csr.mie_mti <= csr.wdata(07); + csr.mie_msi <= csr.wdata(3); + csr.mie_mti <= csr.wdata(7); csr.mie_mei <= csr.wdata(11); csr.mie_firq <= csr.wdata(31 downto 16); @@ -1907,8 +1907,8 @@ begin -- machine trap setup -- -- -------------------------------------------------------------------- when csr_mstatus_c => -- machine status register - low word - csr_rdata(03) <= csr.mstatus_mie; - csr_rdata(07) <= csr.mstatus_mpie; + csr_rdata(3) <= csr.mstatus_mie; + csr_rdata(7) <= csr.mstatus_mpie; csr_rdata(12 downto 11) <= (others => csr.mstatus_mpp); csr_rdata(17) <= csr.mstatus_mprv; csr_rdata(21) <= csr.mstatus_tw and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); @@ -1916,19 +1916,19 @@ begin -- when csr_mstatush_c => csr_rdata <= (others => '0'); -- machine status register - high word - hardwired to zero when csr_misa_c => -- ISA and extensions - csr_rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension - csr_rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension - csr_rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension - csr_rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension - csr_rdata(08) <= bool_to_ulogic_f(not CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) + csr_rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension + csr_rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension + csr_rdata(2) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension + csr_rdata(4) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension + csr_rdata(8) <= bool_to_ulogic_f(not CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) csr_rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension csr_rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension csr_rdata(23) <= '1'; -- X CPU extension (non-standard extensions / NEORV32-specific) csr_rdata(31 downto 30) <= "01"; -- MXL = 32 when csr_mie_c => -- machine interrupt-enable register - csr_rdata(03) <= csr.mie_msi; - csr_rdata(07) <= csr.mie_mti; + csr_rdata(3) <= csr.mie_msi; + csr_rdata(7) <= csr.mie_mti; csr_rdata(11) <= csr.mie_mei; csr_rdata(31 downto 16) <= csr.mie_firq; @@ -1969,8 +1969,8 @@ begin csr_rdata <= csr.mtval; when csr_mip_c => -- machine interrupt pending - csr_rdata(03) <= trap_ctrl.irq_pnd(irq_msi_irq_c); - csr_rdata(07) <= trap_ctrl.irq_pnd(irq_mti_irq_c); + csr_rdata(3) <= trap_ctrl.irq_pnd(irq_msi_irq_c); + csr_rdata(7) <= trap_ctrl.irq_pnd(irq_mti_irq_c); csr_rdata(11) <= trap_ctrl.irq_pnd(irq_mei_irq_c); csr_rdata(31 downto 16) <= trap_ctrl.irq_pnd(irq_firq_15_c downto irq_firq_0_c); @@ -1992,16 +1992,16 @@ begin end if; -- HPM event configuration -- - when csr_mhpmevent3_c => if (hpm_num_c > 00) then csr_rdata <= hpmevent_rd(03); end if; - when csr_mhpmevent4_c => if (hpm_num_c > 01) then csr_rdata <= hpmevent_rd(04); end if; - when csr_mhpmevent5_c => if (hpm_num_c > 02) then csr_rdata <= hpmevent_rd(05); end if; - when csr_mhpmevent6_c => if (hpm_num_c > 03) then csr_rdata <= hpmevent_rd(06); end if; - when csr_mhpmevent7_c => if (hpm_num_c > 04) then csr_rdata <= hpmevent_rd(07); end if; - when csr_mhpmevent8_c => if (hpm_num_c > 05) then csr_rdata <= hpmevent_rd(08); end if; - when csr_mhpmevent9_c => if (hpm_num_c > 06) then csr_rdata <= hpmevent_rd(09); end if; - when csr_mhpmevent10_c => if (hpm_num_c > 07) then csr_rdata <= hpmevent_rd(10); end if; - when csr_mhpmevent11_c => if (hpm_num_c > 08) then csr_rdata <= hpmevent_rd(11); end if; - when csr_mhpmevent12_c => if (hpm_num_c > 09) then csr_rdata <= hpmevent_rd(12); end if; + when csr_mhpmevent3_c => if (hpm_num_c > 0) then csr_rdata <= hpmevent_rd(3); end if; + when csr_mhpmevent4_c => if (hpm_num_c > 1) then csr_rdata <= hpmevent_rd(4); end if; + when csr_mhpmevent5_c => if (hpm_num_c > 2) then csr_rdata <= hpmevent_rd(5); end if; + when csr_mhpmevent6_c => if (hpm_num_c > 3) then csr_rdata <= hpmevent_rd(6); end if; + when csr_mhpmevent7_c => if (hpm_num_c > 4) then csr_rdata <= hpmevent_rd(7); end if; + when csr_mhpmevent8_c => if (hpm_num_c > 5) then csr_rdata <= hpmevent_rd(8); end if; + when csr_mhpmevent9_c => if (hpm_num_c > 6) then csr_rdata <= hpmevent_rd(9); end if; + when csr_mhpmevent10_c => if (hpm_num_c > 7) then csr_rdata <= hpmevent_rd(10); end if; + when csr_mhpmevent11_c => if (hpm_num_c > 8) then csr_rdata <= hpmevent_rd(11); end if; + when csr_mhpmevent12_c => if (hpm_num_c > 9) then csr_rdata <= hpmevent_rd(12); end if; when csr_mhpmevent13_c => if (hpm_num_c > 10) then csr_rdata <= hpmevent_rd(13); end if; when csr_mhpmevent14_c => if (hpm_num_c > 11) then csr_rdata <= hpmevent_rd(14); end if; when csr_mhpmevent15_c => if (hpm_num_c > 12) then csr_rdata <= hpmevent_rd(15); end if; @@ -2010,35 +2010,35 @@ begin -- counters and timers -- -- -------------------------------------------------------------------- -- low word -- - when csr_mcycle_c | csr_cycle_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_lo_rd(00); end if; - when csr_minstret_c | csr_instret_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_lo_rd(02); end if; - when csr_mhpmcounter3_c | csr_hpmcounter3_c => if (hpm_num_c > 00) then csr_rdata <= cnt_lo_rd(03); end if; - when csr_mhpmcounter4_c | csr_hpmcounter4_c => if (hpm_num_c > 01) then csr_rdata <= cnt_lo_rd(04); end if; - when csr_mhpmcounter5_c | csr_hpmcounter5_c => if (hpm_num_c > 02) then csr_rdata <= cnt_lo_rd(05); end if; - when csr_mhpmcounter6_c | csr_hpmcounter6_c => if (hpm_num_c > 03) then csr_rdata <= cnt_lo_rd(06); end if; - when csr_mhpmcounter7_c | csr_hpmcounter7_c => if (hpm_num_c > 04) then csr_rdata <= cnt_lo_rd(07); end if; - when csr_mhpmcounter8_c | csr_hpmcounter8_c => if (hpm_num_c > 05) then csr_rdata <= cnt_lo_rd(08); end if; - when csr_mhpmcounter9_c | csr_hpmcounter9_c => if (hpm_num_c > 06) then csr_rdata <= cnt_lo_rd(09); end if; - when csr_mhpmcounter10_c | csr_hpmcounter10_c => if (hpm_num_c > 07) then csr_rdata <= cnt_lo_rd(10); end if; - when csr_mhpmcounter11_c | csr_hpmcounter11_c => if (hpm_num_c > 08) then csr_rdata <= cnt_lo_rd(11); end if; - when csr_mhpmcounter12_c | csr_hpmcounter12_c => if (hpm_num_c > 09) then csr_rdata <= cnt_lo_rd(12); end if; + when csr_mcycle_c | csr_cycle_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_lo_rd(0); end if; + when csr_minstret_c | csr_instret_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_lo_rd(2); end if; + when csr_mhpmcounter3_c | csr_hpmcounter3_c => if (hpm_num_c > 0) then csr_rdata <= cnt_lo_rd(3); end if; + when csr_mhpmcounter4_c | csr_hpmcounter4_c => if (hpm_num_c > 1) then csr_rdata <= cnt_lo_rd(4); end if; + when csr_mhpmcounter5_c | csr_hpmcounter5_c => if (hpm_num_c > 2) then csr_rdata <= cnt_lo_rd(5); end if; + when csr_mhpmcounter6_c | csr_hpmcounter6_c => if (hpm_num_c > 3) then csr_rdata <= cnt_lo_rd(6); end if; + when csr_mhpmcounter7_c | csr_hpmcounter7_c => if (hpm_num_c > 4) then csr_rdata <= cnt_lo_rd(7); end if; + when csr_mhpmcounter8_c | csr_hpmcounter8_c => if (hpm_num_c > 5) then csr_rdata <= cnt_lo_rd(8); end if; + when csr_mhpmcounter9_c | csr_hpmcounter9_c => if (hpm_num_c > 6) then csr_rdata <= cnt_lo_rd(9); end if; + when csr_mhpmcounter10_c | csr_hpmcounter10_c => if (hpm_num_c > 7) then csr_rdata <= cnt_lo_rd(10); end if; + when csr_mhpmcounter11_c | csr_hpmcounter11_c => if (hpm_num_c > 8) then csr_rdata <= cnt_lo_rd(11); end if; + when csr_mhpmcounter12_c | csr_hpmcounter12_c => if (hpm_num_c > 9) then csr_rdata <= cnt_lo_rd(12); end if; when csr_mhpmcounter13_c | csr_hpmcounter13_c => if (hpm_num_c > 10) then csr_rdata <= cnt_lo_rd(13); end if; when csr_mhpmcounter14_c | csr_hpmcounter14_c => if (hpm_num_c > 11) then csr_rdata <= cnt_lo_rd(14); end if; when csr_mhpmcounter15_c | csr_hpmcounter15_c => if (hpm_num_c > 12) then csr_rdata <= cnt_lo_rd(15); end if; -- high word -- - when csr_mcycleh_c | csr_cycleh_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_hi_rd(00); end if; - when csr_minstreth_c | csr_instreth_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_hi_rd(02); end if; - when csr_mhpmcounter3h_c | csr_hpmcounter3h_c => if (hpm_num_c > 00) then csr_rdata <= cnt_hi_rd(03); end if; - when csr_mhpmcounter4h_c | csr_hpmcounter4h_c => if (hpm_num_c > 01) then csr_rdata <= cnt_hi_rd(04); end if; - when csr_mhpmcounter5h_c | csr_hpmcounter5h_c => if (hpm_num_c > 02) then csr_rdata <= cnt_hi_rd(05); end if; - when csr_mhpmcounter6h_c | csr_hpmcounter6h_c => if (hpm_num_c > 03) then csr_rdata <= cnt_hi_rd(06); end if; - when csr_mhpmcounter7h_c | csr_hpmcounter7h_c => if (hpm_num_c > 04) then csr_rdata <= cnt_hi_rd(07); end if; - when csr_mhpmcounter8h_c | csr_hpmcounter8h_c => if (hpm_num_c > 05) then csr_rdata <= cnt_hi_rd(08); end if; - when csr_mhpmcounter9h_c | csr_hpmcounter9h_c => if (hpm_num_c > 06) then csr_rdata <= cnt_hi_rd(09); end if; - when csr_mhpmcounter10h_c | csr_hpmcounter10h_c => if (hpm_num_c > 07) then csr_rdata <= cnt_hi_rd(10); end if; - when csr_mhpmcounter11h_c | csr_hpmcounter11h_c => if (hpm_num_c > 08) then csr_rdata <= cnt_hi_rd(11); end if; - when csr_mhpmcounter12h_c | csr_hpmcounter12h_c => if (hpm_num_c > 09) then csr_rdata <= cnt_hi_rd(12); end if; + when csr_mcycleh_c | csr_cycleh_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_hi_rd(0); end if; + when csr_minstreth_c | csr_instreth_c => if (CPU_EXTENSION_RISCV_Zicntr) then csr_rdata <= cnt_hi_rd(2); end if; + when csr_mhpmcounter3h_c | csr_hpmcounter3h_c => if (hpm_num_c > 0) then csr_rdata <= cnt_hi_rd(3); end if; + when csr_mhpmcounter4h_c | csr_hpmcounter4h_c => if (hpm_num_c > 1) then csr_rdata <= cnt_hi_rd(4); end if; + when csr_mhpmcounter5h_c | csr_hpmcounter5h_c => if (hpm_num_c > 2) then csr_rdata <= cnt_hi_rd(5); end if; + when csr_mhpmcounter6h_c | csr_hpmcounter6h_c => if (hpm_num_c > 3) then csr_rdata <= cnt_hi_rd(6); end if; + when csr_mhpmcounter7h_c | csr_hpmcounter7h_c => if (hpm_num_c > 4) then csr_rdata <= cnt_hi_rd(7); end if; + when csr_mhpmcounter8h_c | csr_hpmcounter8h_c => if (hpm_num_c > 5) then csr_rdata <= cnt_hi_rd(8); end if; + when csr_mhpmcounter9h_c | csr_hpmcounter9h_c => if (hpm_num_c > 6) then csr_rdata <= cnt_hi_rd(9); end if; + when csr_mhpmcounter10h_c | csr_hpmcounter10h_c => if (hpm_num_c > 7) then csr_rdata <= cnt_hi_rd(10); end if; + when csr_mhpmcounter11h_c | csr_hpmcounter11h_c => if (hpm_num_c > 8) then csr_rdata <= cnt_hi_rd(11); end if; + when csr_mhpmcounter12h_c | csr_hpmcounter12h_c => if (hpm_num_c > 9) then csr_rdata <= cnt_hi_rd(12); end if; when csr_mhpmcounter13h_c | csr_hpmcounter13h_c => if (hpm_num_c > 10) then csr_rdata <= cnt_hi_rd(13); end if; when csr_mhpmcounter14h_c | csr_hpmcounter14h_c => if (hpm_num_c > 11) then csr_rdata <= cnt_hi_rd(14); end if; when csr_mhpmcounter15h_c | csr_hpmcounter15h_c => if (hpm_num_c > 12) then csr_rdata <= cnt_hi_rd(15); end if; @@ -2077,16 +2077,16 @@ begin -- machine extended ISA extensions information -- when csr_mxisa_c => -- extended ISA (sub-)extensions -- - csr_rdata(00) <= '1'; -- Zicsr: CSR access (always enabled) - csr_rdata(01) <= '1'; -- Zifencei: instruction stream sync. (always enabled) - csr_rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div - csr_rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions - csr_rdata(04) <= '0'; -- reserved - csr_rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers - csr_rdata(06) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicond); -- Zicond: integer conditional operations - csr_rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base counters - csr_rdata(08) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Smpmp); -- Smpmp: physical memory protection - csr_rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors + csr_rdata(0) <= '1'; -- Zicsr: CSR access (always enabled) + csr_rdata(1) <= '1'; -- Zifencei: instruction stream sync. (always enabled) + csr_rdata(2) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div + csr_rdata(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions + csr_rdata(4) <= '0'; -- reserved + csr_rdata(5) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers + csr_rdata(6) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicond); -- Zicond: integer conditional operations + csr_rdata(7) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base counters + csr_rdata(8) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Smpmp); -- Smpmp: physical memory protection + csr_rdata(9) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors csr_rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdext); -- Sdext: RISC-V (external) debug mode csr_rdata(11) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdtrig); -- Sdtrig: trigger module -- misc -- @@ -2356,13 +2356,13 @@ begin csr.dcsr_rd(12) <= csr.dcsr_ebreaku when CPU_EXTENSION_RISCV_U else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter) csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping csr.dcsr_rd(10) <= '1'; -- stopcount: standard counters and HPMs are stopped when in debug mode - csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual - csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause - csr.dcsr_rd(05) <= '0'; -- reserved - csr.dcsr_rd(04) <= '1'; -- mprven: mstatus.mprv is also evaluated in debug mode - csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt - csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode - csr.dcsr_rd(01 downto 00) <= (others => csr.dcsr_prv); -- prv: privilege mode when debug mode was entered + csr.dcsr_rd(9) <= '0'; -- stoptime: timers increment as usual + csr.dcsr_rd(8 downto 6) <= csr.dcsr_cause; -- debug mode entry cause + csr.dcsr_rd(5) <= '0'; -- reserved + csr.dcsr_rd(4) <= '1'; -- mprven: mstatus.mprv is also evaluated in debug mode + csr.dcsr_rd(3) <= '0'; -- nmip: no pending non-maskable interrupt + csr.dcsr_rd(2) <= csr.dcsr_step; -- step: single-step mode + csr.dcsr_rd(1 downto 0) <= (others => csr.dcsr_prv); -- prv: privilege mode when debug mode was entered -- **************************************************************************************************************************** diff --git a/rtl/core/neorv32_cpu_cp_bitmanip.vhd b/rtl/core/neorv32_cpu_cp_bitmanip.vhd index 2e271cdc8..401caf206 100644 --- a/rtl/core/neorv32_cpu_cp_bitmanip.vhd +++ b/rtl/core/neorv32_cpu_cp_bitmanip.vhd @@ -337,7 +337,7 @@ begin -- sign-extension -- res_int(op_sext_c)(XLEN-1 downto 16) <= (others => rs1_reg(15)) when (ctrl_i.ir_funct12(0) = '1') else (others => rs1_reg(7)); res_int(op_sext_c)(15 downto 8) <= rs1_reg(15 downto 8) when (ctrl_i.ir_funct12(0) = '1') else (others => rs1_reg(7)); - res_int(op_sext_c)(07 downto 0) <= rs1_reg(07 downto 0); + res_int(op_sext_c)(7 downto 0) <= rs1_reg(7 downto 0); -- zero-extension -- res_int(op_zexth_c)(XLEN-1 downto 16) <= (others => '0'); diff --git a/rtl/core/neorv32_cpu_cp_fpu.vhd b/rtl/core/neorv32_cpu_cp_fpu.vhd index 1a58b1192..94fdc19bd 100644 --- a/rtl/core/neorv32_cpu_cp_fpu.vhd +++ b/rtl/core/neorv32_cpu_cp_fpu.vhd @@ -92,7 +92,7 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is sign_i : in std_ulogic; -- sign exponent_i : in std_ulogic_vector(7 downto 0); -- exponent mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa - class_i : in std_ulogic_vector(09 downto 0); -- operand class + class_i : in std_ulogic_vector(9 downto 0); -- operand class -- output -- result_o : out std_ulogic_vector(31 downto 0); -- integer result flags_o : out std_ulogic_vector(4 downto 0); -- exception flags @@ -154,7 +154,7 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is -- floating-point operands -- type op_data_t is array (0 to 1) of std_ulogic_vector(31 downto 0); - type op_class_t is array (0 to 1) of std_ulogic_vector(09 downto 0); + type op_class_t is array (0 to 1) of std_ulogic_vector(9 downto 0); type fpu_operands_t is record rs1 : std_ulogic_vector(31 downto 0); -- operand 1 rs1_class : std_ulogic_vector(9 downto 0); -- operand 1 number class @@ -339,11 +339,11 @@ begin -- rs1 -- op_data(0)(31) <= rs1_i(31); op_data(0)(30 downto 23) <= rs1_i(30 downto 23); - op_data(0)(22 downto 00) <= (others => '0') when (rs1_i(30 downto 23) = "00000000") else rs1_i(22 downto 0); -- flush mantissa to zero if subnormal + op_data(0)(22 downto 0) <= (others => '0') when (rs1_i(30 downto 23) = "00000000") else rs1_i(22 downto 0); -- flush mantissa to zero if subnormal -- rs2 -- op_data(1)(31) <= rs2_i(31); op_data(1)(30 downto 23) <= rs2_i(30 downto 23); - op_data(1)(22 downto 00) <= (others => '0') when (rs2_i(30 downto 23) = "00000000") else rs2_i(22 downto 0); -- flush mantissa to zero if subnormal + op_data(1)(22 downto 0) <= (others => '0') when (rs2_i(30 downto 23) = "00000000") else rs2_i(22 downto 0); -- flush mantissa to zero if subnormal -- O Classifier ---------------------------------------------------------------------- @@ -354,7 +354,7 @@ begin begin for i in 0 to 1 loop -- for rs1 and rs2 inputs -- check for all-zero/all-one -- - op_m_all_zero_v := not or_reduce_f(op_data(i)(22 downto 00)); + op_m_all_zero_v := not or_reduce_f(op_data(i)(22 downto 0)); op_e_all_zero_v := not or_reduce_f(op_data(i)(30 downto 23)); op_e_all_one_v := and_reduce_f(op_data(i)(30 downto 23)); @@ -475,7 +475,7 @@ begin -- ------------------------------------------------------------------------------------------- fu_classify.flags <= (others => '0'); -- does not generate flags at all fu_classify.result(31 downto 10) <= (others => '0'); - fu_classify.result(09 downto 00) <= fpu_operands.rs1_class; + fu_classify.result(9 downto 0) <= fpu_operands.rs1_class; fu_classify.done <= fu_classify.start; @@ -692,7 +692,7 @@ begin -- input -- sign_i => fpu_operands.rs1(31), -- sign exponent_i => fpu_operands.rs1(30 downto 23), -- exponent - mantissa_i => fpu_operands.rs1(22 downto 00), -- mantissa + mantissa_i => fpu_operands.rs1(22 downto 0), -- mantissa class_i => fpu_operands.rs1_class, -- operand class -- output -- result_o => fu_conv_f2i.result, -- integer result @@ -1233,8 +1233,8 @@ begin -- exponent check: find smaller number (magnitude-only) -- addsub.small_exp <= fpu_operands.rs1(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs2(30 downto 23); addsub.large_exp <= fpu_operands.rs2(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs1(30 downto 23); - addsub.small_man <= ('1' & fpu_operands.rs1(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs2(22 downto 00)); - addsub.large_man <= ('1' & fpu_operands.rs2(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs1(22 downto 00)); + addsub.small_man <= ('1' & fpu_operands.rs1(22 downto 0)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs2(22 downto 0)); + addsub.large_man <= ('1' & fpu_operands.rs2(22 downto 0)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs1(22 downto 0)); -- mantissa check: find smaller number (magnitude-only) -- addsub.man_s <= (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext) when (addsub.man_comp = '1') else (addsub.large_man & "000"); @@ -1425,8 +1425,8 @@ begin normalizer.xmantissa(47 downto 23) <= addsub.res_sum(27 downto 3); normalizer.xmantissa(22) <= addsub.res_sum(2); normalizer.xmantissa(21) <= addsub.res_sum(1); - normalizer.xmantissa(20 downto 01) <= (others => '0'); - normalizer.xmantissa(00) <= addsub.res_sum(0); + normalizer.xmantissa(20 downto 1) <= (others => '0'); + normalizer.xmantissa(0) <= addsub.res_sum(0); normalizer.class <= addsub.res_class; normalizer.flags_in <= addsub.flags; normalizer.start <= addsub.done; @@ -1559,18 +1559,18 @@ entity neorv32_cpu_cp_fpu_normalizer is rstn_i : in std_ulogic; -- global reset, low-active, async start_i : in std_ulogic; -- trigger operation abort_i : in std_ulogic; -- abort current operation - rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + rmode_i : in std_ulogic_vector(2 downto 0); -- rounding mode funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float) -- input -- sign_i : in std_ulogic; -- sign - exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent + exponent_i : in std_ulogic_vector(8 downto 0); -- extended exponent mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa integer_i : in std_ulogic_vector(31 downto 0); -- integer input - class_i : in std_ulogic_vector(09 downto 0); -- input number class - flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input + class_i : in std_ulogic_vector(9 downto 0); -- input number class + flags_i : in std_ulogic_vector(4 downto 0); -- exception flags input -- output -- result_o : out std_ulogic_vector(31 downto 0); -- float result - flags_o : out std_ulogic_vector(04 downto 0); -- exception flags output + flags_o : out std_ulogic_vector(4 downto 0); -- exception flags output done_o : out std_ulogic -- operation done ); end neorv32_cpu_cp_fpu_normalizer; @@ -1582,16 +1582,16 @@ architecture neorv32_cpu_cp_fpu_normalizer_rtl of neorv32_cpu_cp_fpu_normalizer type ctrl_t is record state : ctrl_engine_state_t; -- current state norm_r : std_ulogic; -- normalization round 0 or 1 - cnt : std_ulogic_vector(08 downto 0); -- interation counter/exponent (incl. overflow) - cnt_pre : std_ulogic_vector(08 downto 0); + cnt : std_ulogic_vector(8 downto 0); -- interation counter/exponent (incl. overflow) + cnt_pre : std_ulogic_vector(8 downto 0); cnt_of : std_ulogic; -- counter overflow cnt_uf : std_ulogic; -- counter underflow rounded : std_ulogic; -- output is rounded res_sgn : std_ulogic; - res_exp : std_ulogic_vector(07 downto 0); + res_exp : std_ulogic_vector(7 downto 0); res_man : std_ulogic_vector(22 downto 0); - class : std_ulogic_vector(09 downto 0); - flags : std_ulogic_vector(04 downto 0); + class : std_ulogic_vector(9 downto 0); + flags : std_ulogic_vector(4 downto 0); end record; signal ctrl : ctrl_t; @@ -1710,8 +1710,8 @@ begin when S_PREPARE_NORM => -- prepare "normal" normalization & rounding -- ------------------------------------------------------------ - sreg.upper(31 downto 02) <= (others => '0'); - sreg.upper(01 downto 00) <= mantissa_i(47 downto 46); + sreg.upper(31 downto 2) <= (others => '0'); + sreg.upper(1 downto 0) <= mantissa_i(47 downto 46); sreg.lower <= mantissa_i(45 downto 23); sreg.ext_g <= mantissa_i(22); sreg.ext_r <= mantissa_i(21); @@ -1782,10 +1782,10 @@ begin when S_ROUND => -- rounding cycle (after first normalization) -- ------------------------------------------------------------ ctrl.rounded <= ctrl.rounded or round.en; - sreg.upper(31 downto 02) <= (others => '0'); - sreg.upper(01 downto 00) <= round.output(24 downto 23); - sreg.lower <= round.output(22 downto 00); - -- If after the first shift we get a bit in any of the guard bitsthen independent of rounding mode + sreg.upper(31 downto 2) <= (others => '0'); + sreg.upper(1 downto 0) <= round.output(24 downto 23); + sreg.lower <= round.output(22 downto 0); + -- If after the first shift we get a bit in any of the guard bits then independent of rounding mode -- the end result will be inexact as we are truncating away information ctrl.flags(fp_exc_nx_c) <= sreg.ext_g or sreg.ext_r or sreg.ext_s; sreg.ext_g <= '0'; @@ -1828,33 +1828,33 @@ begin if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') then -- sNaN / qNaN ctrl.res_sgn <= fp_single_qnan_c(31); ctrl.res_exp <= fp_single_qnan_c(30 downto 23); - ctrl.res_man <= fp_single_qnan_c(22 downto 00); + ctrl.res_man <= fp_single_qnan_c(22 downto 0); elsif (ctrl.class(fp_class_neg_inf_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- infinity (ctrl.flags(fp_exc_of_c) = '1') then -- overflow -- if rounding mode is towards 0 we cannot generate an infinity instead we need to generate +MAX if ((rmode_i = "001") and (ctrl.flags(fp_exc_of_c) = '1')) then ctrl.res_exp <= fp_single_pos_max_c(30 downto 23); -- keep original sign - ctrl.res_man <= fp_single_pos_max_c(22 downto 00); + ctrl.res_man <= fp_single_pos_max_c(22 downto 0); -- if rounding mode is towards -inf we cannot generate a positive infinity instead we need to generate +MAX elsif ((rmode_i = "010") and (ctrl.flags(fp_exc_of_c) = '1') and (sign_i = '0')) then ctrl.res_exp <= fp_single_pos_max_c(30 downto 23); -- keep original sign - ctrl.res_man <= fp_single_pos_max_c(22 downto 00); + ctrl.res_man <= fp_single_pos_max_c(22 downto 0); -- if rounding mode is towards +inf we cannot generate a negative infinity instead we need to generate -MAX elsif ((rmode_i = "011") and (ctrl.flags(fp_exc_of_c) = '1') and (sign_i = '1')) then ctrl.res_exp <= fp_single_neg_max_c(30 downto 23); -- keep original sign - ctrl.res_man <= fp_single_neg_max_c(22 downto 00); + ctrl.res_man <= fp_single_neg_max_c(22 downto 0); else ctrl.res_exp <= fp_single_pos_inf_c(30 downto 23); -- keep original sign - ctrl.res_man <= fp_single_pos_inf_c(22 downto 00); + ctrl.res_man <= fp_single_pos_inf_c(22 downto 0); end if; elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') then -- zero ctrl.res_sgn <= ctrl.class(fp_class_neg_zero_c); ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23); - ctrl.res_man <= fp_single_pos_zero_c(22 downto 00); + ctrl.res_man <= fp_single_pos_zero_c(22 downto 0); elsif (ctrl.flags(fp_exc_uf_c) = '1') or -- underflow (sreg.zero = '1') or (ctrl.class(fp_class_neg_denorm_c) = '1') or (ctrl.class(fp_class_pos_denorm_c) = '1') then -- denormalized (flush-to-zero) ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23); -- keep original sign - ctrl.res_man <= fp_single_pos_zero_c(22 downto 00); + ctrl.res_man <= fp_single_pos_zero_c(22 downto 0); else -- result is fine as it is ctrl.res_exp <= ctrl.cnt(7 downto 0); ctrl.res_man <= sreg.lower; @@ -1888,7 +1888,7 @@ begin -- result -- result_o(31) <= ctrl.res_sgn; result_o(30 downto 23) <= ctrl.res_exp; - result_o(22 downto 0) <= ctrl.res_man; + result_o(22 downto 0) <= ctrl.res_man; -- exception flags -- flags_o(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c); -- invalid operation @@ -2003,16 +2003,16 @@ entity neorv32_cpu_cp_fpu_f2i is rstn_i : in std_ulogic; -- global reset, low-active, async start_i : in std_ulogic; -- trigger operation abort_i : in std_ulogic; -- abort current operation - rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + rmode_i : in std_ulogic_vector(2 downto 0); -- rounding mode funct_i : in std_ulogic; -- 0=signed, 1=unsigned -- input -- sign_i : in std_ulogic; -- sign - exponent_i : in std_ulogic_vector(07 downto 0); -- exponent + exponent_i : in std_ulogic_vector(7 downto 0); -- exponent mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa - class_i : in std_ulogic_vector(09 downto 0); -- operand class + class_i : in std_ulogic_vector(9 downto 0); -- operand class -- output -- result_o : out std_ulogic_vector(31 downto 0); -- integer result - flags_o : out std_ulogic_vector(04 downto 0); -- exception flags + flags_o : out std_ulogic_vector(4 downto 0); -- exception flags done_o : out std_ulogic -- operation done ); end neorv32_cpu_cp_fpu_f2i; @@ -2024,15 +2024,15 @@ architecture neorv32_cpu_cp_fpu_f2i_rtl of neorv32_cpu_cp_fpu_f2i is type ctrl_t is record state : ctrl_engine_state_t; -- current state unsign : std_ulogic; - cnt : std_ulogic_vector(07 downto 0); -- interation counter/exponent + cnt : std_ulogic_vector(7 downto 0); -- interation counter/exponent sign : std_ulogic; - class : std_ulogic_vector(09 downto 0); + class : std_ulogic_vector(9 downto 0); rounded : std_ulogic; -- output is rounded over : std_ulogic; -- output is overflowing under : std_ulogic; -- output in underflowing result_tmp : std_ulogic_vector(31 downto 0); result : std_ulogic_vector(31 downto 0); - flags : std_ulogic_vector(04 downto 0); -- we need to generate flags during the normalizing processes + flags : std_ulogic_vector(4 downto 0); -- we need to generate flags during the normalizing processes end record; signal ctrl : ctrl_t; diff --git a/rtl/core/neorv32_cpu_cp_muldiv.vhd b/rtl/core/neorv32_cpu_cp_muldiv.vhd index 32ad5d8b4..1c74f50fa 100644 --- a/rtl/core/neorv32_cpu_cp_muldiv.vhd +++ b/rtl/core/neorv32_cpu_cp_muldiv.vhd @@ -213,10 +213,10 @@ begin elsif rising_edge(clk_i) then if (mul.start = '1') then -- start new multiplication mul.prod(63 downto 32) <= (others => '0'); - mul.prod(31 downto 00) <= rs1_i; + mul.prod(31 downto 0) <= rs1_i; elsif (ctrl.state = S_BUSY) or (ctrl.state = S_DONE) then -- processing step or sign-finalization step mul.prod(63 downto 31) <= mul.add(32 downto 0); - mul.prod(30 downto 00) <= mul.prod(31 downto 1); + mul.prod(30 downto 0) <= mul.prod(31 downto 1); end if; end if; end process multiplier_core; @@ -290,8 +290,8 @@ begin -- no divider -- divider_core_serial_none: if not DIVISION_EN generate - div.remainder <= (others => '0'); div.quotient <= (others => '0'); + div.remainder <= (others => '0'); div.sub <= (others => '0'); div.res_u <= (others => '0'); div.res <= (others => '0'); @@ -306,7 +306,7 @@ begin if (ctrl.out_en = '1') then case ctrl_i.ir_funct3 is when op_mul_c => - res_o <= mul.prod(31 downto 00); + res_o <= mul.prod(31 downto 0); when op_mulh_c | op_mulhsu_c | op_mulhu_c => res_o <= mul.prod(63 downto 32); when others => -- op_div_c | op_rem_c | op_divu_c | op_remu_c diff --git a/rtl/core/neorv32_cpu_decompressor.vhd b/rtl/core/neorv32_cpu_decompressor.vhd index acce18622..1a606e43a 100644 --- a/rtl/core/neorv32_cpu_decompressor.vhd +++ b/rtl/core/neorv32_cpu_decompressor.vhd @@ -59,29 +59,29 @@ begin -- ------------------------------------------------------------------------------------------- -- 22-bit sign-extended immediate for J/JAL -- - imm20(00) <= '0'; - imm20(01) <= ci_instr16_i(3); - imm20(02) <= ci_instr16_i(4); - imm20(03) <= ci_instr16_i(5); - imm20(04) <= ci_instr16_i(11); - imm20(05) <= ci_instr16_i(2); - imm20(06) <= ci_instr16_i(7); - imm20(07) <= ci_instr16_i(6); - imm20(08) <= ci_instr16_i(9); - imm20(09) <= ci_instr16_i(10); + imm20(0) <= '0'; + imm20(1) <= ci_instr16_i(3); + imm20(2) <= ci_instr16_i(4); + imm20(3) <= ci_instr16_i(5); + imm20(4) <= ci_instr16_i(11); + imm20(5) <= ci_instr16_i(2); + imm20(6) <= ci_instr16_i(7); + imm20(7) <= ci_instr16_i(6); + imm20(8) <= ci_instr16_i(9); + imm20(9) <= ci_instr16_i(10); imm20(10) <= ci_instr16_i(8); imm20(20 downto 11) <= (others => ci_instr16_i(12)); -- sign extension -- 12-bit sign-extended immediate for branches -- - imm12(00) <= '0'; - imm12(01) <= ci_instr16_i(3); - imm12(02) <= ci_instr16_i(4); - imm12(03) <= ci_instr16_i(10); - imm12(04) <= ci_instr16_i(11); - imm12(05) <= ci_instr16_i(2); - imm12(06) <= ci_instr16_i(5); - imm12(07) <= ci_instr16_i(6); - imm12(12 downto 08) <= (others => ci_instr16_i(12)); -- sign extension + imm12(0) <= '0'; + imm12(1) <= ci_instr16_i(3); + imm12(2) <= ci_instr16_i(4); + imm12(3) <= ci_instr16_i(10); + imm12(4) <= ci_instr16_i(11); + imm12(5) <= ci_instr16_i(2); + imm12(6) <= ci_instr16_i(5); + imm12(7) <= ci_instr16_i(6); + imm12(12 downto 8) <= (others => ci_instr16_i(12)); -- sign extension -- Compressed Instruction Decoder --------------------------------------------------------- @@ -136,8 +136,8 @@ begin when "110" => -- C.SW -- ---------------------------------------------------------------------------------------------------------- decoded(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c; - decoded(08 downto 07) <= "00"; - decoded(09) <= ci_instr16_i(6); + decoded(8 downto 7) <= "00"; + decoded(9) <= ci_instr16_i(6); decoded(10) <= ci_instr16_i(10); decoded(11) <= ci_instr16_i(11); decoded(25) <= ci_instr16_i(12); @@ -166,7 +166,7 @@ begin decoded(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jal_c; decoded(19 downto 12) <= imm20(19 downto 12); decoded(20) <= imm20(11); - decoded(30 downto 21) <= imm20(10 downto 01); + decoded(30 downto 21) <= imm20(10 downto 1); decoded(31) <= imm20(20); when "110" | "111" => -- C.BEQ, C.BNEZ @@ -179,9 +179,9 @@ begin decoded(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_branch_c; decoded(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); decoded(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "00000"; -- x0 - decoded(07) <= imm12(11); - decoded(11 downto 08) <= imm12(04 downto 01); - decoded(30 downto 25) <= imm12(10 downto 05); + decoded(7) <= imm12(11); + decoded(11 downto 8) <= imm12(4 downto 1); + decoded(30 downto 25) <= imm12(10 downto 5); decoded(31) <= imm12(12); when "010" => -- C.LI @@ -342,8 +342,8 @@ begin when "110" | "111" => -- C.SWSP / C.FSWSP -- ---------------------------------------------------------------------------------------------------------- decoded(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c; - decoded(08 downto 07) <= "00"; - decoded(09) <= ci_instr16_i(9); + decoded(8 downto 7) <= "00"; + decoded(9) <= ci_instr16_i(9); decoded(10) <= ci_instr16_i(10); decoded(11) <= ci_instr16_i(11); decoded(25) <= ci_instr16_i(12); diff --git a/rtl/core/neorv32_cpu_lsu.vhd b/rtl/core/neorv32_cpu_lsu.vhd index c2faf5480..dc7ec6284 100644 --- a/rtl/core/neorv32_cpu_lsu.vhd +++ b/rtl/core/neorv32_cpu_lsu.vhd @@ -116,14 +116,14 @@ begin if (ctrl_i.lsu_mo_we = '1') then case ctrl_i.ir_funct3(1 downto 0) is when "00" => -- byte - bus_req_o.data(07 downto 00) <= wdata_i(7 downto 0); - bus_req_o.data(15 downto 08) <= wdata_i(7 downto 0); + bus_req_o.data(7 downto 0) <= wdata_i(7 downto 0); + bus_req_o.data(15 downto 8) <= wdata_i(7 downto 0); bus_req_o.data(23 downto 16) <= wdata_i(7 downto 0); bus_req_o.data(31 downto 24) <= wdata_i(7 downto 0); bus_req_o.ben <= (others => '0'); bus_req_o.ben(to_integer(unsigned(addr_i(1 downto 0)))) <= '1'; when "01" => -- half-word - bus_req_o.data(15 downto 00) <= wdata_i(15 downto 0); + bus_req_o.data(15 downto 0) <= wdata_i(15 downto 0); bus_req_o.data(31 downto 16) <= wdata_i(15 downto 0); if (addr_i(1) = '0') then bus_req_o.ben <= "0011"; -- low half-word @@ -151,25 +151,25 @@ begin when "00" => -- byte case mar(1 downto 0) is when "00" => -- byte 0 - rdata_o(7 downto 0) <= bus_rsp_i.data(07 downto 00); - rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(07))); -- sign-ext + rdata_o(7 downto 0) <= bus_rsp_i.data(7 downto 0); + rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(7))); -- sign-extend when "01" => -- byte 1 - rdata_o(7 downto 0) <= bus_rsp_i.data(15 downto 08); - rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(15))); -- sign-ext + rdata_o(7 downto 0) <= bus_rsp_i.data(15 downto 8); + rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(15))); -- sign-extend when "10" => -- byte 2 rdata_o(7 downto 0) <= bus_rsp_i.data(23 downto 16); - rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(23))); -- sign-ext + rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(23))); -- sign-extend when others => -- byte 3 rdata_o(7 downto 0) <= bus_rsp_i.data(31 downto 24); - rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(31))); -- sign-ext + rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(31))); -- sign-extend end case; when "01" => -- half-word if (mar(1) = '0') then -- low half-word - rdata_o(15 downto 0) <= bus_rsp_i.data(15 downto 00); - rdata_o(XLEN-1 downto 16) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(15))); -- sign-ext + rdata_o(15 downto 0) <= bus_rsp_i.data(15 downto 0); + rdata_o(XLEN-1 downto 16) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(15))); -- sign-extend else -- high half-word rdata_o(15 downto 0) <= bus_rsp_i.data(31 downto 16); - rdata_o(XLEN-1 downto 16) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(31))); -- sign-ext + rdata_o(XLEN-1 downto 16) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(31))); -- sign-extend end if; when others => -- word rdata_o(XLEN-1 downto 0) <= bus_rsp_i.data(XLEN-1 downto 0); @@ -202,10 +202,10 @@ begin wait_o <= not bus_rsp_i.ack; -- output access/alignment errors to control unit -- - ma_load_o <= arbiter_req and (not ctrl_i.lsu_rw) and misaligned; - be_load_o <= arbiter_req and (not ctrl_i.lsu_rw) and arbiter_err; - ma_store_o <= arbiter_req and ( ctrl_i.lsu_rw) and misaligned; - be_store_o <= arbiter_req and ( ctrl_i.lsu_rw) and arbiter_err; + ma_load_o <= arbiter_req and (not ctrl_i.lsu_rw) and misaligned; -- misaligned load + be_load_o <= arbiter_req and (not ctrl_i.lsu_rw) and arbiter_err; -- load bus error + ma_store_o <= arbiter_req and ( ctrl_i.lsu_rw) and misaligned; -- misaligned store + be_store_o <= arbiter_req and ( ctrl_i.lsu_rw) and arbiter_err; -- store bus error -- access request (all source signals are driven by registers) -- bus_req_o.stb <= ctrl_i.lsu_req and (not misaligned) and (not pmp_fault_i); diff --git a/rtl/core/neorv32_cpu_pmp.vhd b/rtl/core/neorv32_cpu_pmp.vhd index 2115dccd7..dcaf3b077 100644 --- a/rtl/core/neorv32_cpu_pmp.vhd +++ b/rtl/core/neorv32_cpu_pmp.vhd @@ -266,7 +266,7 @@ begin end if; end process addr_masking; - end generate; + end generate; -- /nap_mode_enable -- check region address match -- diff --git a/rtl/core/neorv32_cpu_regfile.vhd b/rtl/core/neorv32_cpu_regfile.vhd index 2af8154d6..57639849c 100644 --- a/rtl/core/neorv32_cpu_regfile.vhd +++ b/rtl/core/neorv32_cpu_regfile.vhd @@ -27,10 +27,10 @@ use neorv32.neorv32_package.all; entity neorv32_cpu_regfile is generic ( - RST_EN : boolean; -- enable dedicated hardware reset ("ASIC style") + RST_EN : boolean; -- implement dedicated hardware reset ("ASIC style") RVE_EN : boolean; -- implement embedded RF extension - RS3_EN : boolean; -- enable 3rd read port - RS4_EN : boolean -- enable 4th read port + RS3_EN : boolean; -- implement 3rd read port + RS4_EN : boolean -- implement 4th read port ); port ( -- global control -- @@ -71,8 +71,8 @@ begin -- Register zero (x0) is a "normal" physical register that is set to zero by the CPU control -- hardware. The register file uses synchronous read accesses and a *single* multiplexed - -- address port for writing and reading rd/rs1 and a single read-only port for rs2. Therefore, - -- the whole register file can be mapped to a single true-dual-port block RAM. + -- address port for writing and reading rd/rs1 and a single read-only port for reading rs2. + -- Therefore, the whole register file can be mapped to a single true-dual-port block RAM. rd_zero <= '1' when (ctrl_i.rf_rd = "00000") else '0'; rf_we <= (ctrl_i.rf_wb_en and (not rd_zero)) or ctrl_i.rf_zero_we; -- never write to x0 unless explicitly forced diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 80722d4b8..b78275c43 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100001"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100002"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index b3c8c006a..6df293126 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -991,6 +991,7 @@ begin xbus_rsp <= rsp_terminate_c; xbus_adr_o <= (others => '0'); xbus_dat_o <= (others => '0'); + xbus_tag_o <= (others => '0'); xbus_we_o <= '0'; xbus_sel_o <= (others => '0'); xbus_stb_o <= '0'; @@ -1398,6 +1399,7 @@ begin neorv32_trng_inst_false: if not IO_TRNG_EN generate iodev_rsp(IODEV_TRNG) <= rsp_terminate_c; + firq(FIRQ_TRNG) <= '0'; end generate;