diff --git a/CHANGELOG.md b/CHANGELOG.md
index 6da21f9d4..8bb79c50b 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
+| 04.07.2024 | [**:rocket:1.10.1**](https://github.com/stnolting/neorv32/releases/tag/v1.10.1) | **New release** | |
| 04.07.2024 | 1.10.0.10 | :warning: rework GPTMRM and remove capture mode | [#939](https://github.com/stnolting/neorv32/pull/939) |
| 03.07.2024 | 1.10.0.9 | :warning: remove `AMO_RVS_GRANULARITY` generic, reservation set granularity is now fixed to 4 bytes | [#938](https://github.com/stnolting/neorv32/pull/938) |
| 03.07.2024 | 1.10.0.8 | :test_tube: add XBUS to AHB3-lite bridge | [#937](https://github.com/stnolting/neorv32/pull/937) |
diff --git a/docs/attrs.adoc b/docs/attrs.adoc
index 8397e9024..9e154a03a 100644
--- a/docs/attrs.adoc
+++ b/docs/attrs.adoc
@@ -1,6 +1,6 @@
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.10.0
+:revnumber: v1.10.1
:doctype: book
:sectnums:
:stem:
diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
index c67b3f84a..377654684 100644
--- a/rtl/core/neorv32_package.vhd
+++ b/rtl/core/neorv32_package.vhd
@@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
- constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100010"; -- hardware version
+ constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100100"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width
diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd
index 16e5ea1c0..cf61934fc 100644
--- a/sw/svd/neorv32.svd
+++ b/sw/svd/neorv32.svd
@@ -4,7 +4,7 @@
stnolting
neorv32
RISC-V
- 1.10.0
+ 1.10.1
The NEORV32 RISC-V Processor