From 6269bd2fcdd695f94afef7b0e4af61af45b68da1 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Wed, 31 Jan 2024 20:46:03 +0100 Subject: [PATCH] =?UTF-8?q?=F0=9F=9A=80=20preparing=20release=20v1.9.4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- CHANGELOG.md | 1 + rtl/core/neorv32_package.vhd | 2 +- sw/svd/neorv32.svd | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index a8256947b..de3f7befb 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Link | |:----:|:-------:|:--------|:----:| +| 31.01.2024 | [**:rocket:1.9.4**](https://github.com/stnolting/neorv32/releases/tag/v1.9.4) | **New release** | | | 31.01.2024 | 1.9.3.10 | close illegal compressed instruction decoding loophole | [#783](https://github.com/stnolting/neorv32/pull/783) | | 29.01.2024 | 1.9.3.9 | :test_tube: extend switchable clock domain (CPU bus switch, i-cache, d-cache) | [#780](https://github.com/stnolting/neorv32/pull/780) | | 29.01.2024 | 1.9.3.8 | top entity input ports now have default values `'L'` or `'h'` modeling a pull-down or pull-resistor in case they are not explicitly assigned during instantiation | [#779](https://github.com/stnolting/neorv32/pull/779) | diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 482aae635..1ff758b11 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -56,7 +56,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090310"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090400"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index 46e8f6547..2376195cf 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.9.3 + 1.9.4 The NEORV32 RISC-V Processor