diff --git a/CHANGELOG.md b/CHANGELOG.md index d0851702e..73daa929f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 02.07.2024 | 1.10.0.7 | minor rtl and software edits and cleanups | [#936](https://github.com/stnolting/neorv32/pull/936) | | 30.06.2024 | 1.10.0.6 | minor rtl edits and cleanups | [#935](https://github.com/stnolting/neorv32/pull/935) | | 29.06.2024 | 1.10.0.5 | :warning: rework and optimize custom functions unit (CFU) interface; simplified illegal RVC decoding | [#932](https://github.com/stnolting/neorv32/pull/932) | | 23.06.2024 | 1.10.0.4 | minor rtl edits/cleanups | [#931](https://github.com/stnolting/neorv32/pull/931) | diff --git a/docs/datasheet/software.adoc b/docs/datasheet/software.adoc index 592a96e85..31580845f 100644 --- a/docs/datasheet/software.adoc +++ b/docs/datasheet/software.adoc @@ -94,7 +94,8 @@ The NEORV32 project provides a set of pre-defined C libraries that allow an easy | `neorv32_dma.c` | `neorv32_dma.h` | <<_direct_memory_access_controller_dma>> HAL | `neorv32_gpio.c` | `neorv32_gpio.h` | <<_general_purpose_input_and_output_port_gpio>> HAL | `neorv32_gptmr.c` | `neorv32_gptmr.h` | <<_general_purpose_timer_gptmr>> HAL -| - | `neorv32_intrinsics.h` | Macros for intrinsics & custom instructions +| - | `neorv32_intrinsics.h` | Macros for intrinsics and custom instructions +| - | `neorv32_legacy.h` | Legacy compatibility layer / wrappers (**do not use for new designs!**) | `neorv32_mtime.c` | `neorv32_mtime.h` | <<_machine_system_timer_mtime>> HAL | `neorv32_neoled.c` | `neorv32_neoled.h` | <<_smart_led_interface_neoled>> HAL | `neorv32_onewire.c` | `neorv32_onewire.h` | <<_one_wire_serial_interface_controller_onewire>> HAL diff --git a/rtl/core/neorv32_cpu_cp_cfu.vhd b/rtl/core/neorv32_cpu_cp_cfu.vhd index 7838d8e7e..dcb2e7732 100644 --- a/rtl/core/neorv32_cpu_cp_cfu.vhd +++ b/rtl/core/neorv32_cpu_cp_cfu.vhd @@ -111,9 +111,6 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library neorv32; -use neorv32.neorv32_package.all; - entity neorv32_cpu_cp_cfu is port ( -- global control -- @@ -251,12 +248,7 @@ begin -- ------------------------------------------------------------------------------------------- result_select: process(rtype_i, funct3_i, xtea) begin - -- defaults -- - result_o <= (others => '0'); - valid_o <= '0'; - - -- check instruction type -- - case rtype_i is + case rtype_i is -- check instruction type when r3type_c => -- R3-type instructions; function select via "funct3" and ""funct7 -- ---------------------------------------------------------------------- diff --git a/rtl/core/neorv32_intercon.vhd b/rtl/core/neorv32_intercon.vhd index 7e972987b..7072308a0 100644 --- a/rtl/core/neorv32_intercon.vhd +++ b/rtl/core/neorv32_intercon.vhd @@ -396,7 +396,18 @@ entity neorv32_bus_io_switch is DEV_17_EN : boolean; DEV_17_BASE : std_ulogic_vector(31 downto 0); DEV_18_EN : boolean; DEV_18_BASE : std_ulogic_vector(31 downto 0); DEV_19_EN : boolean; DEV_19_BASE : std_ulogic_vector(31 downto 0); - DEV_20_EN : boolean; DEV_20_BASE : std_ulogic_vector(31 downto 0) + DEV_20_EN : boolean; DEV_20_BASE : std_ulogic_vector(31 downto 0); + DEV_21_EN : boolean; DEV_21_BASE : std_ulogic_vector(31 downto 0); + DEV_22_EN : boolean; DEV_22_BASE : std_ulogic_vector(31 downto 0); + DEV_23_EN : boolean; DEV_23_BASE : std_ulogic_vector(31 downto 0); + DEV_24_EN : boolean; DEV_24_BASE : std_ulogic_vector(31 downto 0); + DEV_25_EN : boolean; DEV_25_BASE : std_ulogic_vector(31 downto 0); + DEV_26_EN : boolean; DEV_26_BASE : std_ulogic_vector(31 downto 0); + DEV_27_EN : boolean; DEV_27_BASE : std_ulogic_vector(31 downto 0); + DEV_28_EN : boolean; DEV_28_BASE : std_ulogic_vector(31 downto 0); + DEV_29_EN : boolean; DEV_29_BASE : std_ulogic_vector(31 downto 0); + DEV_30_EN : boolean; DEV_30_BASE : std_ulogic_vector(31 downto 0); + DEV_31_EN : boolean; DEV_31_BASE : std_ulogic_vector(31 downto 0) ); port ( -- host port -- @@ -423,56 +434,51 @@ entity neorv32_bus_io_switch is dev_17_req_o : out bus_req_t; dev_17_rsp_i : in bus_rsp_t; dev_18_req_o : out bus_req_t; dev_18_rsp_i : in bus_rsp_t; dev_19_req_o : out bus_req_t; dev_19_rsp_i : in bus_rsp_t; - dev_20_req_o : out bus_req_t; dev_20_rsp_i : in bus_rsp_t + dev_20_req_o : out bus_req_t; dev_20_rsp_i : in bus_rsp_t; + dev_21_req_o : out bus_req_t; dev_21_rsp_i : in bus_rsp_t; + dev_22_req_o : out bus_req_t; dev_22_rsp_i : in bus_rsp_t; + dev_23_req_o : out bus_req_t; dev_23_rsp_i : in bus_rsp_t; + dev_24_req_o : out bus_req_t; dev_24_rsp_i : in bus_rsp_t; + dev_25_req_o : out bus_req_t; dev_25_rsp_i : in bus_rsp_t; + dev_26_req_o : out bus_req_t; dev_26_rsp_i : in bus_rsp_t; + dev_27_req_o : out bus_req_t; dev_27_rsp_i : in bus_rsp_t; + dev_28_req_o : out bus_req_t; dev_28_rsp_i : in bus_rsp_t; + dev_29_req_o : out bus_req_t; dev_29_rsp_i : in bus_rsp_t; + dev_30_req_o : out bus_req_t; dev_30_rsp_i : in bus_rsp_t; + dev_31_req_o : out bus_req_t; dev_31_rsp_i : in bus_rsp_t ); end neorv32_bus_io_switch; architecture neorv32_bus_io_switch_rtl of neorv32_bus_io_switch is - -- ------------------------------------------------------------------------------------------- -- - -- How to add another device port -- - -- ------------------------------------------------------------------------------------------- -- - -- 1. Increment (must not exceed ). -- - -- 2. Append another pair of "DEV_xx_EN" and "DEV_xx_BASE" generics. -- - -- 3. Append these two generics to the according and arrays. -- - -- 4. Append another pair of "dev_xx_req_o" and "dev_xx_rsp_i" ports. -- - -- 5. Append these two ports to the according and array assignments in -- - -- the "Combine Device Ports" section. -- - -- ------------------------------------------------------------------------------------------- -- - -- module configuration -- - constant num_devs_physical_c : natural := 21; -- actual number of devices, max num_devs_logical_c - constant num_devs_logical_c : natural := 32; -- logical max number of devices; do not change! + constant num_devs_c : natural := 32; -- number of device ports -- address bits for access decoding -- constant abb_lo_c : natural := index_size_f(DEV_SIZE); -- low address boundary bit - constant abb_hi_c : natural := (index_size_f(DEV_SIZE) + index_size_f(num_devs_logical_c)) - 1; -- high address boundary bit + constant abb_hi_c : natural := (index_size_f(DEV_SIZE) + index_size_f(num_devs_c)) - 1; -- high address boundary bit -- list of enabled device ports -- - type dev_en_list_t is array (0 to num_devs_physical_c-1) of boolean; + type dev_en_list_t is array (0 to num_devs_c-1) of boolean; constant dev_en_list_c : dev_en_list_t := ( - DEV_00_EN, DEV_01_EN, DEV_02_EN, DEV_03_EN, - DEV_04_EN, DEV_05_EN, DEV_06_EN, DEV_07_EN, - DEV_08_EN, DEV_09_EN, DEV_10_EN, DEV_11_EN, - DEV_12_EN, DEV_13_EN, DEV_14_EN, DEV_15_EN, - DEV_16_EN, DEV_17_EN, DEV_18_EN, DEV_19_EN, - DEV_20_EN + DEV_00_EN, DEV_01_EN, DEV_02_EN, DEV_03_EN, DEV_04_EN, DEV_05_EN, DEV_06_EN, DEV_07_EN, + DEV_08_EN, DEV_09_EN, DEV_10_EN, DEV_11_EN, DEV_12_EN, DEV_13_EN, DEV_14_EN, DEV_15_EN, + DEV_16_EN, DEV_17_EN, DEV_18_EN, DEV_19_EN, DEV_20_EN, DEV_21_EN, DEV_22_EN, DEV_23_EN, + DEV_24_EN, DEV_25_EN, DEV_26_EN, DEV_27_EN, DEV_28_EN, DEV_29_EN, DEV_30_EN, DEV_31_EN ); -- list of device base addresses -- - type dev_base_list_t is array (0 to num_devs_physical_c-1) of std_ulogic_vector(31 downto 0); + type dev_base_list_t is array (0 to num_devs_c-1) of std_ulogic_vector(31 downto 0); constant dev_base_list_c : dev_base_list_t := ( - DEV_00_BASE, DEV_01_BASE, DEV_02_BASE, DEV_03_BASE, - DEV_04_BASE, DEV_05_BASE, DEV_06_BASE, DEV_07_BASE, - DEV_08_BASE, DEV_09_BASE, DEV_10_BASE, DEV_11_BASE, - DEV_12_BASE, DEV_13_BASE, DEV_14_BASE, DEV_15_BASE, - DEV_16_BASE, DEV_17_BASE, DEV_18_BASE, DEV_19_BASE, - DEV_20_BASE + DEV_00_BASE, DEV_01_BASE, DEV_02_BASE, DEV_03_BASE, DEV_04_BASE, DEV_05_BASE, DEV_06_BASE, DEV_07_BASE, + DEV_08_BASE, DEV_09_BASE, DEV_10_BASE, DEV_11_BASE, DEV_12_BASE, DEV_13_BASE, DEV_14_BASE, DEV_15_BASE, + DEV_16_BASE, DEV_17_BASE, DEV_18_BASE, DEV_19_BASE, DEV_20_BASE, DEV_21_BASE, DEV_22_BASE, DEV_23_BASE, + DEV_24_BASE, DEV_25_BASE, DEV_26_BASE, DEV_27_BASE, DEV_28_BASE, DEV_29_BASE, DEV_30_BASE, DEV_31_BASE ); -- device ports combined as arrays -- - type dev_req_t is array (0 to num_devs_physical_c-1) of bus_req_t; - type dev_rsp_t is array (0 to num_devs_physical_c-1) of bus_rsp_t; + type dev_req_t is array (0 to num_devs_c-1) of bus_req_t; + type dev_rsp_t is array (0 to num_devs_c-1) of bus_rsp_t; signal dev_req : dev_req_t; signal dev_rsp : dev_rsp_t; @@ -501,12 +507,23 @@ begin dev_18_req_o <= dev_req(18); dev_rsp(18) <= dev_18_rsp_i; dev_19_req_o <= dev_req(19); dev_rsp(19) <= dev_19_rsp_i; dev_20_req_o <= dev_req(20); dev_rsp(20) <= dev_20_rsp_i; + dev_21_req_o <= dev_req(21); dev_rsp(21) <= dev_21_rsp_i; + dev_22_req_o <= dev_req(22); dev_rsp(22) <= dev_22_rsp_i; + dev_23_req_o <= dev_req(23); dev_rsp(23) <= dev_23_rsp_i; + dev_24_req_o <= dev_req(24); dev_rsp(24) <= dev_24_rsp_i; + dev_25_req_o <= dev_req(25); dev_rsp(25) <= dev_25_rsp_i; + dev_26_req_o <= dev_req(26); dev_rsp(26) <= dev_26_rsp_i; + dev_27_req_o <= dev_req(27); dev_rsp(27) <= dev_27_rsp_i; + dev_28_req_o <= dev_req(28); dev_rsp(28) <= dev_28_rsp_i; + dev_29_req_o <= dev_req(29); dev_rsp(29) <= dev_29_rsp_i; + dev_30_req_o <= dev_req(30); dev_rsp(30) <= dev_30_rsp_i; + dev_31_req_o <= dev_req(31); dev_rsp(31) <= dev_31_rsp_i; -- Request -------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- bus_request_gen: - for i in 0 to (num_devs_physical_c-1) generate + for i in 0 to (num_devs_c-1) generate bus_request_port_enabled: if dev_en_list_c(i) generate @@ -514,7 +531,7 @@ begin begin dev_req(i) <= main_req_i; if (main_req_i.addr(abb_hi_c downto abb_lo_c) = dev_base_list_c(i)(abb_hi_c downto abb_lo_c)) then - dev_req(i).stb <= main_req_i.stb; + dev_req(i).stb <= main_req_i.stb; -- propagate transaction strobe if address match else dev_req(i).stb <= '0'; end if; @@ -526,7 +543,7 @@ begin dev_req(i) <= req_terminate_c; end generate; - end generate; -- /bus_request_gen + end generate; -- Response ------------------------------------------------------------------------------- @@ -535,7 +552,7 @@ begin variable tmp_v : bus_rsp_t; begin tmp_v := rsp_terminate_c; -- start with all-zero - for i in 0 to (num_devs_physical_c-1) loop -- logical OR all response signals + for i in 0 to (num_devs_c-1) loop -- OR all enabled response buses if dev_en_list_c(i) then tmp_v.data := tmp_v.data or dev_rsp(i).data; tmp_v.ack := tmp_v.ack or dev_rsp(i).ack; diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index dbe9e2b75..c99b08a6f 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100006"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100007"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width @@ -700,6 +700,7 @@ package neorv32_package is function popcount_f(input : std_ulogic_vector) return natural; function leading_zeros_f(input : std_ulogic_vector) return natural; impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t; + function print_version_f(version : std_ulogic_vector(31 downto 0)) return string; -- ********************************************************************************************************** -- NEORV32 Processor Top Entity (component prototype) @@ -1171,6 +1172,34 @@ package body neorv32_package is return mem_v; end function mem32_init_f; + -- Print hardware version in human-readable format (xx.xx.xx.xx) -------------------------- + -- ------------------------------------------------------------------------------------------- + function print_version_f(version : std_ulogic_vector(31 downto 0)) return string is + variable res_v : string(1 to 11); + variable idx_v : natural; + begin + idx_v := 1; + if (version(31 downto 28) /= x"0") then -- print only if not trailing zero + res_v(idx_v) := to_hexchar_f(version(31 downto 28)); idx_v := idx_v + 1; + end if; + res_v(idx_v) := to_hexchar_f(version(27 downto 24)); idx_v := idx_v + 1; + res_v(idx_v) := '.'; idx_v := idx_v + 1; + if (version(23 downto 20) /= x"0") then -- print only if not trailing zero + res_v(idx_v) := to_hexchar_f(version(23 downto 20)); idx_v := idx_v + 1; + end if; + res_v(idx_v) := to_hexchar_f(version(19 downto 16)); idx_v := idx_v + 1; + res_v(idx_v) := '.'; idx_v := idx_v + 1; + if (version(15 downto 12) /= x"0") then -- print only if not trailing zero + res_v(idx_v) := to_hexchar_f(version(15 downto 12)); idx_v := idx_v + 1; + end if; + res_v(idx_v) := to_hexchar_f(version(11 downto 8)); idx_v := idx_v + 1; + res_v(idx_v) := '.'; idx_v := idx_v + 1; + if (version(7 downto 4) /= x"0") then -- print only if not trailing zero + res_v(idx_v) := to_hexchar_f(version(7 downto 4)); idx_v := idx_v + 1; + end if; + res_v(idx_v) := to_hexchar_f(version(3 downto 0)); idx_v := idx_v + 1; + return res_v; + end function print_version_f; end neorv32_package; diff --git a/rtl/core/neorv32_sysinfo.vhd b/rtl/core/neorv32_sysinfo.vhd index 1010ce5c9..663c8adb2 100644 --- a/rtl/core/neorv32_sysinfo.vhd +++ b/rtl/core/neorv32_sysinfo.vhd @@ -1,5 +1,5 @@ -- ================================================================================ -- --- NEORV32 SoC - System/Processor Configuration Information Memory (SYSINFO) -- +-- NEORV32 SoC - System Configuration Information Memory (SYSINFO) -- -- -------------------------------------------------------------------------------- -- -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 -- -- Copyright (c) NEORV32 contributors. -- @@ -87,26 +87,26 @@ begin sysinfo(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); -- SYSINFO(1): Internal Memory Configuration (sizes) - sysinfo(1)(07 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size) - sysinfo(1)(15 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size) + sysinfo(1)(7 downto 0) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size) + sysinfo(1)(15 downto 8) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size) sysinfo(1)(23 downto 16) <= (others => '0'); -- reserved sysinfo(1)(31 downto 24) <= std_ulogic_vector(to_unsigned(index_size_f(AMO_RVS_GRANULARITY), 8)); -- log2(reservation set granularity) -- SYSINFO(2): SoC Configuration -- - sysinfo(2)(00) <= '1' when INT_BOOTLOADER_EN else '0'; -- processor-internal bootloader implemented? - sysinfo(2)(01) <= '1' when XBUS_EN else '0'; -- external bus interface implemented? - sysinfo(2)(02) <= '1' when int_imem_en_c else '0'; -- processor-internal instruction memory implemented? - sysinfo(2)(03) <= '1' when int_dmem_en_c else '0'; -- processor-internal data memory implemented? - sysinfo(2)(04) <= '1' when ON_CHIP_DEBUGGER_EN else '0'; -- on-chip debugger implemented? - sysinfo(2)(05) <= '1' when ICACHE_EN else '0'; -- processor-internal instruction cache implemented? - sysinfo(2)(06) <= '1' when DCACHE_EN else '0'; -- processor-internal data cache implemented? - sysinfo(2)(07) <= '1' when CLOCK_GATING_EN else '0'; -- enable clock gating when in sleep mode - sysinfo(2)(08) <= '1' when xcache_en_c else '0'; -- external bus interface cache implemented? - sysinfo(2)(09) <= '1' when XIP_EN else '0'; -- execute in place module implemented? + sysinfo(2)(0) <= '1' when INT_BOOTLOADER_EN else '0'; -- processor-internal bootloader implemented? + sysinfo(2)(1) <= '1' when XBUS_EN else '0'; -- external bus interface implemented? + sysinfo(2)(2) <= '1' when int_imem_en_c else '0'; -- processor-internal instruction memory implemented? + sysinfo(2)(3) <= '1' when int_dmem_en_c else '0'; -- processor-internal data memory implemented? + sysinfo(2)(4) <= '1' when ON_CHIP_DEBUGGER_EN else '0'; -- on-chip debugger implemented? + sysinfo(2)(5) <= '1' when ICACHE_EN else '0'; -- processor-internal instruction cache implemented? + sysinfo(2)(6) <= '1' when DCACHE_EN else '0'; -- processor-internal data cache implemented? + sysinfo(2)(7) <= '1' when CLOCK_GATING_EN else '0'; -- enable clock gating when in sleep mode + sysinfo(2)(8) <= '1' when xcache_en_c else '0'; -- external bus interface cache implemented? + sysinfo(2)(9) <= '1' when XIP_EN else '0'; -- execute in place module implemented? sysinfo(2)(10) <= '1' when xip_cache_en_c else '0'; -- execute in place cache implemented? - sysinfo(2)(11) <= '0'; -- reserved - sysinfo(2)(12) <= '0'; -- reserved - sysinfo(2)(13) <= '0'; -- reserved + sysinfo(2)(11) <= '0'; -- reserved + sysinfo(2)(12) <= '0'; -- reserved + sysinfo(2)(13) <= '0'; -- reserved sysinfo(2)(14) <= '1' when IO_DMA_EN else '0'; -- direct memory access controller (DMA) implemented? sysinfo(2)(15) <= '1' when IO_GPIO_EN else '0'; -- general purpose input/output port unit (GPIO) implemented? sysinfo(2)(16) <= '1' when IO_MTIME_EN else '0'; -- machine system timer (MTIME) implemented? @@ -127,10 +127,10 @@ begin sysinfo(2)(31) <= '1' when IO_CRC_EN else '0'; -- cyclic redundancy check unit (CRC) implemented? -- SYSINFO(3): Cache Configuration -- - sysinfo(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(block_size_in_bytes) - sysinfo(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(number_of_block) + sysinfo(3)(3 downto 0) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(block_size_in_bytes) + sysinfo(3)(7 downto 4) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(number_of_block) -- - sysinfo(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_BLOCK_SIZE), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(block_size) + sysinfo(3)(11 downto 8) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_BLOCK_SIZE), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(block_size) sysinfo(3)(15 downto 12) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_NUM_BLOCKS), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(num_blocks) -- sysinfo(3)(19 downto 16) <= std_ulogic_vector(to_unsigned(index_size_f(XIP_CACHE_BLOCK_SIZE), 4)) when xip_cache_en_c else (others => '0'); -- xip-cache: log2(block_size_in_bytes) diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index 3d6e444e8..20d34786c 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -340,7 +340,7 @@ begin -- say hello -- assert false report "[NEORV32] The NEORV32 RISC-V Processor " & - "(version 0x" & to_hstring32_f(hw_version_c) & "), " & + "(v" & print_version_f(hw_version_c) & "), " & "github.com/stnolting/neorv32" severity note; -- show main SoC configuration -- @@ -1033,7 +1033,18 @@ begin DEV_17_EN => IO_CRC_EN, DEV_17_BASE => base_io_crc_c, DEV_18_EN => IO_DMA_EN, DEV_18_BASE => base_io_dma_c, DEV_19_EN => IO_SLINK_EN, DEV_19_BASE => base_io_slink_c, - DEV_20_EN => IO_CFS_EN, DEV_20_BASE => base_io_cfs_c + DEV_20_EN => IO_CFS_EN, DEV_20_BASE => base_io_cfs_c, + DEV_21_EN => false, DEV_31_BASE => (others => '-'), -- reserved + DEV_22_EN => false, DEV_30_BASE => (others => '-'), -- reserved + DEV_23_EN => false, DEV_29_BASE => (others => '-'), -- reserved + DEV_24_EN => false, DEV_28_BASE => (others => '-'), -- reserved + DEV_25_EN => false, DEV_27_BASE => (others => '-'), -- reserved + DEV_26_EN => false, DEV_26_BASE => (others => '-'), -- reserved + DEV_27_EN => false, DEV_25_BASE => (others => '-'), -- reserved + DEV_28_EN => false, DEV_24_BASE => (others => '-'), -- reserved + DEV_29_EN => false, DEV_23_BASE => (others => '-'), -- reserved + DEV_30_EN => false, DEV_22_BASE => (others => '-'), -- reserved + DEV_31_EN => false, DEV_21_BASE => (others => '-') -- reserved ) port map ( main_req_i => io_req, @@ -1058,7 +1069,18 @@ begin dev_17_req_o => iodev_req(IODEV_CRC), dev_17_rsp_i => iodev_rsp(IODEV_CRC), dev_18_req_o => iodev_req(IODEV_DMA), dev_18_rsp_i => iodev_rsp(IODEV_DMA), dev_19_req_o => iodev_req(IODEV_SLINK), dev_19_rsp_i => iodev_rsp(IODEV_SLINK), - dev_20_req_o => iodev_req(IODEV_CFS), dev_20_rsp_i => iodev_rsp(IODEV_CFS) + dev_20_req_o => iodev_req(IODEV_CFS), dev_20_rsp_i => iodev_rsp(IODEV_CFS), + dev_21_req_o => open, dev_21_rsp_i => rsp_terminate_c, -- reserved + dev_22_req_o => open, dev_22_rsp_i => rsp_terminate_c, -- reserved + dev_23_req_o => open, dev_23_rsp_i => rsp_terminate_c, -- reserved + dev_24_req_o => open, dev_24_rsp_i => rsp_terminate_c, -- reserved + dev_25_req_o => open, dev_25_rsp_i => rsp_terminate_c, -- reserved + dev_26_req_o => open, dev_26_rsp_i => rsp_terminate_c, -- reserved + dev_27_req_o => open, dev_27_rsp_i => rsp_terminate_c, -- reserved + dev_28_req_o => open, dev_28_rsp_i => rsp_terminate_c, -- reserved + dev_29_req_o => open, dev_29_rsp_i => rsp_terminate_c, -- reserved + dev_30_req_o => open, dev_30_rsp_i => rsp_terminate_c, -- reserved + dev_31_req_o => open, dev_31_rsp_i => rsp_terminate_c -- reserved ); diff --git a/sw/bootloader/bootloader.c b/sw/bootloader/bootloader.c index 5da038696..49f09cd19 100644 --- a/sw/bootloader/bootloader.c +++ b/sw/bootloader/bootloader.c @@ -480,7 +480,7 @@ void start_app(int boot_xip) { /**********************************************************************//** * Bootloader trap handler. Used for the MTIME tick and to capture any other traps. * - * @note Since we have no runtime environment, we have to use the interrupt attribute here. + * @note Since we have no runtime environment we have to use the interrupt attribute here. **************************************************************************/ void __attribute__((interrupt("machine"))) bootloader_trap_handler(void) { @@ -728,9 +728,9 @@ void print_hex_word(uint32_t num) { -// ------------------------------------------------------------------------------------- +// ########################################################################################################## // SPI flash driver functions -// ------------------------------------------------------------------------------------- +// ########################################################################################################## /**********************************************************************//** * Wake up flash from deep sleep state @@ -744,6 +744,7 @@ void spi_flash_wakeup(void) { #endif } + /**********************************************************************//** * Check if SPI and flash are available/working by making sure the WEL * flag of the flash status register can be set and cleared again. @@ -774,6 +775,7 @@ int spi_flash_check(void) { #endif } + /**********************************************************************//** * Read byte from SPI flash. * diff --git a/sw/example/performance_tests/I/main.c b/sw/example/performance_tests/I/main.c index 745264900..858929071 100644 --- a/sw/example/performance_tests/I/main.c +++ b/sw/example/performance_tests/I/main.c @@ -133,8 +133,8 @@ int main() { #endif // setup input variables - uint startTime, stopTime; - uint totalTime = 0; + uint32_t startTime, stopTime; + uint32_t totalTime = 0; #ifndef instCalls #define instCalls 256 #endif diff --git a/sw/example/performance_tests/M/main.c b/sw/example/performance_tests/M/main.c index 2fdae7762..cb203108c 100644 --- a/sw/example/performance_tests/M/main.c +++ b/sw/example/performance_tests/M/main.c @@ -63,8 +63,8 @@ int main() { // time offset values // setup input variables - uint startTime, stopTime; - uint totalTime = 0; + uint32_t startTime, stopTime; + uint32_t totalTime = 0; #ifndef instCalls #define instCalls 256 diff --git a/sw/example/processor_check/main.c b/sw/example/processor_check/main.c index e9669180d..829840cef 100644 --- a/sw/example/processor_check/main.c +++ b/sw/example/processor_check/main.c @@ -149,7 +149,7 @@ int main() { // fancy intro // ----------------------------------------------- neorv32_rte_print_logo(); // show NEORV32 ASCII logo - neorv32_rte_print_credits(); // show project credits + neorv32_rte_print_about(); // show project credits neorv32_rte_print_hw_config(); // show full hardware configuration report @@ -992,7 +992,7 @@ int main() { // Fast interrupt channel 0 // ---------------------------------------------------------- neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c); - PRINT_STANDARD("[%i] FIRQ (TRNG) ", cnt_test); + PRINT_STANDARD("[%i] FIRQ0 (TRNG) ", cnt_test); if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_IO_TRNG)) { cnt_test++; diff --git a/sw/lib/include/neorv32.h b/sw/lib/include/neorv32.h index 48d728200..9210233e2 100644 --- a/sw/lib/include/neorv32.h +++ b/sw/lib/include/neorv32.h @@ -23,24 +23,60 @@ extern "C" { // Standard libraries #include #include -#include #include #include /**********************************************************************//** - * Processor clock prescaler select + * @name Main Address Space Sections **************************************************************************/ -enum NEORV32_CLOCK_PRSC_enum { - CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */ - CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */ - CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */ - CLK_PRSC_64 = 3, /**< CPU_CLK (from clk_i top signal) / 64 */ - CLK_PRSC_128 = 4, /**< CPU_CLK (from clk_i top signal) / 128 */ - CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */ - CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */ - CLK_PRSC_4096 = 7 /**< CPU_CLK (from clk_i top signal) / 4096 */ -}; +/**@{*/ +/** XIP-mapped memory base address */ +#define XIP_MEM_BASE_ADDRESS (0xE0000000U) +/** bootloader memory base address */ +#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U) +/** peripheral/IO devices memory base address */ +#define IO_BASE_ADDRESS (0xFFFFE000U) +/**@}*/ + + +/**********************************************************************//** + * @name IO Address Space Map - Peripheral/IO Devices + **************************************************************************/ +/**@{*/ +//#define NEORV32_???_BASE (0xFFFFE000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE100U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE200U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE300U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE400U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE500U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE600U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE700U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE800U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFE900U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFFFEA00U) /**< reserved */ +#define NEORV32_CFS_BASE (0xFFFFEB00U) /**< Custom Functions Subsystem (CFS) */ +#define NEORV32_SLINK_BASE (0xFFFFEC00U) /**< Stream Link Interface (SLINK) */ +#define NEORV32_DMA_BASE (0xFFFFED00U) /**< Direct Memory Access Controller (DMA) */ +#define NEORV32_CRC_BASE (0xFFFFEE00U) /**< Cyclic Redundancy Check Unit (DMA) */ +#define NEORV32_XIP_BASE (0xFFFFEF00U) /**< Execute In Place Module (XIP) */ +#define NEORV32_PWM_BASE (0xFFFFF000U) /**< Pulse Width Modulation Controller (PWM) */ +#define NEORV32_GPTMR_BASE (0xFFFFF100U) /**< General Purpose Timer (GPTMR) */ +#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) /**< 1-Wire Interface Controller (ONEWIRE) */ +#define NEORV32_XIRQ_BASE (0xFFFFF300U) /**< External Interrupt Controller (XIRQ) */ +#define NEORV32_MTIME_BASE (0xFFFFF400U) /**< Machine System Timer (MTIME) */ +#define NEORV32_UART0_BASE (0xFFFFF500U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */ +#define NEORV32_UART1_BASE (0xFFFFF600U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */ +#define NEORV32_SDI_BASE (0xFFFFF700U) /**< Serial Data Interface (SDI) */ +#define NEORV32_SPI_BASE (0xFFFFF800U) /**< Serial Peripheral Interface Controller (SPI) */ +#define NEORV32_TWI_BASE (0xFFFFF900U) /**< Two-Wire Interface Controller (TWI) */ +#define NEORV32_TRNG_BASE (0xFFFFFA00U) /**< True Random Number Generator (TRNG) */ +#define NEORV32_WDT_BASE (0xFFFFFB00U) /**< Watchdog Timer (WDT) */ +#define NEORV32_GPIO_BASE (0xFFFFFC00U) /**< General Purpose Input/Output Port Controller (GPIO) */ +#define NEORV32_NEOLED_BASE (0xFFFFFD00U) /**< Smart LED Hardware Interface (NEOLED) */ +#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) /**< System Information Memory (SYSINFO) */ +#define NEORV32_DM_BASE (0xFFFFFF00U) /**< On-Chip Debugger - Debug Module (OCD) */ +/**@}*/ /**********************************************************************//** @@ -153,47 +189,6 @@ enum NEORV32_CLOCK_PRSC_enum { /**@}*/ -/**********************************************************************//** - * @name Main Address Space Sections - **************************************************************************/ -/**@{*/ -/** XIP-mapped memory base address */ -#define XIP_MEM_BASE_ADDRESS (0xE0000000U) -/** bootloader memory base address */ -#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U) -/** peripheral/IO devices memory base address */ -#define IO_BASE_ADDRESS (0xFFFFE000U) -/**@}*/ - - -/**********************************************************************//** - * @name IO Address Space - Peripheral/IO Devices - **************************************************************************/ -/**@{*/ -#define NEORV32_CFS_BASE (0xFFFFEB00U) /**< Custom Functions Subsystem (CFS) */ -#define NEORV32_SLINK_BASE (0xFFFFEC00U) /**< Stream Link Interface (SLINK) */ -#define NEORV32_DMA_BASE (0xFFFFED00U) /**< Direct Memory Access Controller (DMA) */ -#define NEORV32_CRC_BASE (0xFFFFEE00U) /**< Cyclic Redundancy Check Unit (DMA) */ -#define NEORV32_XIP_BASE (0xFFFFEF00U) /**< Execute In Place Module (XIP) */ -#define NEORV32_PWM_BASE (0xFFFFF000U) /**< Pulse Width Modulation Controller (PWM) */ -#define NEORV32_GPTMR_BASE (0xFFFFF100U) /**< General Purpose Timer (GPTMR) */ -#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) /**< 1-Wire Interface Controller (ONEWIRE) */ -#define NEORV32_XIRQ_BASE (0xFFFFF300U) /**< External Interrupt Controller (XIRQ) */ -#define NEORV32_MTIME_BASE (0xFFFFF400U) /**< Machine System Timer (MTIME) */ -#define NEORV32_UART0_BASE (0xFFFFF500U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */ -#define NEORV32_UART1_BASE (0xFFFFF600U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */ -#define NEORV32_SDI_BASE (0xFFFFF700U) /**< Serial Data Interface (SDI) */ -#define NEORV32_SPI_BASE (0xFFFFF800U) /**< Serial Peripheral Interface Controller (SPI) */ -#define NEORV32_TWI_BASE (0xFFFFF900U) /**< Two-Wire Interface Controller (TWI) */ -#define NEORV32_TRNG_BASE (0xFFFFFA00U) /**< True Random Number Generator (TRNG) */ -#define NEORV32_WDT_BASE (0xFFFFFB00U) /**< Watchdog Timer (WDT) */ -#define NEORV32_GPIO_BASE (0xFFFFFC00U) /**< General Purpose Input/Output Port Controller (GPIO) */ -#define NEORV32_NEOLED_BASE (0xFFFFFD00U) /**< Smart LED Hardware Interface (NEOLED) */ -#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) /**< System Information Memory (SYSINFO) */ -#define NEORV32_DM_BASE (0xFFFFFF00U) /**< On-Chip Debugger - Debug Module (OCD) */ -/**@}*/ - - // ---------------------------------------------------------------------------- // Include all system header files // ---------------------------------------------------------------------------- @@ -203,6 +198,9 @@ enum NEORV32_CLOCK_PRSC_enum { // helper functions #include "neorv32_aux.h" +// legacy compatibility layer +#include "neorv32_legacy.h" + // cpu core #include "neorv32_cpu.h" #include "neorv32_cpu_amo.h" diff --git a/sw/lib/include/neorv32_aux.h b/sw/lib/include/neorv32_aux.h index d609ac578..17d5786c3 100644 --- a/sw/lib/include/neorv32_aux.h +++ b/sw/lib/include/neorv32_aux.h @@ -17,6 +17,7 @@ #include + /**********************************************************************//** * @name Select minimum/maximum **************************************************************************/ @@ -26,6 +27,23 @@ /**@}*/ +/**********************************************************************//** + * Processor clock prescaler select + **************************************************************************/ +/**@{*/ +enum NEORV32_CLOCK_PRSC_enum { + CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */ + CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */ + CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */ + CLK_PRSC_64 = 3, /**< CPU_CLK (from clk_i top signal) / 64 */ + CLK_PRSC_128 = 4, /**< CPU_CLK (from clk_i top signal) / 128 */ + CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */ + CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */ + CLK_PRSC_4096 = 7 /**< CPU_CLK (from clk_i top signal) / 4096 */ +}; +/**@}*/ + + /**********************************************************************//** * @name Date and time struct **************************************************************************/ @@ -48,9 +66,7 @@ typedef struct { /**@{*/ uint64_t neorv32_aux_date2unixtime(date_t* date); void neorv32_aux_unixtime2date(uint64_t unixtime, date_t* date); - uint64_t neorv32_aux_hexstr2uint64(char *buffer, uint8_t length); - uint32_t neorv32_aux_xorshift32(void); /**@}*/ diff --git a/sw/lib/include/neorv32_cfs.h b/sw/lib/include/neorv32_cfs.h index a67dd5dcc..f23e80d5c 100644 --- a/sw/lib/include/neorv32_cfs.h +++ b/sw/lib/include/neorv32_cfs.h @@ -20,6 +20,9 @@ #ifndef neorv32_cfs_h #define neorv32_cfs_h +#include + + /**********************************************************************//** * @name IO Device: Custom Functions Subsystem (CFS) **************************************************************************/ diff --git a/sw/lib/include/neorv32_cpu.h b/sw/lib/include/neorv32_cpu.h index 1db7d8c12..8e6d56220 100644 --- a/sw/lib/include/neorv32_cpu.h +++ b/sw/lib/include/neorv32_cpu.h @@ -16,6 +16,8 @@ #ifndef neorv32_cpu_h #define neorv32_cpu_h +#include + /**********************************************************************//** * @name Prototypes diff --git a/sw/lib/include/neorv32_cpu_amo.h b/sw/lib/include/neorv32_cpu_amo.h index ddfcc7ac8..ff111457e 100644 --- a/sw/lib/include/neorv32_cpu_amo.h +++ b/sw/lib/include/neorv32_cpu_amo.h @@ -16,6 +16,9 @@ #ifndef neorv32_cpu_amo_h #define neorv32_cpu_amo_h +#include + + // prototypes uint32_t neorv32_cpu_amoswapw(uint32_t addr, uint32_t wdata); uint32_t neorv32_cpu_amoaddw(uint32_t addr, uint32_t wdata); diff --git a/sw/lib/include/neorv32_cpu_cfu.h b/sw/lib/include/neorv32_cpu_cfu.h index 6f4d32073..8ee942e63 100644 --- a/sw/lib/include/neorv32_cpu_cfu.h +++ b/sw/lib/include/neorv32_cpu_cfu.h @@ -16,6 +16,9 @@ #ifndef neorv32_cpu_cfu_h #define neorv32_cpu_cfu_h +#include + + // prototypes int neorv32_cpu_cfu_available(void); diff --git a/sw/lib/include/neorv32_cpu_csr.h b/sw/lib/include/neorv32_cpu_csr.h index 9a2d55f16..6dd10be1a 100644 --- a/sw/lib/include/neorv32_cpu_csr.h +++ b/sw/lib/include/neorv32_cpu_csr.h @@ -16,6 +16,8 @@ #ifndef neorv32_cpu_csr_h #define neorv32_cpu_csr_h +#include + /**********************************************************************//** * Available CPU Control and Status Registers (CSRs) diff --git a/sw/lib/include/neorv32_crc.h b/sw/lib/include/neorv32_crc.h index ed69fb704..600cb824d 100644 --- a/sw/lib/include/neorv32_crc.h +++ b/sw/lib/include/neorv32_crc.h @@ -18,6 +18,9 @@ #ifndef neorv32_crc_h #define neorv32_crc_h +#include + + /**********************************************************************//** * @name IO Device: Cyclic Redundancy Check Unit (CRC) **************************************************************************/ diff --git a/sw/lib/include/neorv32_dm.h b/sw/lib/include/neorv32_dm.h index 78d6de84e..ae6969b9b 100644 --- a/sw/lib/include/neorv32_dm.h +++ b/sw/lib/include/neorv32_dm.h @@ -18,6 +18,9 @@ #ifndef neorv32_dm_h #define neorv32_dm_h +#include + + /**********************************************************************//** * @name IO Device: On-Chip Debugger (CANNOT be accessed by application software!) **************************************************************************/ diff --git a/sw/lib/include/neorv32_dma.h b/sw/lib/include/neorv32_dma.h index 8f5547e11..170a7b5f2 100644 --- a/sw/lib/include/neorv32_dma.h +++ b/sw/lib/include/neorv32_dma.h @@ -18,6 +18,9 @@ #ifndef neorv32_dma_h #define neorv32_dma_h +#include + + /**********************************************************************//** * @name IO Device: Direct Memory Access Controller (DMA) **************************************************************************/ diff --git a/sw/lib/include/neorv32_gpio.h b/sw/lib/include/neorv32_gpio.h index 595ceb52a..d7a28d5a8 100644 --- a/sw/lib/include/neorv32_gpio.h +++ b/sw/lib/include/neorv32_gpio.h @@ -18,6 +18,9 @@ #ifndef neorv32_gpio_h #define neorv32_gpio_h +#include + + /**********************************************************************//** * @name IO Device: General Purpose Input/Output Port Unit (GPIO) **************************************************************************/ diff --git a/sw/lib/include/neorv32_gptmr.h b/sw/lib/include/neorv32_gptmr.h index 08f9e84a6..bd8a355c6 100644 --- a/sw/lib/include/neorv32_gptmr.h +++ b/sw/lib/include/neorv32_gptmr.h @@ -18,6 +18,9 @@ #ifndef neorv32_gptmr_h #define neorv32_gptmr_h +#include + + /**********************************************************************//** * @name IO Device: General Purpose Timer (GPTMR) **************************************************************************/ diff --git a/sw/lib/include/neorv32_intrinsics.h b/sw/lib/include/neorv32_intrinsics.h index f311d7db9..e971c447f 100644 --- a/sw/lib/include/neorv32_intrinsics.h +++ b/sw/lib/include/neorv32_intrinsics.h @@ -16,6 +16,8 @@ #ifndef neorv32_intrinsics_h #define neorv32_intrinsics_h +#include + // **************************************************************************************************************************** // Custom Instruction Intrinsics diff --git a/sw/lib/include/neorv32_legacy.h b/sw/lib/include/neorv32_legacy.h new file mode 100644 index 000000000..e8919a94a --- /dev/null +++ b/sw/lib/include/neorv32_legacy.h @@ -0,0 +1,70 @@ +// ================================================================================ // +// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 // +// Copyright (c) NEORV32 contributors. // +// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. // +// Licensed under the BSD-3-Clause license, see LICENSE for details. // +// SPDX-License-Identifier: BSD-3-Clause // +// ================================================================================ // + +/** + * @file neorv32_legacy.h + * @brief Legacy compatibility layer. + * @warning Deprecated! Do not use for new designs! + * @see https://stnolting.github.io/neorv32/sw/files.html + */ + +#ifndef neorv32_legacy_h +#define neorv32_legacy_h + +#include + + +/**********************************************************************//** + * @name UART0 legacy compatibility wrappers + **************************************************************************/ +/**@{*/ +#define neorv32_uart0_available() neorv32_uart_available(NEORV32_UART0) +#define neorv32_uart0_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART0) +#define neorv32_uart0_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART0) +#define neorv32_uart0_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART0, baudrate, irq_mask) +#define neorv32_uart0_disable() neorv32_uart_disable(NEORV32_UART0) +#define neorv32_uart0_enable() neorv32_uart_enable(NEORV32_UART0) +#define neorv32_uart0_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART0) +#define neorv32_uart0_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART0) +#define neorv32_uart0_putc(c) neorv32_uart_putc(NEORV32_UART0, c) +#define neorv32_uart0_rx_clear() neorv32_uart_rx_clear(NEORV32_UART0) +#define neorv32_uart0_tx_clear() neorv32_uart_tx_clear(NEORV32_UART0) +#define neorv32_uart0_tx_busy() neorv32_uart_tx_busy(NEORV32_UART0) +#define neorv32_uart0_getc() neorv32_uart_getc(NEORV32_UART0) +#define neorv32_uart0_char_received() neorv32_uart_char_received(NEORV32_UART0) +#define neorv32_uart0_char_received_get() neorv32_uart_char_received_get(NEORV32_UART0) +#define neorv32_uart0_puts(s) neorv32_uart_puts(NEORV32_UART0, s) +#define neorv32_uart0_printf(...) neorv32_uart_printf(NEORV32_UART0, __VA_ARGS__) +#define neorv32_uart0_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART0, buffer, max_size, echo) +/**@}*/ + +/**********************************************************************//** + * @name UART1 legacy compatibility wrappers + **************************************************************************/ +/**@{*/ +#define neorv32_uart1_available() neorv32_uart_available(NEORV32_UART1) +#define neorv32_uart1_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART1) +#define neorv32_uart1_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART1) +#define neorv32_uart1_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART1, baudrate, irq_mask) +#define neorv32_uart1_disable() neorv32_uart_disable(NEORV32_UART1) +#define neorv32_uart1_enable() neorv32_uart_enable(NEORV32_UART1) +#define neorv32_uart1_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART1) +#define neorv32_uart1_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART1) +#define neorv32_uart1_putc(c) neorv32_uart_putc(NEORV32_UART1, c) +#define neorv32_uart1_rx_clear() neorv32_uart_rx_clear(NEORV32_UART1) +#define neorv32_uart1_tx_clear() neorv32_uart_tx_clear(NEORV32_UART1) +#define neorv32_uart1_tx_busy() neorv32_uart_tx_busy(NEORV32_UART1) +#define neorv32_uart1_getc() neorv32_uart_getc(NEORV32_UART1) +#define neorv32_uart1_char_received() neorv32_uart_char_received(NEORV32_UART1) +#define neorv32_uart1_char_received_get() neorv32_uart_char_received_get(NEORV32_UART1) +#define neorv32_uart1_puts(s) neorv32_uart_puts(NEORV32_UART1, s) +#define neorv32_uart1_printf(...) neorv32_uart_printf(NEORV32_UART1, __VA_ARGS__) +#define neorv32_uart1_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART1, buffer, max_size, echo) +/**@}*/ + +#endif // neorv32_legacy_h diff --git a/sw/lib/include/neorv32_mtime.h b/sw/lib/include/neorv32_mtime.h index ff8568e34..51722de48 100644 --- a/sw/lib/include/neorv32_mtime.h +++ b/sw/lib/include/neorv32_mtime.h @@ -18,6 +18,9 @@ #ifndef neorv32_mtime_h #define neorv32_mtime_h +#include + + /**********************************************************************//** * @name IO Device: Machine System Timer (MTIME) **************************************************************************/ diff --git a/sw/lib/include/neorv32_neoled.h b/sw/lib/include/neorv32_neoled.h index 8644ae23d..a4b5689e1 100644 --- a/sw/lib/include/neorv32_neoled.h +++ b/sw/lib/include/neorv32_neoled.h @@ -18,6 +18,9 @@ #ifndef neorv32_neoled_h #define neorv32_neoled_h +#include + + /**********************************************************************//** * @name IO Device: Smart LED Hardware Interface (NEOLED) **************************************************************************/ diff --git a/sw/lib/include/neorv32_onewire.h b/sw/lib/include/neorv32_onewire.h index ca8cbba9f..e81eacaf1 100644 --- a/sw/lib/include/neorv32_onewire.h +++ b/sw/lib/include/neorv32_onewire.h @@ -18,6 +18,9 @@ #ifndef neorv32_onewire_h #define neorv32_onewire_h +#include + + /**********************************************************************//** * @name IO Device: 1-Wire Interface Controller (ONEWIRE) **************************************************************************/ diff --git a/sw/lib/include/neorv32_pwm.h b/sw/lib/include/neorv32_pwm.h index 713f1badd..bdf5f6c67 100644 --- a/sw/lib/include/neorv32_pwm.h +++ b/sw/lib/include/neorv32_pwm.h @@ -18,6 +18,9 @@ #ifndef neorv32_pwm_h #define neorv32_pwm_h +#include + + /**********************************************************************//** * @name IO Device: Pulse Width Modulation Controller (PWM) **************************************************************************/ diff --git a/sw/lib/include/neorv32_rte.h b/sw/lib/include/neorv32_rte.h index f6583be15..051dc0dde 100644 --- a/sw/lib/include/neorv32_rte.h +++ b/sw/lib/include/neorv32_rte.h @@ -16,6 +16,8 @@ #ifndef neorv32_rte_h #define neorv32_rte_h +#include + /**********************************************************************//** * NEORV32 runtime environment: Number of available traps. @@ -69,11 +71,10 @@ int neorv32_rte_handler_uninstall(int id); void neorv32_rte_debug_handler(void); uint32_t neorv32_rte_context_get(int x); void neorv32_rte_context_put(int x, uint32_t data); -void neorv32_rte_print_info(void); void neorv32_rte_print_hw_config(void); void neorv32_rte_print_hw_version(void); -void neorv32_rte_print_credits(void); +void neorv32_rte_print_about(void); void neorv32_rte_print_logo(void); void neorv32_rte_print_license(void); /**@}*/ diff --git a/sw/lib/include/neorv32_sdi.h b/sw/lib/include/neorv32_sdi.h index d45f97748..d46eda550 100644 --- a/sw/lib/include/neorv32_sdi.h +++ b/sw/lib/include/neorv32_sdi.h @@ -18,6 +18,9 @@ #ifndef neorv32_sdi_h #define neorv32_sdi_h +#include + + /**********************************************************************//** * @name IO Device: Serial Data Interface (SDI) **************************************************************************/ diff --git a/sw/lib/include/neorv32_slink.h b/sw/lib/include/neorv32_slink.h index 10492f503..8d1f1245c 100644 --- a/sw/lib/include/neorv32_slink.h +++ b/sw/lib/include/neorv32_slink.h @@ -16,6 +16,9 @@ #ifndef neorv32_slink_h #define neorv32_slink_h +#include + + /**********************************************************************//** * @name IO Device: Stream Link Interface (SLINK) **************************************************************************/ diff --git a/sw/lib/include/neorv32_spi.h b/sw/lib/include/neorv32_spi.h index c4b3d4ff2..615ca36d5 100644 --- a/sw/lib/include/neorv32_spi.h +++ b/sw/lib/include/neorv32_spi.h @@ -18,6 +18,9 @@ #ifndef neorv32_spi_h #define neorv32_spi_h +#include + + /**********************************************************************//** * @name IO Device: Serial Peripheral Interface Controller (SPI) **************************************************************************/ diff --git a/sw/lib/include/neorv32_sysinfo.h b/sw/lib/include/neorv32_sysinfo.h index fff1c3a6b..5a8f87b75 100644 --- a/sw/lib/include/neorv32_sysinfo.h +++ b/sw/lib/include/neorv32_sysinfo.h @@ -16,6 +16,9 @@ #ifndef neorv32_sysinfo_h #define neorv32_sysinfo_h +#include + + /**********************************************************************//** * @name IO Device: System Configuration Information Memory (SYSINFO) **************************************************************************/ diff --git a/sw/lib/include/neorv32_trng.h b/sw/lib/include/neorv32_trng.h index dd440c432..73ba7d0d5 100644 --- a/sw/lib/include/neorv32_trng.h +++ b/sw/lib/include/neorv32_trng.h @@ -18,6 +18,9 @@ #ifndef neorv32_trng_h #define neorv32_trng_h +#include + + /**********************************************************************//** * @name IO Device: True Random Number Generator (TRNG) **************************************************************************/ diff --git a/sw/lib/include/neorv32_twi.h b/sw/lib/include/neorv32_twi.h index 220c7fe20..5ec40aad6 100644 --- a/sw/lib/include/neorv32_twi.h +++ b/sw/lib/include/neorv32_twi.h @@ -18,6 +18,9 @@ #ifndef neorv32_twi_h #define neorv32_twi_h +#include + + /**********************************************************************//** * @name IO Device: Two-Wire Interface Controller (TWI) **************************************************************************/ diff --git a/sw/lib/include/neorv32_uart.h b/sw/lib/include/neorv32_uart.h index f755f8996..5fc2b616f 100644 --- a/sw/lib/include/neorv32_uart.h +++ b/sw/lib/include/neorv32_uart.h @@ -16,59 +16,10 @@ #ifndef neorv32_uart_h #define neorv32_uart_h -// Libs required by functions +#include #include -/**********************************************************************//** - * @name UART0 easy-access aliases - **************************************************************************/ -/**@{*/ -#define neorv32_uart0_available() neorv32_uart_available(NEORV32_UART0) -#define neorv32_uart0_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART0) -#define neorv32_uart0_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART0) -#define neorv32_uart0_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART0, baudrate, irq_mask) -#define neorv32_uart0_disable() neorv32_uart_disable(NEORV32_UART0) -#define neorv32_uart0_enable() neorv32_uart_enable(NEORV32_UART0) -#define neorv32_uart0_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART0) -#define neorv32_uart0_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART0) -#define neorv32_uart0_putc(c) neorv32_uart_putc(NEORV32_UART0, c) -#define neorv32_uart0_rx_clear() neorv32_uart_rx_clear(NEORV32_UART0) -#define neorv32_uart0_tx_clear() neorv32_uart_tx_clear(NEORV32_UART0) -#define neorv32_uart0_tx_busy() neorv32_uart_tx_busy(NEORV32_UART0) -#define neorv32_uart0_getc() neorv32_uart_getc(NEORV32_UART0) -#define neorv32_uart0_char_received() neorv32_uart_char_received(NEORV32_UART0) -#define neorv32_uart0_char_received_get() neorv32_uart_char_received_get(NEORV32_UART0) -#define neorv32_uart0_puts(s) neorv32_uart_puts(NEORV32_UART0, s) -#define neorv32_uart0_printf(...) neorv32_uart_printf(NEORV32_UART0, __VA_ARGS__) -#define neorv32_uart0_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART0, buffer, max_size, echo) -/**@}*/ - -/**********************************************************************//** - * @name UART1 easy-access aliases - **************************************************************************/ -/**@{*/ -#define neorv32_uart1_available() neorv32_uart_available(NEORV32_UART1) -#define neorv32_uart1_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART1) -#define neorv32_uart1_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART1) -#define neorv32_uart1_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART1, baudrate, irq_mask) -#define neorv32_uart1_disable() neorv32_uart_disable(NEORV32_UART1) -#define neorv32_uart1_enable() neorv32_uart_enable(NEORV32_UART1) -#define neorv32_uart1_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART1) -#define neorv32_uart1_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART1) -#define neorv32_uart1_putc(c) neorv32_uart_putc(NEORV32_UART1, c) -#define neorv32_uart1_rx_clear() neorv32_uart_rx_clear(NEORV32_UART1) -#define neorv32_uart1_tx_clear() neorv32_uart_tx_clear(NEORV32_UART1) -#define neorv32_uart1_tx_busy() neorv32_uart_tx_busy(NEORV32_UART1) -#define neorv32_uart1_getc() neorv32_uart_getc(NEORV32_UART1) -#define neorv32_uart1_char_received() neorv32_uart_char_received(NEORV32_UART1) -#define neorv32_uart1_char_received_get() neorv32_uart_char_received_get(NEORV32_UART1) -#define neorv32_uart1_puts(s) neorv32_uart_puts(NEORV32_UART1, s) -#define neorv32_uart1_printf(...) neorv32_uart_printf(NEORV32_UART1, __VA_ARGS__) -#define neorv32_uart1_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART1, buffer, max_size, echo) -/**@}*/ - - /**********************************************************************//** * @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1) **************************************************************************/ diff --git a/sw/lib/include/neorv32_wdt.h b/sw/lib/include/neorv32_wdt.h index e9455a060..dba1fa8ce 100644 --- a/sw/lib/include/neorv32_wdt.h +++ b/sw/lib/include/neorv32_wdt.h @@ -18,6 +18,9 @@ #ifndef neorv32_wdt_h #define neorv32_wdt_h +#include + + /**********************************************************************//** * @name IO Device: Watchdog Timer (WDT) **************************************************************************/ diff --git a/sw/lib/include/neorv32_xip.h b/sw/lib/include/neorv32_xip.h index 6500ed292..6e6f8436c 100644 --- a/sw/lib/include/neorv32_xip.h +++ b/sw/lib/include/neorv32_xip.h @@ -18,6 +18,9 @@ #ifndef neorv32_xip_h #define neorv32_xip_h +#include + + /**********************************************************************//** * @name IO Device: Execute In Place Module (XIP) **************************************************************************/ diff --git a/sw/lib/include/neorv32_xirq.h b/sw/lib/include/neorv32_xirq.h index 41199eb26..590a6fde0 100644 --- a/sw/lib/include/neorv32_xirq.h +++ b/sw/lib/include/neorv32_xirq.h @@ -16,6 +16,9 @@ #ifndef neorv32_xirq_h #define neorv32_xirq_h +#include + + /**********************************************************************//** * @name IO Device: External Interrupt Controller (XIRQ) **************************************************************************/ diff --git a/sw/lib/source/neorv32_rte.c b/sw/lib/source/neorv32_rte.c index 354ddadae..4e088f84d 100644 --- a/sw/lib/source/neorv32_rte.c +++ b/sw/lib/source/neorv32_rte.c @@ -111,7 +111,7 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) { "addi sp, sp, -16*4 \n" #endif - "sw x0, 0*4(sp) \n" + "sw x0, 0*4(sp) \n" // is always zero, but backup to have a "complete" indexable register frame "sw x1, 1*4(sp) \n" "csrrw x1, mscratch, sp \n" // mscratch = base address of original context @@ -182,7 +182,7 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) { case TRAP_CODE_FIRQ_13: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break; case TRAP_CODE_FIRQ_14: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break; case TRAP_CODE_FIRQ_15: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break; - default: handler_base = (uint32_t)(&neorv32_rte_debug_handler); break; + default: handler_base = (uint32_t)(&neorv32_rte_debug_handler); break; } // execute handler @@ -211,7 +211,7 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) { // restore context asm volatile ( -// "lw x0, 0*4(sp) \n" +// "lw x0, 0*4(sp) \n" // hardwired to zero "lw x1, 1*4(sp) \n" // restore 2x at the very end "lw x3, 3*4(sp) \n" @@ -260,6 +260,7 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) { **************************************************************************/ uint32_t neorv32_rte_context_get(int x) { + // MSCRATCH CSR contain the stack pointer of the interrupted program uint32_t tmp = neorv32_cpu_csr_read(CSR_MSCRATCH); #ifdef __riscv_32e tmp += (x & 15) << 2; @@ -279,6 +280,7 @@ uint32_t neorv32_rte_context_get(int x) { **************************************************************************/ void neorv32_rte_context_put(int x, uint32_t data) { + // MSCRATCH CSR contain the stack pointer of the interrupted program uint32_t tmp = neorv32_cpu_csr_read(CSR_MSCRATCH); #ifdef __riscv_32e tmp += (x & 15) << 2; @@ -377,70 +379,6 @@ void neorv32_rte_debug_handler(void) { } -/**********************************************************************//** - * NEORV32 runtime environment (RTE): - * Print current RTE configuration via UART0. - **************************************************************************/ -void neorv32_rte_print_info(void) { - - const char trap_name[NEORV32_RTE_NUM_TRAPS][11] = { - "I_ACCESS ", - "I_ILLEGAL ", - "I_MISALIGN", - "BREAKPOINT", - "L_MISALIGN", - "L_ACCESS ", - "S_MISALIGN", - "S_ACCESS ", - "UENV_CALL ", - "MENV_CALL ", - "MSI ", - "MTI ", - "MEI ", - "FIRQ_0 ", - "FIRQ_1 ", - "FIRQ_2 ", - "FIRQ_3 ", - "FIRQ_4 ", - "FIRQ_5 ", - "FIRQ_6 ", - "FIRQ_7 ", - "FIRQ_8 ", - "FIRQ_9 ", - "FIRQ_10 ", - "FIRQ_11 ", - "FIRQ_12 ", - "FIRQ_13 ", - "FIRQ_14 ", - "FIRQ_15 " - }; - - if (neorv32_uart0_available() == 0) { - return; // cannot output anything if UART0 is not implemented - } - - neorv32_uart0_puts("\n\n<< NEORV32 RTE Configuration >>\n\n"); - - // header - neorv32_uart0_puts("-------------------------------\n"); - neorv32_uart0_puts("Trap Name [ID] Handler\n"); - neorv32_uart0_puts("-------------------------------\n"); - - uint32_t i; - for (i=0; i