diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd
index 6dcd0779d..42cdf8486 100644
--- a/sim/neorv32_tb.vhd
+++ b/sim/neorv32_tb.vhd
@@ -100,6 +100,7 @@ architecture neorv32_tb_rtl of neorv32_tb is
   signal slink_val : std_ulogic;
   signal slink_lst : std_ulogic;
   signal slink_rdy : std_ulogic;
+  signal slink_id  : std_ulogic_vector(3 downto 0);
 
   -- Wishbone bus --
   type wishbone_t is record
@@ -305,12 +306,14 @@ begin
     xbus_err_i     => wb_cpu.err,      -- transfer error
     -- Stream Link Interface (available if IO_SLINK_EN = true) --
     slink_rx_dat_i => slink_dat,       -- RX input data
+    slink_rx_src_i => slink_id,        -- RX source routing information
     slink_rx_val_i => slink_val,       -- RX valid input
-    slink_rx_lst_i => slink_lst,       -- last element of stream
+    slink_rx_lst_i => slink_lst,       -- RX last element of stream
     slink_rx_rdy_o => slink_rdy,       -- RX ready to receive
     slink_tx_dat_o => slink_dat,       -- TX output data
+    slink_tx_dst_o => slink_id,        -- TX destination routing information
     slink_tx_val_o => slink_val,       -- TX valid output
-    slink_tx_lst_o => slink_lst,       -- last element of stream
+    slink_tx_lst_o => slink_lst,       -- TX last element of stream
     slink_tx_rdy_i => slink_rdy,       -- TX ready to send
     -- XIP (execute in place via SPI) signals (available if XIP_EN = true) --
     xip_csn_o      => open,            -- chip-select, low-active
diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd
index 7d880ebd6..6b3884cd1 100644
--- a/sim/simple/neorv32_tb.simple.vhd
+++ b/sim/simple/neorv32_tb.simple.vhd
@@ -120,6 +120,7 @@ architecture neorv32_tb_simple_rtl of neorv32_tb_simple is
   signal slink_val : std_ulogic;
   signal slink_lst : std_ulogic;
   signal slink_rdy : std_ulogic;
+  signal slink_id  : std_ulogic_vector(3 downto 0);
 
   -- Wishbone bus --
   type wishbone_t is record
@@ -281,12 +282,14 @@ begin
     xbus_err_i     => wb_cpu.err,      -- transfer error
     -- Stream Link Interface (available if IO_SLINK_EN = true) --
     slink_rx_dat_i => slink_dat,       -- RX input data
+    slink_rx_src_i => slink_id,        -- RX source routing information
     slink_rx_val_i => slink_val,       -- RX valid input
-    slink_rx_lst_i => slink_lst,       -- last element of stream
+    slink_rx_lst_i => slink_lst,       -- RX last element of stream
     slink_rx_rdy_o => slink_rdy,       -- RX ready to receive
     slink_tx_dat_o => slink_dat,       -- TX output data
+    slink_tx_dst_o => slink_id,        -- TX destination routing information
     slink_tx_val_o => slink_val,       -- TX valid output
-    slink_tx_lst_o => slink_lst,       -- last element of stream
+    slink_tx_lst_o => slink_lst,       -- TX last element of stream
     slink_tx_rdy_i => slink_rdy,       -- TX ready to send
     -- XIP (execute in place via SPI) signals (available if XIP_EN = true) --
     xip_csn_o      => open,            -- chip-select, low-active