From 021c74adb0d8917af86f5f39c98a43a4acb3e526 Mon Sep 17 00:00:00 2001
From: stnolting <stnolting@gmail.com>
Date: Wed, 5 Jun 2024 17:26:27 +0200
Subject: [PATCH] update radiant/upduino_v3 setup #173

---
 radiant/UPduino_v3/neorv32_upduino_v3.rdf | 51 ++++++++++++-----------
 1 file changed, 27 insertions(+), 24 deletions(-)

diff --git a/radiant/UPduino_v3/neorv32_upduino_v3.rdf b/radiant/UPduino_v3/neorv32_upduino_v3.rdf
index f4fe96e..82c580a 100644
--- a/radiant/UPduino_v3/neorv32_upduino_v3.rdf
+++ b/radiant/UPduino_v3/neorv32_upduino_v3.rdf
@@ -3,67 +3,64 @@
     <Options/>
     <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
         <Options def_top="neorv32_upduino_v3_top"/>
-        <Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
-            <Options lib="work" top_module="neorv32_upduino_v3_top"/>
-        </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_package.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_clockgate.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_bootloader_image.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
         <Source name="../../neorv32/rtl/core/neorv32_boot_rom.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_bootloader_image.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
         <Source name="../../neorv32/rtl/core/neorv32_cfs.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_clockgate.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_alu.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_control.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
         <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_cond.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_alu.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_cond.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_lsu.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_pmp.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu_control.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_lsu.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_cpu.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_pmp.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_xip.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
         <Source name="../../neorv32/rtl/core/neorv32_crc.vhd" type="VHDL" type_short="VHDL">
@@ -102,9 +99,6 @@
         <Source name="../../neorv32/rtl/core/neorv32_onewire.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_package.vhd" type="VHDL" type_short="VHDL">
-            <Options lib="neorv32"/>
-        </Source>
         <Source name="../../neorv32/rtl/core/neorv32_pwm.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
@@ -132,12 +126,18 @@
         <Source name="../../neorv32/rtl/core/neorv32_wdt.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
-        <Source name="../../neorv32/rtl/core/neorv32_wishbone.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../neorv32/rtl/core/neorv32_xip.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
         <Source name="../../neorv32/rtl/core/neorv32_xirq.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
+        <Source name="../../neorv32/rtl/core/neorv32_cache.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="neorv32"/>
+        </Source>
+        <Source name="../../neorv32/rtl/core/neorv32_xbus.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="neorv32"/>
+        </Source>
         <Source name="neorv32_dmem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
@@ -147,6 +147,9 @@
         <Source name="../../neorv32/rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
+        <Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work" top_module="neorv32_upduino_v3_top"/>
+        </Source>
         <Source name="neorv32_upduino_v3.pdc" type="Physical Constraints File" type_short="PDC">
             <Options/>
         </Source>