Section 9.5 Interrupt Enables is unnecessarily misleading.

[robertlipe]

SiFive U74 Manual 20G1.03.00

Starting in section 9.4 (to set up a rhythm here...) we have precedence of a 132 bit register carried over five words. It starts at 0x0C00_1000 and it ends at 0x0C00_1010. It would be nice if Table 45 and Table 46 had some kind of connection marker or something to show that this was the top and bottom ends of that 132 bits, but that's manageable. (Bonus points for making this better to show that Pending 2-4 live in here and show the same format.)

Section 9.5 starts OK. It describes that we have another 132-bit register that follows the same form. It's a little alarming that it calls out that 64 or 32-bit accesses are legal. Are they NOT legal in the others? Where else are they legal?

Section 9.5 really leaves the rails that it describes TWO sets of 132-bit registers, the M mode and the S mode for each of the 132 bits controlled by the PLIC, but shows the beginning of M and the end of S.

MACHINE MODE
0x0C00_2000.0 = hardwired 0
0x0C00_2000.1 = intr 1
[ ... ]
0x0C00_2000.31 = intr 31.
0x0C00_2004 should be 32-63
0x0C00_2008 63-95
0x0C00_200C 96-127
0x0C00_2010 128, 129, 130, 131, 132.

Here, adjacent tables showing the start of Machine and the end of Machine mode is a little funky (why not one table?) but it's OK

Table 47 shows the start of enable1 for Machine.
Table 49 shows the end of enable5 for System.
This is super weird. I think we want something more like

SYSTEM MODE
0x0C00_2080.0 = hardwired 0
0x0C00_2090.128-132 = 128, 129, 130, 131, 132. for System Enables

It stands out if you do a search for "2080", the offset of a S mode into enables, and notice that it appears only in one place. There is no callout for the end of M mode or the beginning of S mode in section 9.5.

Each of Table 47 and Table 48 should probably be split into two tables, showing the beginning and the end, as is done in 45 and 46, but it starts to feel pretty heavy. A rethink of the table presentation is probably worthwhile.

[jrtc27]

Section 9.5 starts OK. It describes that we have another 132-bit register that follows the same form. It's a little alarming that it calls out that 64 or 32-bit accesses are legal. Are they NOT legal in the others? Where else are they legal?

The RISC-V PLIC spec only defines them as 32-bit registers, so no, 64-bit accesses are not legal unless your platform says otherwise.

[robertlipe]

I didn't even think of that interpretation, but I apologize for what I now see was misleading on my part. I wasn't saying it was a literal 132 bit register. I meant that it was 132 bits of values, chunked 32 at a time in the "obvious" way as I described in my lines under the "MACHINE MODE" heading in post 1.

Section 9.5, uniquely, it seems, implies that 64-bit accesses should work. It seems weird that these are the only registers where that's true. If that's not true, that sentence should be stricken, no? It's not terribly useful even if it is possible, IMO.

The bigger problem in this report was the second half - showing the start of Machine and the end of System without any acknowledgement that they're not the same and that there is a gap between them.