{"payload":{"header_redesign_enabled":false,"results":[{"id":"806746791","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"shahed22/Architectural-Design-for-Bus-interface-connected-with-LFSR","hl_trunc_description":"bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system…","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":806746791,"name":"Architectural-Design-for-Bus-interface-connected-with-LFSR","owner_id":78405065,"owner_login":"shahed22","updated_at":"2024-05-28T05:08:32.004Z","has_issues":true}},"sponsorable":false,"topics":["asic","fsm","interface","architecture","rtl","verilog","peripherals","datapath","soc","testbench","lfsr","32-bit","32bit","bus-interface","asic-design","controlpath","datapath-design","lfsr-algorithm"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":75,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ashahed22%252FArchitectural-Design-for-Bus-interface-connected-with-LFSR%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/shahed22/Architectural-Design-for-Bus-interface-connected-with-LFSR/star":{"post":"WbUA4fs_SKdqk5RwKo0hyTrSvg7RMEQqSjbGdcgYzgxH9EicVkonPwks-_n35AFzyiF8X1Dxu5btxYyFsLVCGg"},"/shahed22/Architectural-Design-for-Bus-interface-connected-with-LFSR/unstar":{"post":"UKUTgi9wSxGHPLuf1yJXwxymJMQkUXNnF66DaVjvGT7xkHnpq-uIV7X3-yZWS-jr3IAF6y1C3flbDzXli3v5Hw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"kiGTtGMowrD3f8vu0ZY_P1UqHPPE8hDarQG_koK03uAzghkXcucX_tg_Z0OEZziZVItHHRCZizXZzOA0_qM5hQ"}}},"title":"Repository search results"}