From d26cdb81c161d7b5b0f6bd7f185ae591b52b186f Mon Sep 17 00:00:00 2001 From: Dream Wu Date: Thu, 10 Oct 2024 17:07:57 +0800 Subject: [PATCH] replace FqChipK1 --- zkevm-circuits/src/sig_circuit.rs | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/zkevm-circuits/src/sig_circuit.rs b/zkevm-circuits/src/sig_circuit.rs index d679296ec0..6589a9cf9c 100644 --- a/zkevm-circuits/src/sig_circuit.rs +++ b/zkevm-circuits/src/sig_circuit.rs @@ -43,7 +43,7 @@ use halo2_ecc::{ FieldChip, }, }; -use halo2_proofs::{arithmetic::CurveAffine, halo2curves::bls12_381::Fp}; +use halo2_proofs::arithmetic::CurveAffine; mod ecdsa; mod utils; @@ -52,7 +52,6 @@ pub(crate) use utils::*; use halo2_proofs::{ circuit::{Layouter, Value}, - halo2curves::group::GroupEncoding, // secp256k1 curve halo2curves::secp256k1::{Fp as Fp_K1, Fq as Fq_K1, Secp256k1Affine}, // p256 curve @@ -61,7 +60,7 @@ use halo2_proofs::{ poly::Rotation, }; -use ethers_core::{k256::elliptic_curve::AffinePoint, utils::keccak256}; +use ethers_core::utils::keccak256; use itertools::Itertools; use log::error; use std::{iter, marker::PhantomData}; @@ -539,8 +538,7 @@ impl SigCircuit { gate.assert_is_const(ctx, &pk_is_valid, F::one()); // build Fq chip from Fp chip - // TODO: check if need to add new fq_chip_r - let fq_chip = FqChipK1::construct(ecdsa_chip.range().clone(), 88, 3, modulus::()); + let fq_chip = FpConfig::::construct(ecdsa_chip.range().clone(), 88, 3, modulus::()); let integer_r = fq_chip.load_private(ctx, FpConfig::::fe_to_witness(&Value::known(*sig_r))); let integer_s = @@ -617,6 +615,7 @@ impl SigCircuit { ecc_chip .field_chip .range + // TODO: check 87 is appropriate for p256 .range_check(ctx, &assigned_y_tmp, 87); let pk_not_zero = gate.not(ctx, QuantumCell::Existing(pk_is_zero)); @@ -699,8 +698,6 @@ impl SigCircuit { ctx: &mut Context, ecdsa_chip: &FpChipK1, sign_data: &SignData, - //TODO: refactor this method to sign_data_decomposition - // or just add new parameter `sign_data_r1` assigned_data: &AssignedECDSA>, ) -> Result, Error> { // build ecc chip from Fp chip @@ -999,7 +996,6 @@ impl SigCircuit { ctx: &mut Context, rlc_chip: &RangeConfig, sign_data: &SignData, - // TODO: add sign_data_r1 sign_data_decomposed: &SignDataDecomposed, challenges: &Challenges>, assigned_ecdsa: &AssignedECDSA>, @@ -1289,6 +1285,7 @@ impl SigCircuit { // ================================================ // step 3: compute RLC of keys and messages // ================================================ + // TODO: make assigned_sig_values include r1 signature. let (assigned_keccak_values, assigned_sig_values): ( Vec<[AssignedValue; 3]>, Vec>,