{"payload":{"header_redesign_enabled":false,"results":[{"id":"157973246","archived":false,"color":"#b2b7f8","followers":2,"has_funding_file":false,"hl_name":"sarthi92/boron_codesign","hl_trunc_description":"ZYNQ7 FPGA Co-design of BORON Cipher","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":157973246,"name":"boron_codesign","owner_id":10906140,"owner_login":"sarthi92","updated_at":"2018-11-17T11:23:06.113Z","has_issues":true}},"sponsorable":false,"topics":["c","fpga","verilog","codesign","zynq-7000","axi4"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":72,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Asarthi92%252Fboron_codesign%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/sarthi92/boron_codesign/star":{"post":"q2oY_Q5I6wYfTgNWDEBiwN1PIwBl1_HQAqjwJC22ZY1WG-X4u_tT554oVHTt4v3TvF3gCuuqTVXPNg9VXRAtDg"},"/sarthi92/boron_codesign/unstar":{"post":"50EZ16D8ainELC-mddzIDGEdjT5DVM6O2OAhAxiw4R4gReufgyqw-bFjuO3hoOcKlQa8c4VQNTRJFVhIMYhZeA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"gtWlUurbbTqPBU1hyT1GBUWa2inau4ANyklSFYs_m4hSgLvIuTmd4Lr0RXTYY6V20GF7snPuXR7O627MArn-Og"}}},"title":"Repository search results"}