From 7b694396f7a93baba66f2236432af44688041e9a Mon Sep 17 00:00:00 2001
From: khei4 <kk.asano.luxy@gmail.com>
Date: Tue, 15 Aug 2023 20:52:54 +0900
Subject: [PATCH] add codegen test for issue 107554

specify llvm-version and bit width for int arg
---
 tests/codegen/trailing_zeros.rs | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/codegen/trailing_zeros.rs

diff --git a/tests/codegen/trailing_zeros.rs b/tests/codegen/trailing_zeros.rs
new file mode 100644
index 0000000000000..c9a5ed312f2d8
--- /dev/null
+++ b/tests/codegen/trailing_zeros.rs
@@ -0,0 +1,22 @@
+// compile-flags: -O
+// min-llvm-version: 17
+
+#![crate_type = "lib"]
+
+// CHECK-LABEL: @trailing_zeros_ge
+#[no_mangle]
+pub fn trailing_zeros_ge(val: u32) -> bool {
+    // CHECK: %[[AND:.*]] = and i32 %val, 7
+    // CHECK: %[[ICMP:.*]] = icmp eq i32 [[AND]], 0
+    // CHECK: ret i1 [[ICMP]]
+    val.trailing_zeros() >= 3
+}
+
+// CHECK-LABEL: @trailing_zeros_gt
+#[no_mangle]
+pub fn trailing_zeros_gt(val: u64) -> bool {
+    // CHECK: %[[AND:.*]] = and i64 %val, 15
+    // CHECK: %[[ICMP:.*]] = icmp eq i64 [[AND]], 0
+    // CHECK: ret i1 [[ICMP]]
+    val.trailing_zeros() > 3
+}