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What's going on here

On branch arm-sve (obsolete, try arm-sve-alt instead if you have a recent enough compiler), the library assume a register width, 256 (--enable-sve256) or 512 (--enable-sve) bits. Commit to pick at the moment for the basic stuff: e16fb9d029368c9b8c4212f660577fce47ccb3ff. This should work with the ARM HPC Compiler version 19.1 or newer, and perhaps GCC 10 and newer (not tested as the branch is obsolete). On that branch, newer commits add 'half-sve' when using --enable-sve, using masking to get 256-bits SIMD from a 512 bits register - this require ARM HPC Compiler version 19.3 or newer, like arm-sve-alt below.

On branch arm-sve-alt masking is always used. --enable-sve creates codelets for 128, 256, 512, 1024 & 2048 bits SIMD. They are only used if the hardware has a width equal or larger than the codelet. As you need the Arm C Language Extension for SVE, this requires ARM HPC Compiler version 19.3 or newer (earlier version have a minor bug triggered by this code), or GCC 10 or newer.

Branch riscv-v adds support for the RISC-V cycle counter (for RV64 & RV32) and some basic support for a draft of the 'V' extension using built-ins functions - for which you need the EPI (European Processor Initiative) version of LLVM. The source drop of the EPI LLVM for revision 0.8 of the V extension can be found here: https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8 (see https://lists.riscv.org/g/tech-vector-ext/message/24 for more details).

Acknowledgements

This work has partly been done as part of the European Processor Initiative project.

The European Processor Initiative (EPI) (FPA: 800928) has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement EPI-SGA1: 826647