Question about the Siamese architecture

[slchenchn]

Hi, first, thanks for presenting such a nice paper!
After reading your paper, I still can't understand the Siamese architecture. As circled out in the figure above, the input2 branch has the maxpooling and upsampling layers between the encoder and decoder, why doesn't the input1 branch have? Have you tested the performance of the architecture whose input1 branch has the maxpooling and upsampling layers?