{"payload":{"header_redesign_enabled":false,"results":[{"id":"497660825","archived":false,"color":"#b2b7f8","followers":10,"has_funding_file":false,"hl_name":"infini8-13/riscv-ms-soc","hl_trunc_description":"A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":497660825,"name":"riscv-ms-soc","owner_id":54203063,"owner_login":"infini8-13","updated_at":"2022-05-31T17:02:34.212Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","risc-v","mixed-signal","system-on-chip","pll","tl-verilog"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":44,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ainfini8-13%252Friscv-ms-soc%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/infini8-13/riscv-ms-soc/star":{"post":"mzLGhnq0MPZJVp8JHvDNs1w3G8cgRg-o_igRzU542IlMGtpKuNjk1gA0Tzfp3wDy4ZxJ5hpvylMYNbVrOAof5g"},"/infini8-13/riscv-ms-soc/unstar":{"post":"yr0J4AvOmic_utc3r-ZeqbsTrY9ehNIcViGbt96sFzF1qxLQQK4KjBPXf4swe0g-K6ZwrMeYpjt2DeQr6dlDlA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"kY3EBL-9vF0q1ZfEoyoxCAPV1tmALBbV_WvjPAX7a1yPAj7jjE9iERgRlbSOUf9hxvog3FKq6EaMNKjHqz3duA"}}},"title":"Repository search results"}