From 9108d4120461f5c79bb76adea4d47e9e214250f4 Mon Sep 17 00:00:00 2001 From: Gonzalo Larumbe Date: Wed, 10 Jan 2024 00:29:27 +0100 Subject: [PATCH] Update test-hdl ref --- misc/notes.org | 4 +++- test-hdl | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/misc/notes.org b/misc/notes.org index 932dedc..c21cb05 100644 --- a/misc/notes.org +++ b/misc/notes.org @@ -365,7 +365,7 @@ DANGER: Still very inefficient, removed funcall in ** TODO Dev: Check ox-hugo to generate blog with short tutorial ** TODO Dev: Rebase/rewrite tree-sitter-verilog ** TODO Pending before release 0.5.0 -*** TODO Dev: vhdl-ts-mode: 'symbols in regexp-opts +*** TODO Dev: vhdl-ext: enable hideshow by default, similar to verilog-ext *** TODO Dev: verilog-ext - [-] Check functionality: last 1 checked was navigation (still the fix for the define-key-map), continue on template - [X] navigation: all except `verilog-ext-forward-word', `verilog-ext-backward-word' and `verilog-ext-jump-to-parent-module' @@ -393,6 +393,8 @@ the proper one depending on if verilog-mode or verilog-ts-mode - Use tree-sitter parsing to get the ports, their type, and their names and save them in some variable - Use this variable to generate the instantiation +*** DONE Dev: vhdl-ts-mode: 'symbols in regexp-opts +CLOSED: [2024-01-10 Wed 00:28] *** DONE Dev: vhdl-ext CLOSED: [2023-12-22 Fri 14:08] - [X] Missing vhdl-ts-mode integration: diff --git a/test-hdl b/test-hdl index 087bdac..2b1148f 160000 --- a/test-hdl +++ b/test-hdl @@ -1 +1 @@ -Subproject commit 087bdac9f4c62564646adc171243e371986219e6 +Subproject commit 2b1148f83cc37ac55a485c40c1a3db24853448c1