From 35df0164c890056b56f920ac3fdce5a593131cde Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Wed, 19 Jul 2023 14:41:48 +0200 Subject: [PATCH 01/13] manually adapted https://github.com/esl-epfl/cv32e40px/commit/3e410390566c8951574c1b8083387437e715a94d --- rtl/cv32e40p_core.sv | 47 +++++++- rtl/cv32e40p_ex_stage.sv | 37 +++--- rtl/cv32e40p_x_disp.sv | 236 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 306 insertions(+), 14 deletions(-) create mode 100644 rtl/cv32e40p_x_disp.sv diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv index 528ac1c8f..89e048f0e 100644 --- a/rtl/cv32e40p_core.sv +++ b/rtl/cv32e40p_core.sv @@ -37,7 +37,8 @@ module cv32e40p_core parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication lane pipeline registers number parameter FPU_OTHERS_LAT = 0, // Floating-Point COMParison/CONVersion lanes pipeline registers number parameter ZFINX = 0, // Float-in-General Purpose registers - parameter NUM_MHPMCOUNTERS = 1 + parameter NUM_MHPMCOUNTERS = 1, + parameter COREV_X_IF = 0 ) ( // Clock and Reset input logic clk_i, @@ -83,6 +84,30 @@ module cv32e40p_core input logic [ 31:0] apu_result_i, input logic [APU_NUSFLAGS_CPU-1:0] apu_flags_i, + + // X-Interface + // X-Request Channel + output logic x_valid_o, + input logic x_ready_i, + output logic [ 2:0][31:0] x_rs_o, + output logic [ 2:0] x_rs_valid_o, + output logic x_rd_clean_o, + input logic x_accept_i, + input logic x_is_mem_op_i, + input logic x_writeback_i, + // X-Response Channel + input logic x_rvalid_i, + output logic x_rready_o, + input logic x_rd_i, + input logic [31:0] x_data_i, + input logic x_dualwb_i, // Moritz: not handled yet + input logic x_type_i, // Moritz: not handled yet + input logic x_error_i, // Moritz: not handled yet + // XMem-Request Channel + + // XMem-Response Channel + + // Interrupt inputs input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts output logic irq_ack_o, @@ -630,6 +655,19 @@ module cv32e40p_core .apu_perf_dep_o (perf_apu_dep), .apu_busy_i (apu_busy), + // X-Interface + .x_valid_o (x_valid_o), + .x_ready_i (x_ready_i), + .x_rs_o (x_rs_o), + .x_rs_valid_o (x_rs_valid_o), + .x_rd_clean_o (x_rd_clean_o), + .x_accept_i (x_accept_i), + .x_is_mem_op_i (x_is_mem_op_i), + .x_writeback_i (x_writeback_i), + .x_rvalid_i (x_rvalid_i), + .x_rd_i (x_rd_i), + + // CSR ID/EX .csr_access_ex_o (csr_access_ex), .csr_op_ex_o (csr_op_ex), @@ -814,6 +852,13 @@ module cv32e40p_core .apu_rvalid_i (apu_rvalid_i), .apu_result_i (apu_result_i), + // X-Interface + .x_rvalid_i(1'b0), + // .x_rvalid_i ( x_rvalid_i ), + .x_rd_i (x_rd_i), + .x_data_i (x_data_i), + + .lsu_en_i (data_req_ex), .lsu_rdata_i(lsu_rdata), diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40p_ex_stage.sv index 6b58a8425..d0291af5d 100644 --- a/rtl/cv32e40p_ex_stage.sv +++ b/rtl/cv32e40p_ex_stage.sv @@ -94,6 +94,11 @@ module cv32e40p_ex_stage input logic [1:0] apu_write_regs_valid_i, output logic apu_write_dep_o, + // X-Interface + input logic x_rvalid_i, + input logic x_rd_i, + input logic [31:0] x_data_i, + output logic apu_perf_type_o, output logic apu_perf_cont_o, output logic apu_perf_wb_o, @@ -183,21 +188,27 @@ module cv32e40p_ex_stage regfile_alu_we_fw_o = '0; wb_contention = 1'b0; - // APU single cycle operations, and multicycle operations (>2cycles) are written back on ALU port - if (apu_valid & (apu_singlecycle | apu_multicycle)) begin + if (x_rvalid_i) begin regfile_alu_we_fw_o = 1'b1; - regfile_alu_waddr_fw_o = apu_waddr; - regfile_alu_wdata_fw_o = apu_result; - - if (regfile_alu_we_i & ~apu_en_i) begin - wb_contention = 1'b1; - end + regfile_alu_waddr_fw_o = x_rd_i; + regfile_alu_wdata_fw_o = x_data_i; end else begin - regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i; // private fpu incomplete? - regfile_alu_waddr_fw_o = regfile_alu_waddr_i; - if (alu_en_i) regfile_alu_wdata_fw_o = alu_result; - if (mult_en_i) regfile_alu_wdata_fw_o = mult_result; - if (csr_access_i) regfile_alu_wdata_fw_o = csr_rdata_i; + // APU single cycle operations, and multicycle operations (>2cycles) are written back on ALU port + if (apu_valid & (apu_singlecycle | apu_multicycle)) begin + regfile_alu_we_fw_o = 1'b1; + regfile_alu_waddr_fw_o = apu_waddr; + regfile_alu_wdata_fw_o = apu_result; + + if (regfile_alu_we_i & ~apu_en_i) begin + wb_contention = 1'b1; + end + end else begin + regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i; // private fpu incomplete? + regfile_alu_waddr_fw_o = regfile_alu_waddr_i; + if (alu_en_i) regfile_alu_wdata_fw_o = alu_result; + if (mult_en_i) regfile_alu_wdata_fw_o = mult_result; + if (csr_access_i) regfile_alu_wdata_fw_o = csr_rdata_i; + end end end diff --git a/rtl/cv32e40p_x_disp.sv b/rtl/cv32e40p_x_disp.sv new file mode 100644 index 000000000..e7059b5c4 --- /dev/null +++ b/rtl/cv32e40p_x_disp.sv @@ -0,0 +1,236 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Moritz Imfeld - moimfeld@student.ethz.ch // +// // +// Design Name: x-interface dispatcher // +// Project Name: cv32e40p // +// Language: SystemVerilog // +// // +// Description: Dispatcher for sending instructions to the x-interface. // +// // +//////////////////////////////////////////////////////////////////////////////// + +module cv32e40p_x_disp + import cv32e40p_core_v_xif_pkg::*; +( + // clock and reset + input logic clk_i, + input logic rst_ni, + + // compressed interface + output logic [3:0] x_compressed_id_o, + // issue interface + output logic x_issue_valid_o, + input logic x_issue_ready_i, + input logic x_issue_resp_accept_i, + input logic x_issue_resp_writeback_i, + input logic x_issue_resp_loadstore_i, // unused + output logic [2:0] x_issue_req_rs_valid_o, + output logic [3:0] x_issue_req_id_o, + output logic [1:0] x_issue_req_mode_o, + output logic x_issue_req_ecs_valid, + + // commit interface + output logic x_commit_valid_o, + output logic [3:0] x_commit_id_o, + output logic x_commit_commit_kill, // hardwired to 0 + + // memory (request/response) interface + input logic x_mem_valid_i, + output logic x_mem_ready_o, + input logic [1:0] x_mem_req_mode_i, // unused + input logic x_mem_req_spec_i, // unused + input logic x_mem_req_last_i, // unused + output logic x_mem_resp_exc_o, // hardwired to 0 + output logic [5:0] x_mem_resp_exccode_o, // hardwired to 0 + output logic x_mem_resp_dbg_o, // hardwired to 0 + + // memory result interface + output logic x_mem_result_valid_o, + output logic x_mem_result_err_o, // hardwired to 0 + + // result interface + input logic x_result_valid_i, + output logic x_result_ready_o, // hardwired to 1 + input logic [4:0] x_result_rd_i, + input logic x_result_we_i, + + // scoreboard, dependency check, stall, forwarding + input logic [4:0] waddr_id_i, + input logic [4:0] waddr_ex_i, + input logic [4:0] waddr_wb_i, + input logic we_ex_i, + input logic we_wb_i, + input logic [4:0] mem_instr_waddr_ex_i, + input logic mem_instr_we_ex_i, + input logic [2:0] regs_used_i, + input logic branch_or_jump_i, + input logic instr_valid_i, + input logic [2:0][4:0] x_rs_addr_i, + output logic [2:0] x_ex_fwd_o, + output logic [2:0] x_wb_fwd_o, + + // memory request core-internal status signals + output logic x_mem_data_req_o, + input logic x_mem_instr_wb_i, + input logic wb_ready_i, + + // additional status signals + output logic x_stall_o, + output logic x_illegal_insn_o, + input logic x_illegal_insn_dec_i, + input logic id_ready_i, + input logic ex_valid_i, + input logic ex_ready_i, + input cv32e40p_pkg::PrivLvl_t current_priv_lvl_i, + input logic data_req_dec_i +); + + // scoreboard, id and satus signals + logic [31:0] scoreboard_q, scoreboard_d; + logic [3:0] id_q, id_d; + logic [3:0] instr_offloaded_q, instr_offloaded_d; + logic [3:0] mem_counter_q, mem_counter_d; + logic dep; + logic outstanding_mem; + logic x_if_not_ready; + logic x_if_memory_instr; + logic illegal_forwarding_prevention; + + // issue interface + assign x_issue_valid_o = x_illegal_insn_dec_i & ~branch_or_jump_i & ~instr_offloaded_q & instr_valid_i & ~illegal_forwarding_prevention; + assign x_issue_req_id_o = id_q; + assign x_issue_req_rs_valid_o[0] = (~scoreboard_q[x_rs_addr_i[0]] | x_ex_fwd_o[0] | x_wb_fwd_o[0]) + & ~(x_rs_addr_i[0] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[0] == waddr_wb_i & ~ex_valid_i); + assign x_issue_req_rs_valid_o[1] = (~scoreboard_q[x_rs_addr_i[1]] | x_ex_fwd_o[1] | x_wb_fwd_o[1]) + & ~(x_rs_addr_i[1] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[1] == waddr_wb_i & ~ex_valid_i); + assign x_issue_req_rs_valid_o[2] = (~scoreboard_q[x_rs_addr_i[2]] | x_ex_fwd_o[2] | x_wb_fwd_o[2]) + & ~(x_rs_addr_i[2] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[2] == waddr_wb_i & ~ex_valid_i); + assign x_issue_req_ecs_valid = 1'b1; // extension context status is not implemented in cv32e40p + + // commit interface + assign x_commit_valid_o = x_issue_valid_o; + assign x_commit_id_o = id_q; + assign x_commit_commit_kill = 1'b0; + + // memory (req/resp) interface + assign x_mem_ready_o = ex_ready_i; + assign x_mem_resp_exc_o = 1'b0; + assign x_mem_resp_exccode_o = '0; + assign x_mem_resp_dbg_o = 1'b0; + + // memory result channel + assign x_mem_result_valid_o = x_mem_instr_wb_i & wb_ready_i; + assign x_mem_result_err_o = 1'b0; + + // result channel + assign x_result_ready_o = 1'b1; + + // core internal memory request signal + assign x_mem_data_req_o = x_mem_valid_i & x_mem_ready_o; + + // core stall signal + assign x_stall_o = dep | outstanding_mem | x_if_not_ready | x_if_memory_instr | illegal_forwarding_prevention; + assign dep = ~x_illegal_insn_o & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0])) + | (regs_used_i[1] & scoreboard_q[x_rs_addr_i[1]] & (x_result_rd_i != x_rs_addr_i[1])) + | (regs_used_i[2] & scoreboard_q[x_rs_addr_i[2]] & (x_result_rd_i != x_rs_addr_i[2]))); + assign outstanding_mem = data_req_dec_i & (mem_counter_q != '0); + assign x_if_memory_instr = x_mem_data_req_o & ~(x_issue_valid_o & x_issue_ready_i); + assign x_if_not_ready = x_issue_valid_o & ~x_issue_ready_i; + + assign illegal_forwarding_prevention = x_result_valid_i & (x_ex_fwd_o[0] | x_ex_fwd_o[1] | x_ex_fwd_o[2]); + + // forwarding + assign x_ex_fwd_o[0] = x_rs_addr_i[0] == waddr_ex_i & we_ex_i & ex_valid_i; + assign x_ex_fwd_o[1] = x_rs_addr_i[1] == waddr_ex_i & we_ex_i & ex_valid_i; + assign x_ex_fwd_o[2] = x_rs_addr_i[2] == waddr_ex_i & we_ex_i & ex_valid_i; + assign x_wb_fwd_o[0] = x_rs_addr_i[0] == waddr_wb_i & we_wb_i & ex_valid_i; + assign x_wb_fwd_o[1] = x_rs_addr_i[1] == waddr_wb_i & we_wb_i & ex_valid_i; + assign x_wb_fwd_o[2] = x_rs_addr_i[2] == waddr_wb_i & we_wb_i & ex_valid_i; + + // id generation + assign x_compressed_id_o = id_d; + always_comb begin + id_d = id_q; + if (x_issue_valid_o & x_issue_ready_i) begin + id_d = id_q + 4'b0001; + end + end + + // assign operation mode according to PrivLvl_t + always_comb begin + x_issue_req_mode_o = 2'b11; + case (current_priv_lvl_i) + cv32e40p_pkg::PRIV_LVL_M: x_issue_req_mode_o = 2'b11; + cv32e40p_pkg::PRIV_LVL_H: x_issue_req_mode_o = 2'b10; + cv32e40p_pkg::PRIV_LVL_S: x_issue_req_mode_o = 2'b01; + cv32e40p_pkg::PRIV_LVL_U: x_issue_req_mode_o = 2'b00; + default: x_issue_req_mode_o = 2'b11; + endcase + end + + // scoreboard update + always_comb begin + scoreboard_d = scoreboard_q; + if (x_issue_resp_writeback_i & x_issue_valid_o & x_issue_ready_i + & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & x_result_rd_i)) begin + scoreboard_d[waddr_id_i] = 1'b1; + end + if (x_result_valid_i & x_result_we_i) begin + scoreboard_d[x_result_rd_i] = 1'b0; + end + end + + // status signal that indicates if an instruction has already been offloaded + always_comb begin + instr_offloaded_d = instr_offloaded_q; + if (id_ready_i) begin + instr_offloaded_d = 1'b0; + end else if (x_issue_valid_o & x_issue_ready_i) begin + instr_offloaded_d = 1'b1; + end + end + + // illegal instruction assertion + always_comb begin + x_illegal_insn_o = 1'b0; + if (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_accept_i) begin + x_illegal_insn_o = 1'b1; + end + end + + // scoreboard and status signal register + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + scoreboard_q <= '0; + instr_offloaded_q <= 1'b0; + id_q <= '0; + mem_counter_q <= '0; + end else begin + scoreboard_q <= scoreboard_d; + instr_offloaded_q <= instr_offloaded_d; + id_q <= id_d; + mem_counter_q <= mem_counter_d; + end + end + + + always_comb begin + mem_counter_d = mem_counter_q; + if ((x_issue_valid_o & x_issue_ready_i & x_issue_resp_loadstore_i) & ~(x_mem_valid_i & x_mem_ready_o) ) begin + mem_counter_d = mem_counter_q + 4'b0001; + end else if (~(x_issue_valid_o & x_issue_ready_i & x_issue_resp_loadstore_i) & (x_mem_valid_i & x_mem_ready_o)) begin + mem_counter_d = mem_counter_q - 4'b0001; + end + end + +endmodule : cv32e40p_x_disp From 203b66730b6319d3bc31bd02634c85ef8434531a Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Wed, 19 Jul 2023 17:07:22 +0200 Subject: [PATCH 02/13] manually adapted 9f03a9321b7373799674940bb8ef2a5fd1bfb759 --- rtl/cv32e40p_controller.sv | 17 +- rtl/cv32e40p_core.sv | 135 ++++++++---- rtl/cv32e40p_ex_stage.sv | 51 ++++- rtl/cv32e40p_id_stage.sv | 279 ++++++++++++++++++++++--- rtl/cv32e40p_if_stage.sv | 41 +++- rtl/cv32e40p_top.sv | 36 +++- rtl/include/cv32e40p_core_v_xif_pkg.sv | 96 +++++++++ 7 files changed, 563 insertions(+), 92 deletions(-) create mode 100644 rtl/include/cv32e40p_core_v_xif_pkg.sv diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40p_controller.sv index 56cce6281..672e3e12b 100644 --- a/rtl/cv32e40p_controller.sv +++ b/rtl/cv32e40p_controller.sv @@ -46,7 +46,8 @@ module cv32e40p_controller import cv32e40p_pkg::*; // decoder related signals output logic deassert_we_o, // deassert write enable for next instruction - input logic illegal_insn_i, // decoder encountered an invalid instruction + input logic illegal_insn_i, // xif confirmed the invalid instruction + input logic illegal_insn_dec_i, // decoder encountered an invalid instruction input logic ecall_insn_i, // decoder encountered an ecall instruction input logic mret_insn_i, // decoder encountered an mret instruction input logic uret_insn_i, // decoder encountered an uret instruction @@ -527,13 +528,13 @@ module cv32e40p_controller import cv32e40p_pkg::*; is_hwlp_illegal = is_hwlp_body & (jump_in_dec || branch_in_id_dec || mret_insn_i || uret_insn_i || dret_insn_i || is_compressed_i || fencei_insn_i || wfi_active); - if(illegal_insn_i || is_hwlp_illegal) begin - - halt_if_o = 1'b1; - halt_id_o = 1'b0; - ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE; - illegal_insn_n = 1'b1; - + if(illegal_insn_dec_i || is_hwlp_illegal) begin + if(illegal_insn_i) begin + halt_if_o = 1'b1; + halt_id_o = 1'b0; + ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE; + illegal_insn_n = 1'b1; + end end else begin //decoding block diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv index 89e048f0e..9bc0fef4d 100644 --- a/rtl/cv32e40p_core.sv +++ b/rtl/cv32e40p_core.sv @@ -30,15 +30,16 @@ module cv32e40p_core import cv32e40p_apu_core_pkg::*; + import cv32e40p_core_v_xif_pkg::*; #( + parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) parameter FPU = 0, // Floating Point Unit (interfaced via APU interface) parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication lane pipeline registers number parameter FPU_OTHERS_LAT = 0, // Floating-Point COMParison/CONVersion lanes pipeline registers number parameter ZFINX = 0, // Float-in-General Purpose registers - parameter NUM_MHPMCOUNTERS = 1, - parameter COREV_X_IF = 0 + parameter NUM_MHPMCOUNTERS = 1 ) ( // Clock and Reset input logic clk_i, @@ -85,27 +86,37 @@ module cv32e40p_core input logic [APU_NUSFLAGS_CPU-1:0] apu_flags_i, - // X-Interface - // X-Request Channel - output logic x_valid_o, - input logic x_ready_i, - output logic [ 2:0][31:0] x_rs_o, - output logic [ 2:0] x_rs_valid_o, - output logic x_rd_clean_o, - input logic x_accept_i, - input logic x_is_mem_op_i, - input logic x_writeback_i, - // X-Response Channel - input logic x_rvalid_i, - output logic x_rready_o, - input logic x_rd_i, - input logic [31:0] x_data_i, - input logic x_dualwb_i, // Moritz: not handled yet - input logic x_type_i, // Moritz: not handled yet - input logic x_error_i, // Moritz: not handled yet - // XMem-Request Channel - - // XMem-Response Channel + // CORE-V-XIF + // Compressed interface + output logic x_compressed_valid_o, + input logic x_compressed_ready_i, + output x_compressed_req_t x_compressed_req_o, + input x_compressed_resp_t x_compressed_resp_i, + + // Issue Interface + output logic x_issue_valid_o, + input logic x_issue_ready_i, + output x_issue_req_t x_issue_req_o, + input x_issue_resp_t x_issue_resp_i, + + // Commit Interface + output logic x_commit_valid_o, + output x_commit_t x_commit_o, + + // Memory request/response Interface + input logic x_mem_valid_i, + output logic x_mem_ready_o, + input x_mem_req_t x_mem_req_i, + output x_mem_resp_t x_mem_resp_o, + + // Memory Result Interface + output logic x_mem_result_valid_o, + output x_mem_result_t x_mem_result_o, + + // Result Interface + input logic x_result_valid_i, + output logic x_result_ready_o, + input x_result_t x_result_i, // Interrupt inputs @@ -247,6 +258,14 @@ module cv32e40p_core logic perf_apu_dep; logic perf_apu_wb; + // X-Interface + logic [ 3:0] x_compressed_id; + logic x_result_valid_assigned; + logic x_mem_instr; + logic [ 3:0] x_mem_id_ex; + logic x_mem_instr_wb; + logic [31:0] result_fw_to_x; + // Register Write Control logic [ 5:0] regfile_waddr_ex; logic regfile_we_ex; @@ -475,6 +494,14 @@ module cv32e40p_core .instr_err_i (1'b0), // Bus error (not used yet) .instr_err_pmp_i(instr_err_pmp), // PMP error + + // X-IF + .x_compressed_valid_o (x_compressed_valid_o), + .x_compressed_ready_i (x_compressed_ready_i), + .x_compressed_req_o (x_compressed_req_o), + .x_compressed_resp_i (x_compressed_resp_i), + .x_compressed_id_i (x_compressed_id), + // outputs to ID stage .instr_valid_id_o (instr_valid_id), .instr_rdata_id_o (instr_rdata_id), @@ -531,6 +558,7 @@ module cv32e40p_core // // ///////////////////////////////////////////////// cv32e40p_id_stage #( + .COREV_X_IF (COREV_X_IF), .COREV_PULP (COREV_PULP), .COREV_CLUSTER (COREV_CLUSTER), .N_HWLP (N_HWLP), @@ -655,18 +683,40 @@ module cv32e40p_core .apu_perf_dep_o (perf_apu_dep), .apu_busy_i (apu_busy), - // X-Interface - .x_valid_o (x_valid_o), - .x_ready_i (x_ready_i), - .x_rs_o (x_rs_o), - .x_rs_valid_o (x_rs_valid_o), - .x_rd_clean_o (x_rd_clean_o), - .x_accept_i (x_accept_i), - .x_is_mem_op_i (x_is_mem_op_i), - .x_writeback_i (x_writeback_i), - .x_rvalid_i (x_rvalid_i), - .x_rd_i (x_rd_i), - + // CORE-V-XIF + // Compressed Interface + .x_compressed_id_o (x_compressed_id), + + // Issue Interface + .x_issue_valid_o (x_issue_valid_o), + .x_issue_ready_i (x_issue_ready_i), + .x_issue_req_o (x_issue_req_o), + .x_issue_resp_i (x_issue_resp_i), + + // Commit Interface + .x_commit_valid_o (x_commit_valid_o), + .x_commit_o (x_commit_o), + + // Memory request/response Interface + .x_mem_valid_i (x_mem_valid_i), + .x_mem_ready_o (x_mem_ready_o), + .x_mem_req_i (x_mem_req_i), + .x_mem_resp_o (x_mem_resp_o), + + // Memory Result Interface + .x_mem_result_valid_o (x_mem_result_valid_o), + .x_mem_result_err_o (x_mem_result_o.err), + + // Result Interface + .x_result_valid_i (x_result_valid_i), + .x_result_ready_o (x_result_ready_o), + .x_result_i (x_result_i), + .x_result_valid_assigned_o (x_result_valid_assigned), + + .x_mem_instr_ex_o(x_mem_instr), + .x_mem_id_ex_o (x_mem_id_ex), + .x_mem_instr_wb_i(x_mem_instr_wb), + .result_fw_to_x_i(result_fw_to_x), // CSR ID/EX .csr_access_ex_o (csr_access_ex), @@ -853,11 +903,16 @@ module cv32e40p_core .apu_result_i (apu_result_i), // X-Interface - .x_rvalid_i(1'b0), - // .x_rvalid_i ( x_rvalid_i ), - .x_rd_i (x_rd_i), - .x_data_i (x_data_i), - + .x_result_valid_assigned_i (x_result_valid_assigned), + .x_result_rd_i (x_result_i.rd), + .x_result_data_i (x_result_i.data), + .x_result_we_i (x_result_i.we), + .x_mem_instr_i (x_mem_instr), + .x_mem_id_ex_i (x_mem_id_ex), + .x_mem_result_rdata_o (x_mem_result_o.rdata), + .x_mem_instr_wb_o (x_mem_instr_wb), + .x_mem_result_id_o (x_mem_result_o.id), + .result_fw_to_x_o (result_fw_to_x), .lsu_en_i (data_req_ex), .lsu_rdata_i(lsu_rdata), diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40p_ex_stage.sv index d0291af5d..bd4128017 100644 --- a/rtl/cv32e40p_ex_stage.sv +++ b/rtl/cv32e40p_ex_stage.sv @@ -32,6 +32,7 @@ module cv32e40p_ex_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*; + import cv32e40p_core_v_xif_pkg::*; #( parameter FPU = 0, parameter APU_NARGS_CPU = 3, @@ -95,9 +96,17 @@ module cv32e40p_ex_stage output logic apu_write_dep_o, // X-Interface - input logic x_rvalid_i, - input logic x_rd_i, - input logic [31:0] x_data_i, + input logic x_result_valid_assigned_i, + input logic [ 4:0] x_result_rd_i, + input logic [31:0] x_result_data_i, + input logic x_result_we_i, + input logic x_mem_instr_i, + input logic [ 3:0] x_mem_id_ex_i, + output logic [31:0] x_mem_result_rdata_o, + output logic x_mem_instr_wb_o, + output logic [ 3:0] x_mem_result_id_o, + output logic [31:0] result_fw_to_x_o, + output logic apu_perf_type_o, output logic apu_perf_cont_o, @@ -187,27 +196,39 @@ module cv32e40p_ex_stage regfile_alu_waddr_fw_o = '0; regfile_alu_we_fw_o = '0; wb_contention = 1'b0; - - if (x_rvalid_i) begin + result_fw_to_x_o = '0; + if (x_result_valid_assigned_i & x_result_we_i & (x_result_rd_i != 5'b00000)) begin regfile_alu_we_fw_o = 1'b1; - regfile_alu_waddr_fw_o = x_rd_i; - regfile_alu_wdata_fw_o = x_data_i; + regfile_alu_waddr_fw_o = {1'b0, x_result_rd_i}; + regfile_alu_wdata_fw_o = x_result_data_i; + if (regfile_alu_we_i) begin + wb_contention = 1'b1; + end end else begin // APU single cycle operations, and multicycle operations (>2cycles) are written back on ALU port if (apu_valid & (apu_singlecycle | apu_multicycle)) begin regfile_alu_we_fw_o = 1'b1; regfile_alu_waddr_fw_o = apu_waddr; regfile_alu_wdata_fw_o = apu_result; - + result_fw_to_x_o = apu_result; if (regfile_alu_we_i & ~apu_en_i) begin wb_contention = 1'b1; end end else begin regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i; // private fpu incomplete? regfile_alu_waddr_fw_o = regfile_alu_waddr_i; - if (alu_en_i) regfile_alu_wdata_fw_o = alu_result; - if (mult_en_i) regfile_alu_wdata_fw_o = mult_result; - if (csr_access_i) regfile_alu_wdata_fw_o = csr_rdata_i; + if (alu_en_i) begin + regfile_alu_wdata_fw_o = alu_result; + result_fw_to_x_o = alu_result; + end + if (mult_en_i) begin + regfile_alu_wdata_fw_o = mult_result; + result_fw_to_x_o = mult_result; + end + if (csr_access_i) begin + regfile_alu_wdata_fw_o = csr_rdata_i; + result_fw_to_x_o = csr_rdata_i; + end end end end @@ -232,6 +253,9 @@ module cv32e40p_ex_stage end end + // X-Interface writeback + assign x_mem_result_rdata_o = lsu_rdata_i; + // branch handling assign branch_decision_o = alu_cmp_result; assign jump_target_o = alu_operand_c_i; @@ -402,10 +426,14 @@ module cv32e40p_ex_stage if (~rst_n) begin regfile_waddr_lsu <= '0; regfile_we_lsu <= 1'b0; + x_mem_instr_wb_o <= 1'b0; + x_mem_result_id_o <= '0; end else begin if (ex_valid_o) // wb_ready_i is implied begin regfile_we_lsu <= regfile_we_i & ~lsu_err_i; + x_mem_instr_wb_o <= x_mem_instr_i; + x_mem_result_id_o <= x_mem_id_ex_i; if (regfile_we_i & ~lsu_err_i) begin regfile_waddr_lsu <= regfile_waddr_i; end @@ -413,6 +441,7 @@ module cv32e40p_ex_stage // we are ready for a new instruction, but there is none available, // so we just flush the current one out of the pipe regfile_we_lsu <= 1'b0; + x_mem_instr_wb_o <= 1'b0; end end end diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40p_id_stage.sv index 0f54e31eb..27bc35ad4 100644 --- a/rtl/cv32e40p_id_stage.sv +++ b/rtl/cv32e40p_id_stage.sv @@ -31,6 +31,7 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*; #( + parameter COREV_X_IF = 0, parameter COREV_PULP = 1, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) parameter COREV_CLUSTER = 0, parameter N_HWLP = 2, @@ -155,6 +156,42 @@ module cv32e40p_id_stage input logic fs_off_i, input logic [C_RM-1:0] frm_i, + // CORE-V-XIF + // Compressed Interface + output logic [3:0] x_compressed_id_o, + + // Issue Interface + output logic x_issue_valid_o, + input logic x_issue_ready_i, + output x_issue_req_t x_issue_req_o, + input x_issue_resp_t x_issue_resp_i, + + // Commit Interface + output logic x_commit_valid_o, + output x_commit_t x_commit_o, + + // Memory request/response Interface + input logic x_mem_valid_i, + output logic x_mem_ready_o, + input x_mem_req_t x_mem_req_i, + output x_mem_resp_t x_mem_resp_o, + + // Memory Result Interface + output logic x_mem_result_valid_o, + output logic x_mem_result_err_o, + + // Core internal xif memory signals + output logic x_mem_instr_ex_o, + output logic [3:0] x_mem_id_ex_o, + input logic x_mem_instr_wb_i, + input logic [31:0] result_fw_to_x_i, + + // Result Interface + input logic x_result_valid_i, + output logic x_result_ready_o, + input x_result_t x_result_i, + output logic x_result_valid_assigned_o, + // CSR ID/EX output logic csr_access_ex_o, output csr_opcode_e csr_op_ex_o, @@ -281,9 +318,9 @@ module cv32e40p_id_stage logic fencei_insn_dec; - logic rega_used_dec; - logic regb_used_dec; - logic regc_used_dec; + logic rega_used; + logic regb_used; + logic regc_used; logic branch_taken_ex; logic [ 1:0] ctrl_transfer_insn_in_id; @@ -388,6 +425,19 @@ module cv32e40p_id_stage logic apu_stall; logic [2:0] fp_rnd_mode; + // X-Interface + logic illegal_insn; + logic [4:0] waddr_id; + logic [4:0] waddr_ex; + logic [4:0] waddr_wb; + logic [2:0] regs_used; + logic x_stall; + logic [2:0][4:0] x_rs_addr; + logic x_mem_data_req; + logic x_mem_valid; + logic [2:0] x_ex_fwd; + logic [2:0] x_wb_fwd; + // Register Write Control logic regfile_we_id; logic regfile_alu_waddr_mux_sel; @@ -518,12 +568,16 @@ module cv32e40p_id_stage // register C mux always_comb begin - unique case (regc_mux) - REGC_ZERO: regfile_addr_rc_id = '0; - REGC_RD: regfile_addr_rc_id = {regfile_fp_c, instr[REG_D_MSB:REG_D_LSB]}; - REGC_S1: regfile_addr_rc_id = {regfile_fp_c, instr[REG_S1_MSB:REG_S1_LSB]}; - REGC_S4: regfile_addr_rc_id = {regfile_fp_c, instr[REG_S4_MSB:REG_S4_LSB]}; - endcase + if (!illegal_insn_dec) begin + unique case (regc_mux) + REGC_ZERO: regfile_addr_rc_id = '0; + REGC_RD: regfile_addr_rc_id = {regfile_fp_c, instr[REG_D_MSB:REG_D_LSB]}; + REGC_S1: regfile_addr_rc_id = {regfile_fp_c, instr[REG_S1_MSB:REG_S1_LSB]}; + REGC_S4: regfile_addr_rc_id = {regfile_fp_c, instr[REG_S4_MSB:REG_S4_LSB]}; + endcase + end else begin + regfile_addr_rc_id = {regfile_fp_c, instr[REG_S4_MSB:REG_S4_LSB]}; + end end //--------------------------------------------------------------------------- @@ -536,15 +590,15 @@ module cv32e40p_id_stage assign regfile_alu_waddr_id = regfile_alu_waddr_mux_sel ? regfile_waddr_id : regfile_addr_ra_id; // Forwarding control signals - assign reg_d_ex_is_reg_a_id = (regfile_waddr_ex_o == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0); - assign reg_d_ex_is_reg_b_id = (regfile_waddr_ex_o == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0); - assign reg_d_ex_is_reg_c_id = (regfile_waddr_ex_o == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0); - assign reg_d_wb_is_reg_a_id = (regfile_waddr_wb_i == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0); - assign reg_d_wb_is_reg_b_id = (regfile_waddr_wb_i == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0); - assign reg_d_wb_is_reg_c_id = (regfile_waddr_wb_i == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0); - assign reg_d_alu_is_reg_a_id = (regfile_alu_waddr_fw_i == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0); - assign reg_d_alu_is_reg_b_id = (regfile_alu_waddr_fw_i == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0); - assign reg_d_alu_is_reg_c_id = (regfile_alu_waddr_fw_i == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0); + assign reg_d_ex_is_reg_a_id = (regfile_waddr_ex_o == regfile_addr_ra_id) && (rega_used == 1'b1) && (regfile_addr_ra_id != '0); + assign reg_d_ex_is_reg_b_id = (regfile_waddr_ex_o == regfile_addr_rb_id) && (regb_used == 1'b1) && (regfile_addr_rb_id != '0); + assign reg_d_ex_is_reg_c_id = (regfile_waddr_ex_o == regfile_addr_rc_id) && (regc_used == 1'b1) && (regfile_addr_rc_id != '0); + assign reg_d_wb_is_reg_a_id = (regfile_waddr_wb_i == regfile_addr_ra_id) && (rega_used == 1'b1) && (regfile_addr_ra_id != '0); + assign reg_d_wb_is_reg_b_id = (regfile_waddr_wb_i == regfile_addr_rb_id) && (regb_used == 1'b1) && (regfile_addr_rb_id != '0); + assign reg_d_wb_is_reg_c_id = (regfile_waddr_wb_i == regfile_addr_rc_id) && (regc_used == 1'b1) && (regfile_addr_rc_id != '0); + assign reg_d_alu_is_reg_a_id = (regfile_alu_waddr_fw_i == regfile_addr_ra_id) && (rega_used == 1'b1) && (regfile_addr_ra_id != '0); + assign reg_d_alu_is_reg_b_id = (regfile_alu_waddr_fw_i == regfile_addr_rb_id) && (regb_used == 1'b1) && (regfile_addr_rb_id != '0); + assign reg_d_alu_is_reg_c_id = (regfile_alu_waddr_fw_i == regfile_addr_rc_id) && (regc_used == 1'b1) && (regfile_addr_rc_id != '0); // kill instruction in the IF/ID stage by setting the instr_valid_id control @@ -933,6 +987,152 @@ module cv32e40p_id_stage .we_b_i (regfile_alu_we_fw_i) ); + logic [1:0] x_mem_data_type_id; + + generate + if (COREV_X_IF) begin : gen_x_disp + //////////////////////////////////////// + // __ __ ____ ___ ____ ____ // + // \ \/ / | _ \_ _/ ___|| _ \ // + // \ /_____| | | | |\___ \| |_) | // + // / \_____| |_| | | ___) | __/ // + // /_/\_\ |____/___|____/|_| // + // // + //////////////////////////////////////// + + cv32e40p_x_disp x_disp_i ( + // clock and reset + .clk_i (clk), + .rst_ni(rst_n), + + // compressed interface + .x_compressed_id_o (x_compressed_id_o), + + // issue interface + .x_issue_valid_o (x_issue_valid_o), + .x_issue_ready_i (x_issue_ready_i), + .x_issue_resp_writeback_i(x_issue_resp_i.writeback), + .x_issue_resp_accept_i (x_issue_resp_i.accept), + .x_issue_resp_loadstore_i(x_issue_resp_i.loadstore), + .x_issue_req_rs_valid_o (x_issue_req_o.rs_valid), + .x_issue_req_id_o (x_issue_req_o.id), + .x_issue_req_mode_o (x_issue_req_o.mode), + .x_issue_req_ecs_valid (x_issue_req_o.ecs_valid), + + // commit interface + .x_commit_valid_o (x_commit_valid_o), + .x_commit_id_o (x_commit_o.id), + .x_commit_commit_kill(x_commit_o.commit_kill), + + // memory (request/response) interface + .x_mem_valid_i (x_mem_valid_i), + .x_mem_ready_o (x_mem_ready_o), + .x_mem_req_mode_i (x_mem_req_i.mode), + .x_mem_req_spec_i (x_mem_req_i.spec), + .x_mem_req_last_i (x_mem_req_i.last), + .x_mem_resp_exc_o (x_mem_resp_o.exc), + .x_mem_resp_exccode_o(x_mem_resp_o.exccode), + .x_mem_resp_dbg_o (x_mem_resp_o.dbg), + + // memory result interface + .x_mem_result_valid_o(x_mem_result_valid_o), + .x_mem_result_err_o (x_mem_result_err_o), + + // result interface + .x_result_valid_i(x_result_valid_i), + .x_result_ready_o(x_result_ready_o), + .x_result_rd_i (x_result_i.rd), + .x_result_we_i (x_result_i.we), + + // scoreboard, dependency check, stall, forwarding + .waddr_id_i (waddr_id), + .waddr_ex_i (waddr_ex), + .waddr_wb_i (waddr_wb), + .we_ex_i (regfile_alu_we_ex_o), + .we_wb_i (regfile_we_wb_i), + .mem_instr_waddr_ex_i(regfile_waddr_ex_o[4:0]), + .mem_instr_we_ex_i (regfile_we_ex_o), + .regs_used_i (regs_used), + .branch_or_jump_i (pc_set_o), + .instr_valid_i (instr_valid_i), + .x_rs_addr_i (x_rs_addr), + .x_ex_fwd_o (x_ex_fwd), + .x_wb_fwd_o (x_wb_fwd), + + // memory request core-internal status signals + .x_mem_data_req_o(x_mem_data_req), + .x_mem_instr_wb_i(x_mem_instr_wb_i), + .wb_ready_i (wb_ready_i), + + // additional status signals + .x_stall_o (x_stall), + .x_illegal_insn_o (x_illegal_insn), + .x_illegal_insn_dec_i(illegal_insn_dec), + .id_ready_i (id_ready_o), + .ex_valid_i (ex_valid_i), + .ex_ready_i (ex_ready_i), + .current_priv_lvl_i (current_priv_lvl_i), + .data_req_dec_i (data_req_id) + ); + + + // illegal instruction signal + assign illegal_insn = x_illegal_insn; + + // x-dispatcher signal assignments + assign x_issue_req_o.instr = instr; + assign x_issue_req_o.ecs = '0; + assign x_rs_addr[0] = regfile_addr_ra_id[4:0]; + assign x_rs_addr[1] = regfile_addr_rb_id[4:0]; + assign x_rs_addr[2] = regfile_addr_rc_id[4:0]; + assign waddr_id = instr[REG_D_MSB:REG_D_LSB]; + assign waddr_ex = regfile_alu_waddr_ex_o[4:0]; + assign waddr_wb = regfile_waddr_wb_i[4:0]; + assign regs_used = {regc_used, regb_used, rega_used}; + assign x_result_valid_assigned_o = x_result_valid_i; + assign x_mem_valid = x_mem_valid_i; + + // xif integer souce operand selection + for (genvar i = 0; i < 3; i++) begin : xif_operand_assignment + always_comb begin + if (i == 0) begin + x_issue_req_o.rs[i] = regfile_data_ra_id; + end else if (i == 1) begin + x_issue_req_o.rs[i] = regfile_data_rb_id; + end else begin + x_issue_req_o.rs[i] = regfile_data_rc_id; + end + if (x_ex_fwd[i]) begin + x_issue_req_o.rs[i] = result_fw_to_x_i; + end else if (x_wb_fwd[i]) begin + x_issue_req_o.rs[i] = regfile_wdata_wb_i; + end + end + end + // LSU signal assignment/MUX + always_comb begin + x_mem_data_type_id = 2'b00; + case (x_mem_req_i.size) + 2'b00: x_mem_data_type_id = 2'b10; // SB + 2'b01: x_mem_data_type_id = 2'b01; // SH + 2'b10: x_mem_data_type_id = 2'b00; // SW + endcase + end + + + end else begin : gen_no_x_disp + + // default illegal instruction assignment + assign illegal_insn = illegal_insn_dec; + + // default assignment for x-interface control signals + assign x_stall = 1'b0; + assign x_result_valid_assigned_o = 1'b0; + assign x_mem_valid = 1'b0; + assign x_issue_valid_o = 1'b0; + + end : gen_no_x_disp + endgenerate /////////////////////////////////////////////// // ____ _____ ____ ___ ____ _____ ____ // @@ -975,9 +1175,9 @@ module cv32e40p_id_stage .fencei_insn_o(fencei_insn_dec), - .rega_used_o(rega_used_dec), - .regb_used_o(regb_used_dec), - .regc_used_o(regc_used_dec), + .rega_used_o(rega_used), + .regb_used_o(regb_used), + .regc_used_o(regc_used), .reg_fp_a_o(regfile_fp_a), .reg_fp_b_o(regfile_fp_b), @@ -1098,7 +1298,8 @@ module cv32e40p_id_stage // decoder related signals .deassert_we_o(deassert_we), - .illegal_insn_i(illegal_insn_dec), + .illegal_insn_i(illegal_insn), + .illegal_insn_dec_i(illegal_insn_dec), .ecall_insn_i (ecall_insn_dec), .mret_insn_i (mret_insn_dec), .uret_insn_i (uret_insn_dec), @@ -1434,6 +1635,8 @@ module cv32e40p_id_stage apu_flags_ex_o <= '0; apu_waddr_ex_o <= '0; + x_mem_instr_ex_o <= 1'b0; + x_mem_id_ex_o <= '0; regfile_waddr_ex_o <= 6'b0; regfile_we_ex_o <= 1'b0; @@ -1555,6 +1758,9 @@ module cv32e40p_id_stage data_load_event_ex_o <= 1'b0; end + x_mem_instr_ex_o <= 1'b0; + x_mem_id_ex_o <= 1'b0; + data_misaligned_ex_o <= 1'b0; if ((ctrl_transfer_insn_in_id == BRANCH_COND) || data_req_id) begin @@ -1572,10 +1778,6 @@ module cv32e40p_id_stage csr_op_ex_o <= CSR_OP_READ; - data_req_ex_o <= 1'b0; - - data_load_event_ex_o <= 1'b0; - data_misaligned_ex_o <= 1'b0; branch_in_ex_o <= 1'b0; @@ -1588,6 +1790,25 @@ module cv32e40p_id_stage alu_en_ex_o <= 1'b1; + if (x_mem_valid) begin + data_req_ex_o <= x_mem_valid; + data_we_ex_o <= x_mem_req_i.we; + data_type_ex_o <= x_mem_data_type_id; + data_sign_ext_ex_o <= 2'b00; + data_reg_offset_ex_o <= 2'b00; + data_load_event_ex_o <= 1'b1; + prepost_useincr_ex_o <= 1'b0; + alu_operand_a_ex_o <= x_mem_req_i.addr; + alu_operand_c_ex_o <= x_mem_req_i.wdata; + x_mem_instr_ex_o <= x_mem_data_req; + x_mem_id_ex_o <= x_mem_req_i.id; + end else begin + x_mem_instr_ex_o <= 1'b0; + x_mem_id_ex_o <= 1'b0; + data_req_ex_o <= 1'b0; + data_load_event_ex_o <= 1'b0; + end + end else if (csr_access_ex_o) begin //In the EX stage there was a CSR access, to avoid multiple //writes to the RF, disable regfile_alu_we_ex_o. @@ -1602,7 +1823,7 @@ module cv32e40p_id_stage // Illegal/ebreak/ecall are never counted as retired instructions. Note that actually issued instructions // are being counted; the manner in which CSR instructions access the performance counters guarantees // that this count will correspond to the retired isntructions count. - assign minstret = id_valid_o && is_decoding_o && !(illegal_insn_dec || ebrk_insn_dec || ecall_insn_dec); + assign minstret = id_valid_o && is_decoding_o && !(illegal_insn || ebrk_insn_dec || ecall_insn_dec); always_ff @(posedge clk, negedge rst_n) begin if (rst_n == 1'b0) begin @@ -1642,8 +1863,8 @@ module cv32e40p_id_stage end // stall control - assign id_ready_o = ((~misaligned_stall) & (~jr_stall) & (~load_stall) & (~apu_stall) & (~csr_apu_stall) & ex_ready_i); - assign id_valid_o = (~halt_id) & id_ready_o; + assign id_ready_o = ((~misaligned_stall) & (~jr_stall) & (~load_stall) & (~apu_stall) & (~csr_apu_stall) & (~x_stall) & ex_ready_i); + assign id_valid_o = (~halt_id) & ~x_mem_valid & id_ready_o; assign halt_if_o = halt_if; diff --git a/rtl/cv32e40p_if_stage.sv b/rtl/cv32e40p_if_stage.sv index 23fd14f5f..c3020af10 100644 --- a/rtl/cv32e40p_if_stage.sv +++ b/rtl/cv32e40p_if_stage.sv @@ -26,6 +26,7 @@ //////////////////////////////////////////////////////////////////////////////// module cv32e40p_if_stage #( + parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) parameter PULP_OBI = 0, // Legacy PULP OBI behavior parameter PULP_SECURE = 0, @@ -58,6 +59,13 @@ module cv32e40p_if_stage #( input logic instr_err_i, // External bus error (validity defined by instr_rvalid_i) (not used yet) input logic instr_err_pmp_i, // PMP error (validity defined by instr_gnt_i) + // compressed x-interface + output logic x_compressed_valid_o, + input logic x_compressed_ready_i, + output cv32e40p_core_v_xif_pkg::x_compressed_req_t x_compressed_req_o, + input cv32e40p_core_v_xif_pkg::x_compressed_resp_t x_compressed_resp_i, + input logic [3:0] x_compressed_id_i, + // Output of IF Pipeline stage output logic instr_valid_id_o, // instruction in IF/ID pipeline is valid output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding @@ -122,11 +130,12 @@ module cv32e40p_if_stage #( logic instr_valid; logic illegal_c_insn; + logic illegal_c_insn_dec; logic [31:0] instr_aligned; logic [31:0] instr_decompressed; + logic [31:0] instr_decompressed_dec; logic instr_compressed_int; - // exception PC selection mux always_comb begin : EXC_PC_MUX unique case (trap_addr_mux_i) @@ -275,11 +284,37 @@ module cv32e40p_if_stage #( .ZFINX(ZFINX) ) compressed_decoder_i ( .instr_i (instr_aligned), - .instr_o (instr_decompressed), + .instr_o (instr_decompressed_dec), .is_compressed_o(instr_compressed_int), - .illegal_instr_o(illegal_c_insn) + .illegal_instr_o(illegal_c_insn_dec) ); + + generate + if (COREV_X_IF) begin + assign x_compressed_valid_o = illegal_c_insn_dec; + assign x_compressed_req_o.instr = instr_aligned; + assign x_compressed_req_o.mode = 2'b00; // Machine Mode + assign x_compressed_req_o.id = x_compressed_id_i; + + always_comb begin + instr_decompressed = instr_decompressed_dec; + illegal_c_insn = illegal_c_insn_dec; + if (x_compressed_valid_o & x_compressed_ready_i & x_compressed_resp_i.accept) begin + instr_decompressed = x_compressed_resp_i.instr; + illegal_c_insn = 1'b0; + end else if (x_compressed_valid_o & x_compressed_ready_i & ~x_compressed_resp_i.accept) begin + instr_decompressed = x_compressed_resp_i.instr; + illegal_c_insn = 1'b1; + end + end + end else begin + assign instr_decompressed = instr_decompressed_dec; + assign illegal_c_insn = illegal_c_insn_dec; + end + endgenerate + + //---------------------------------------------------------------------------- // Assertions //---------------------------------------------------------------------------- diff --git a/rtl/cv32e40p_top.sv b/rtl/cv32e40p_top.sv index 7ddd2d5a2..1b5c9c829 100644 --- a/rtl/cv32e40p_top.sv +++ b/rtl/cv32e40p_top.sv @@ -11,7 +11,8 @@ // Top file instantiating a CV32E40P core and an optional FPU // Contributor: Davide Schiavone -module cv32e40p_top #( +module cv32e40p_top import cv32e40p_core_v_xif_pkg::*; #( + parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) parameter FPU = 0, // Floating Point Unit (interfaced via APU interface) @@ -51,6 +52,38 @@ module cv32e40p_top #( output logic [31:0] data_wdata_o, input logic [31:0] data_rdata_i, + // CORE-V-XIF + // Compressed interface + output logic x_compressed_valid_o, + input logic x_compressed_ready_i, + output x_compressed_req_t x_compressed_req_o, + input x_compressed_resp_t x_compressed_resp_i, + + // Issue Interface + output logic x_issue_valid_o, + input logic x_issue_ready_i, + output x_issue_req_t x_issue_req_o, + input x_issue_resp_t x_issue_resp_i, + + // Commit Interface + output logic x_commit_valid_o, + output x_commit_t x_commit_o, + + // Memory request/response Interface + input logic x_mem_valid_i, + output logic x_mem_ready_o, + input x_mem_req_t x_mem_req_i, + output x_mem_resp_t x_mem_resp_o, + + // Memory Result Interface + output logic x_mem_result_valid_o, + output x_mem_result_t x_mem_result_o, + + // Result Interface + input logic x_result_valid_i, + output logic x_result_ready_o, + input x_result_t x_result_i, + // Interrupt inputs input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts output logic irq_ack_o, @@ -84,6 +117,7 @@ module cv32e40p_top #( // Instantiate the Core cv32e40p_core #( + .COREV_X_IF (COREV_X_IF), .COREV_PULP (COREV_PULP), .COREV_CLUSTER (COREV_CLUSTER), .FPU (FPU), diff --git a/rtl/include/cv32e40p_core_v_xif_pkg.sv b/rtl/include/cv32e40p_core_v_xif_pkg.sv new file mode 100644 index 000000000..71cd8804c --- /dev/null +++ b/rtl/include/cv32e40p_core_v_xif_pkg.sv @@ -0,0 +1,96 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// CORE-V-XIF Package +// Contributor: Moritz Imfeld + +package cv32e40p_core_v_xif_pkg; + + // cv-x-if parameters + parameter int X_NUM_RS = 3; + parameter int X_ID_WIDTH = 4; + parameter int X_MEM_WIDTH = 32; + parameter int X_RFR_WIDTH = 32; + parameter int X_RFW_WIDTH = 32; + parameter logic [31:0] X_MISA = '0; + parameter logic [ 1:0] X_ECS_XS = '0; + + // interface structs + typedef struct packed { + logic [ 15:0] instr; + logic [ 1:0] mode; + logic [X_ID_WIDTH-1:0] id; + } x_compressed_req_t; + + typedef struct packed { + logic [31:0] instr; + logic accept; + } x_compressed_resp_t; + + typedef struct packed { + logic [ 31:0] instr; + logic [ 1:0] mode; + logic [ X_ID_WIDTH-1:0] id; + logic [ X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs; + logic [ X_NUM_RS-1:0] rs_valid; + logic [ 5:0] ecs; + logic ecs_valid; + } x_issue_req_t; + + typedef struct packed { + logic accept; + logic writeback; + logic float; + logic dualwrite; + logic dualread; + logic loadstore; + logic exc; + } x_issue_resp_t; + + typedef struct packed { + logic [X_ID_WIDTH-1:0] id; + logic commit_kill; + } x_commit_t; + + typedef struct packed { + logic [ X_ID_WIDTH-1:0] id; + logic [ 31:0] addr; + logic [ 1:0] mode; + logic [ 1:0] size; + logic we; + logic [X_MEM_WIDTH-1:0] wdata; + logic last; + logic spec; + } x_mem_req_t; + + typedef struct packed { + logic exc; + logic [5:0] exccode; + logic dbg; + } x_mem_resp_t; + + typedef struct packed { + logic [ X_ID_WIDTH-1:0] id; + logic [X_MEM_WIDTH-1:0] rdata; + logic err; + logic dbg; + } x_mem_result_t; + + typedef struct packed { + logic [ X_ID_WIDTH-1:0] id; + logic [ X_RFW_WIDTH-1:0] data; + logic [ 4:0] rd; + logic we; + logic [ 2:0] ecswe; + logic [ 5:0] ecsdata; + logic exc; + logic [ 5:0] exccode; + } x_result_t; +endpackage From 6a7ce2cc6eb2fd8985d4a39f40c8d25c4d8e6781 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 20 Jul 2023 08:35:59 +0200 Subject: [PATCH 03/13] update cadence lec --- scripts/lec/cadence_conformal/check_lec.tcl | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/scripts/lec/cadence_conformal/check_lec.tcl b/scripts/lec/cadence_conformal/check_lec.tcl index d8b918a36..2ff64380c 100644 --- a/scripts/lec/cadence_conformal/check_lec.tcl +++ b/scripts/lec/cadence_conformal/check_lec.tcl @@ -27,6 +27,19 @@ add_ignored_outputs apu_operands_o* -Both add_ignored_outputs apu_op_o* -Both add_ignored_outputs apu_flags_o* -Both +// core_v_xif signals +add ignored outputs x_compressed_valid_o -Both +add ignored outputs x_compressed_req_o* -Both +add ignored outputs x_issue_valid_o -Both +add ignored outputs x_issue_req_o* -Both +add ignored outputs x_commit_valid_o -Both +add ignored outputs x_commit_o* -Both +add ignored outputs x_mem_ready_o -Both +add ignored outputs x_mem_resp_o* -Both +add ignored outputs x_mem_result_valid_o -Both +add ignored outputs x_mem_result_o* -Both +add ignored outputs x_result_ready_o -Both + write_hier_compare_dofile hier_compare_r2r.do -constraint -replace run_hier_compare hier_compare_r2r.do -ROOT_module cv32e40p_core cv32e40p_core From 75df7475d5db74f9aa77155f87794a24ca354c0e Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 20 Jul 2023 09:19:36 +0200 Subject: [PATCH 04/13] renaming files to cv32e40px --- cv32e40p_fpu_manifest.flist | 93 ------------------- cv32e40p_manifest.flist | 63 ------------- ...32e40p_aligner.sv => cv32e40px_aligner.sv} | 0 rtl/{cv32e40p_alu.sv => cv32e40px_alu.sv} | 0 ...32e40p_alu_div.sv => cv32e40px_alu_div.sv} | 0 ...e40p_apu_disp.sv => cv32e40px_apu_disp.sv} | 0 ...der.sv => cv32e40px_compressed_decoder.sv} | 0 ..._controller.sv => cv32e40px_controller.sv} | 0 rtl/{cv32e40p_core.sv => cv32e40px_core.sv} | 0 ...registers.sv => cv32e40px_cs_registers.sv} | 0 ...32e40p_decoder.sv => cv32e40px_decoder.sv} | 0 ...e40p_ex_stage.sv => cv32e40px_ex_stage.sv} | 0 ...cv32e40p_ff_one.sv => cv32e40px_ff_one.sv} | 0 rtl/{cv32e40p_fifo.sv => cv32e40px_fifo.sv} | 0 ..._fp_wrapper.sv => cv32e40px_fp_wrapper.sv} | 0 ...wloop_regs.sv => cv32e40px_hwloop_regs.sv} | 0 ...e40p_id_stage.sv => cv32e40px_id_stage.sv} | 0 ...e40p_if_stage.sv => cv32e40px_if_stage.sv} | 0 ...troller.sv => cv32e40px_int_controller.sv} | 0 ...e_unit.sv => cv32e40px_load_store_unit.sv} | 0 rtl/{cv32e40p_mult.sv => cv32e40px_mult.sv} | 0 ...nterface.sv => cv32e40px_obi_interface.sv} | 0 ...cv32e40p_popcnt.sv => cv32e40px_popcnt.sv} | 0 ...buffer.sv => cv32e40px_prefetch_buffer.sv} | 0 ...er.sv => cv32e40px_prefetch_controller.sv} | 0 ...le_ff.sv => cv32e40px_register_file_ff.sv} | 0 ...ch.sv => cv32e40px_register_file_latch.sv} | 0 ..._sleep_unit.sv => cv32e40px_sleep_unit.sv} | 0 rtl/{cv32e40p_top.sv => cv32e40px_top.sv} | 0 ...cv32e40p_x_disp.sv => cv32e40px_x_disp.sv} | 0 ..._core_pkg.sv => cv32e40px_apu_core_pkg.sv} | 0 ...xif_pkg.sv => cv32e40px_core_v_xif_pkg.sv} | 0 ...32e40p_fpu_pkg.sv => cv32e40px_fpu_pkg.sv} | 0 .../{cv32e40p_pkg.sv => cv32e40px_pkg.sv} | 0 34 files changed, 156 deletions(-) delete mode 100644 cv32e40p_fpu_manifest.flist delete mode 100644 cv32e40p_manifest.flist rename rtl/{cv32e40p_aligner.sv => cv32e40px_aligner.sv} (100%) rename rtl/{cv32e40p_alu.sv => cv32e40px_alu.sv} (100%) rename rtl/{cv32e40p_alu_div.sv => cv32e40px_alu_div.sv} (100%) rename rtl/{cv32e40p_apu_disp.sv => cv32e40px_apu_disp.sv} (100%) rename rtl/{cv32e40p_compressed_decoder.sv => cv32e40px_compressed_decoder.sv} (100%) rename rtl/{cv32e40p_controller.sv => cv32e40px_controller.sv} (100%) rename rtl/{cv32e40p_core.sv => cv32e40px_core.sv} (100%) rename rtl/{cv32e40p_cs_registers.sv => cv32e40px_cs_registers.sv} (100%) rename rtl/{cv32e40p_decoder.sv => cv32e40px_decoder.sv} (100%) rename rtl/{cv32e40p_ex_stage.sv => cv32e40px_ex_stage.sv} (100%) rename rtl/{cv32e40p_ff_one.sv => cv32e40px_ff_one.sv} (100%) rename rtl/{cv32e40p_fifo.sv => cv32e40px_fifo.sv} (100%) rename rtl/{cv32e40p_fp_wrapper.sv => cv32e40px_fp_wrapper.sv} (100%) rename rtl/{cv32e40p_hwloop_regs.sv => cv32e40px_hwloop_regs.sv} (100%) rename rtl/{cv32e40p_id_stage.sv => cv32e40px_id_stage.sv} (100%) rename rtl/{cv32e40p_if_stage.sv => cv32e40px_if_stage.sv} (100%) rename rtl/{cv32e40p_int_controller.sv => cv32e40px_int_controller.sv} (100%) rename rtl/{cv32e40p_load_store_unit.sv => cv32e40px_load_store_unit.sv} (100%) rename rtl/{cv32e40p_mult.sv => cv32e40px_mult.sv} (100%) rename rtl/{cv32e40p_obi_interface.sv => cv32e40px_obi_interface.sv} (100%) rename rtl/{cv32e40p_popcnt.sv => cv32e40px_popcnt.sv} (100%) rename rtl/{cv32e40p_prefetch_buffer.sv => cv32e40px_prefetch_buffer.sv} (100%) rename rtl/{cv32e40p_prefetch_controller.sv => cv32e40px_prefetch_controller.sv} (100%) rename rtl/{cv32e40p_register_file_ff.sv => cv32e40px_register_file_ff.sv} (100%) rename rtl/{cv32e40p_register_file_latch.sv => cv32e40px_register_file_latch.sv} (100%) rename rtl/{cv32e40p_sleep_unit.sv => cv32e40px_sleep_unit.sv} (100%) rename rtl/{cv32e40p_top.sv => cv32e40px_top.sv} (100%) rename rtl/{cv32e40p_x_disp.sv => cv32e40px_x_disp.sv} (100%) rename rtl/include/{cv32e40p_apu_core_pkg.sv => cv32e40px_apu_core_pkg.sv} (100%) rename rtl/include/{cv32e40p_core_v_xif_pkg.sv => cv32e40px_core_v_xif_pkg.sv} (100%) rename rtl/include/{cv32e40p_fpu_pkg.sv => cv32e40px_fpu_pkg.sv} (100%) rename rtl/include/{cv32e40p_pkg.sv => cv32e40px_pkg.sv} (100%) diff --git a/cv32e40p_fpu_manifest.flist b/cv32e40p_fpu_manifest.flist deleted file mode 100644 index aca8c41b2..000000000 --- a/cv32e40p_fpu_manifest.flist +++ /dev/null @@ -1,93 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Copyright 2020 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -/////////////////////////////////////////////////////////////////////////////// -// -// Manifest for the CV32E40P RTL model. -// - Intended to be used by both synthesis and simulation. -// - Relevent synthesis and simulation scripts/Makefiles must set the shell -// ENV variable DESIGN_RTL_DIR as required. -// -/////////////////////////////////////////////////////////////////////////////// - -+incdir+${DESIGN_RTL_DIR}/include -+incdir+${DESIGN_RTL_DIR}/../bhv -+incdir+${DESIGN_RTL_DIR}/../bhv/include -+incdir+${DESIGN_RTL_DIR}/../sva -+incdir+${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/include - -${DESIGN_RTL_DIR}/include/cv32e40p_apu_core_pkg.sv -${DESIGN_RTL_DIR}/include/cv32e40p_fpu_pkg.sv -${DESIGN_RTL_DIR}/include/cv32e40p_pkg.sv -${DESIGN_RTL_DIR}/cv32e40p_if_stage.sv -${DESIGN_RTL_DIR}/cv32e40p_cs_registers.sv -${DESIGN_RTL_DIR}/cv32e40p_register_file_ff.sv -${DESIGN_RTL_DIR}/cv32e40p_load_store_unit.sv -${DESIGN_RTL_DIR}/cv32e40p_id_stage.sv -${DESIGN_RTL_DIR}/cv32e40p_aligner.sv -${DESIGN_RTL_DIR}/cv32e40p_decoder.sv -${DESIGN_RTL_DIR}/cv32e40p_compressed_decoder.sv -${DESIGN_RTL_DIR}/cv32e40p_fifo.sv -${DESIGN_RTL_DIR}/cv32e40p_prefetch_buffer.sv -${DESIGN_RTL_DIR}/cv32e40p_hwloop_regs.sv -${DESIGN_RTL_DIR}/cv32e40p_mult.sv -${DESIGN_RTL_DIR}/cv32e40p_int_controller.sv -${DESIGN_RTL_DIR}/cv32e40p_ex_stage.sv -${DESIGN_RTL_DIR}/cv32e40p_alu_div.sv -${DESIGN_RTL_DIR}/cv32e40p_alu.sv -${DESIGN_RTL_DIR}/cv32e40p_ff_one.sv -${DESIGN_RTL_DIR}/cv32e40p_popcnt.sv -${DESIGN_RTL_DIR}/cv32e40p_apu_disp.sv -${DESIGN_RTL_DIR}/cv32e40p_controller.sv -${DESIGN_RTL_DIR}/cv32e40p_obi_interface.sv -${DESIGN_RTL_DIR}/cv32e40p_prefetch_controller.sv -${DESIGN_RTL_DIR}/cv32e40p_sleep_unit.sv -${DESIGN_RTL_DIR}/cv32e40p_core.sv - -${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/cf_math_pkg.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/lzc.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_pkg.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_divsqrt_th_32.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_classifier.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_rounding.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_cast_multi.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_fma_multi.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_noncomp.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_opgroup_fmt_slice.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_opgroup_multifmt_slice.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_opgroup_block.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_divsqrt_multi.sv -${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_top.sv -${DESIGN_RTL_DIR}/cv32e40p_fp_wrapper.sv - -${DESIGN_RTL_DIR}/cv32e40p_top.sv - -${DESIGN_RTL_DIR}/../bhv/cv32e40p_sim_clock_gate.sv -${DESIGN_RTL_DIR}/../bhv/include/cv32e40p_tracer_pkg.sv -${DESIGN_RTL_DIR}/../bhv/cv32e40p_tb_wrapper.sv diff --git a/cv32e40p_manifest.flist b/cv32e40p_manifest.flist deleted file mode 100644 index b69ccecd3..000000000 --- a/cv32e40p_manifest.flist +++ /dev/null @@ -1,63 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Copyright 2020 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -/////////////////////////////////////////////////////////////////////////////// -// -// Manifest for the CV32E40P RTL model. -// - Intended to be used by both synthesis and simulation. -// - Relevent synthesis and simulation scripts/Makefiles must set the shell -// ENV variable DESIGN_RTL_DIR as required. -// -/////////////////////////////////////////////////////////////////////////////// - -+incdir+${DESIGN_RTL_DIR}/include -+incdir+${DESIGN_RTL_DIR}/../bhv -+incdir+${DESIGN_RTL_DIR}/../bhv/include -+incdir+${DESIGN_RTL_DIR}/../sva - -${DESIGN_RTL_DIR}/include/cv32e40p_apu_core_pkg.sv -${DESIGN_RTL_DIR}/include/cv32e40p_fpu_pkg.sv -${DESIGN_RTL_DIR}/include/cv32e40p_pkg.sv -${DESIGN_RTL_DIR}/cv32e40p_if_stage.sv -${DESIGN_RTL_DIR}/cv32e40p_cs_registers.sv -${DESIGN_RTL_DIR}/cv32e40p_register_file_ff.sv -${DESIGN_RTL_DIR}/cv32e40p_load_store_unit.sv -${DESIGN_RTL_DIR}/cv32e40p_id_stage.sv -${DESIGN_RTL_DIR}/cv32e40p_aligner.sv -${DESIGN_RTL_DIR}/cv32e40p_decoder.sv -${DESIGN_RTL_DIR}/cv32e40p_compressed_decoder.sv -${DESIGN_RTL_DIR}/cv32e40p_fifo.sv -${DESIGN_RTL_DIR}/cv32e40p_prefetch_buffer.sv -${DESIGN_RTL_DIR}/cv32e40p_hwloop_regs.sv -${DESIGN_RTL_DIR}/cv32e40p_mult.sv -${DESIGN_RTL_DIR}/cv32e40p_int_controller.sv -${DESIGN_RTL_DIR}/cv32e40p_ex_stage.sv -${DESIGN_RTL_DIR}/cv32e40p_alu_div.sv -${DESIGN_RTL_DIR}/cv32e40p_alu.sv -${DESIGN_RTL_DIR}/cv32e40p_ff_one.sv -${DESIGN_RTL_DIR}/cv32e40p_popcnt.sv -${DESIGN_RTL_DIR}/cv32e40p_apu_disp.sv -${DESIGN_RTL_DIR}/cv32e40p_controller.sv -${DESIGN_RTL_DIR}/cv32e40p_obi_interface.sv -${DESIGN_RTL_DIR}/cv32e40p_prefetch_controller.sv -${DESIGN_RTL_DIR}/cv32e40p_sleep_unit.sv -${DESIGN_RTL_DIR}/cv32e40p_core.sv - -${DESIGN_RTL_DIR}/cv32e40p_top.sv - -${DESIGN_RTL_DIR}/../bhv/cv32e40p_sim_clock_gate.sv -${DESIGN_RTL_DIR}/../bhv/include/cv32e40p_tracer_pkg.sv -${DESIGN_RTL_DIR}/../bhv/cv32e40p_tb_wrapper.sv diff --git a/rtl/cv32e40p_aligner.sv b/rtl/cv32e40px_aligner.sv similarity index 100% rename from rtl/cv32e40p_aligner.sv rename to rtl/cv32e40px_aligner.sv diff --git a/rtl/cv32e40p_alu.sv b/rtl/cv32e40px_alu.sv similarity index 100% rename from rtl/cv32e40p_alu.sv rename to rtl/cv32e40px_alu.sv diff --git a/rtl/cv32e40p_alu_div.sv b/rtl/cv32e40px_alu_div.sv similarity index 100% rename from rtl/cv32e40p_alu_div.sv rename to rtl/cv32e40px_alu_div.sv diff --git a/rtl/cv32e40p_apu_disp.sv b/rtl/cv32e40px_apu_disp.sv similarity index 100% rename from rtl/cv32e40p_apu_disp.sv rename to rtl/cv32e40px_apu_disp.sv diff --git a/rtl/cv32e40p_compressed_decoder.sv b/rtl/cv32e40px_compressed_decoder.sv similarity index 100% rename from rtl/cv32e40p_compressed_decoder.sv rename to rtl/cv32e40px_compressed_decoder.sv diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40px_controller.sv similarity index 100% rename from rtl/cv32e40p_controller.sv rename to rtl/cv32e40px_controller.sv diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40px_core.sv similarity index 100% rename from rtl/cv32e40p_core.sv rename to rtl/cv32e40px_core.sv diff --git a/rtl/cv32e40p_cs_registers.sv b/rtl/cv32e40px_cs_registers.sv similarity index 100% rename from rtl/cv32e40p_cs_registers.sv rename to rtl/cv32e40px_cs_registers.sv diff --git a/rtl/cv32e40p_decoder.sv b/rtl/cv32e40px_decoder.sv similarity index 100% rename from rtl/cv32e40p_decoder.sv rename to rtl/cv32e40px_decoder.sv diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40px_ex_stage.sv similarity index 100% rename from rtl/cv32e40p_ex_stage.sv rename to rtl/cv32e40px_ex_stage.sv diff --git a/rtl/cv32e40p_ff_one.sv b/rtl/cv32e40px_ff_one.sv similarity index 100% rename from rtl/cv32e40p_ff_one.sv rename to rtl/cv32e40px_ff_one.sv diff --git a/rtl/cv32e40p_fifo.sv b/rtl/cv32e40px_fifo.sv similarity index 100% rename from rtl/cv32e40p_fifo.sv rename to rtl/cv32e40px_fifo.sv diff --git a/rtl/cv32e40p_fp_wrapper.sv b/rtl/cv32e40px_fp_wrapper.sv similarity index 100% rename from rtl/cv32e40p_fp_wrapper.sv rename to rtl/cv32e40px_fp_wrapper.sv diff --git a/rtl/cv32e40p_hwloop_regs.sv b/rtl/cv32e40px_hwloop_regs.sv similarity index 100% rename from rtl/cv32e40p_hwloop_regs.sv rename to rtl/cv32e40px_hwloop_regs.sv diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40px_id_stage.sv similarity index 100% rename from rtl/cv32e40p_id_stage.sv rename to rtl/cv32e40px_id_stage.sv diff --git a/rtl/cv32e40p_if_stage.sv b/rtl/cv32e40px_if_stage.sv similarity index 100% rename from rtl/cv32e40p_if_stage.sv rename to rtl/cv32e40px_if_stage.sv diff --git a/rtl/cv32e40p_int_controller.sv b/rtl/cv32e40px_int_controller.sv similarity index 100% rename from rtl/cv32e40p_int_controller.sv rename to rtl/cv32e40px_int_controller.sv diff --git a/rtl/cv32e40p_load_store_unit.sv b/rtl/cv32e40px_load_store_unit.sv similarity index 100% rename from rtl/cv32e40p_load_store_unit.sv rename to rtl/cv32e40px_load_store_unit.sv diff --git a/rtl/cv32e40p_mult.sv b/rtl/cv32e40px_mult.sv similarity index 100% rename from rtl/cv32e40p_mult.sv rename to rtl/cv32e40px_mult.sv diff --git a/rtl/cv32e40p_obi_interface.sv b/rtl/cv32e40px_obi_interface.sv similarity index 100% rename from rtl/cv32e40p_obi_interface.sv rename to rtl/cv32e40px_obi_interface.sv diff --git a/rtl/cv32e40p_popcnt.sv b/rtl/cv32e40px_popcnt.sv similarity index 100% rename from rtl/cv32e40p_popcnt.sv rename to rtl/cv32e40px_popcnt.sv diff --git a/rtl/cv32e40p_prefetch_buffer.sv b/rtl/cv32e40px_prefetch_buffer.sv similarity index 100% rename from rtl/cv32e40p_prefetch_buffer.sv rename to rtl/cv32e40px_prefetch_buffer.sv diff --git a/rtl/cv32e40p_prefetch_controller.sv b/rtl/cv32e40px_prefetch_controller.sv similarity index 100% rename from rtl/cv32e40p_prefetch_controller.sv rename to rtl/cv32e40px_prefetch_controller.sv diff --git a/rtl/cv32e40p_register_file_ff.sv b/rtl/cv32e40px_register_file_ff.sv similarity index 100% rename from rtl/cv32e40p_register_file_ff.sv rename to rtl/cv32e40px_register_file_ff.sv diff --git a/rtl/cv32e40p_register_file_latch.sv b/rtl/cv32e40px_register_file_latch.sv similarity index 100% rename from rtl/cv32e40p_register_file_latch.sv rename to rtl/cv32e40px_register_file_latch.sv diff --git a/rtl/cv32e40p_sleep_unit.sv b/rtl/cv32e40px_sleep_unit.sv similarity index 100% rename from rtl/cv32e40p_sleep_unit.sv rename to rtl/cv32e40px_sleep_unit.sv diff --git a/rtl/cv32e40p_top.sv b/rtl/cv32e40px_top.sv similarity index 100% rename from rtl/cv32e40p_top.sv rename to rtl/cv32e40px_top.sv diff --git a/rtl/cv32e40p_x_disp.sv b/rtl/cv32e40px_x_disp.sv similarity index 100% rename from rtl/cv32e40p_x_disp.sv rename to rtl/cv32e40px_x_disp.sv diff --git a/rtl/include/cv32e40p_apu_core_pkg.sv b/rtl/include/cv32e40px_apu_core_pkg.sv similarity index 100% rename from rtl/include/cv32e40p_apu_core_pkg.sv rename to rtl/include/cv32e40px_apu_core_pkg.sv diff --git a/rtl/include/cv32e40p_core_v_xif_pkg.sv b/rtl/include/cv32e40px_core_v_xif_pkg.sv similarity index 100% rename from rtl/include/cv32e40p_core_v_xif_pkg.sv rename to rtl/include/cv32e40px_core_v_xif_pkg.sv diff --git a/rtl/include/cv32e40p_fpu_pkg.sv b/rtl/include/cv32e40px_fpu_pkg.sv similarity index 100% rename from rtl/include/cv32e40p_fpu_pkg.sv rename to rtl/include/cv32e40px_fpu_pkg.sv diff --git a/rtl/include/cv32e40p_pkg.sv b/rtl/include/cv32e40px_pkg.sv similarity index 100% rename from rtl/include/cv32e40p_pkg.sv rename to rtl/include/cv32e40px_pkg.sv From 54e154c6c87ddf837f6248a49e62abb79cf095ec Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 20 Jul 2023 09:23:20 +0200 Subject: [PATCH 05/13] replaced cv32e40p with cv32e40px in module names --- bhv/cv32e40p_tb_wrapper.sv | 508 ------------------ ..._apu_tracer.sv => cv32e40px_apu_tracer.sv} | 8 +- ...e40p_core_log.sv => cv32e40px_core_log.sv} | 12 +- ...tr_trace.svh => cv32e40px_instr_trace.svh} | 0 bhv/{cv32e40p_rvfi.sv => cv32e40px_rvfi.sv} | 10 +- ..._rvfi_trace.sv => cv32e40px_rvfi_trace.sv} | 10 +- ...ck_gate.sv => cv32e40px_sim_clock_gate.sv} | 6 +- bhv/cv32e40px_tb_wrapper.sv | 508 ++++++++++++++++++ ...cv32e40p_tracer.sv => cv32e40px_tracer.sv} | 10 +- ...e40p_rvfi_pkg.sv => cv32e40px_rvfi_pkg.sv} | 6 +- ..._tracer_pkg.sv => cv32e40px_tracer_pkg.sv} | 4 +- rtl/cv32e40px_aligner.sv | 2 +- rtl/cv32e40px_alu.sv | 10 +- rtl/cv32e40px_alu_div.sv | 2 +- rtl/cv32e40px_apu_disp.sv | 2 +- rtl/cv32e40px_compressed_decoder.sv | 4 +- rtl/cv32e40px_controller.sv | 4 +- rtl/cv32e40px_core.sv | 22 +- rtl/cv32e40px_cs_registers.sv | 6 +- rtl/cv32e40px_decoder.sv | 276 +++++----- rtl/cv32e40px_ex_stage.sv | 14 +- rtl/cv32e40px_ff_one.sv | 4 +- rtl/cv32e40px_fifo.sv | 4 +- rtl/cv32e40px_fp_wrapper.sv | 8 +- rtl/cv32e40px_hwloop_regs.sv | 2 +- rtl/cv32e40px_id_stage.sv | 34 +- rtl/cv32e40px_if_stage.sv | 14 +- rtl/cv32e40px_int_controller.sv | 10 +- rtl/cv32e40px_load_store_unit.sv | 8 +- rtl/cv32e40px_mult.sv | 4 +- rtl/cv32e40px_obi_interface.sv | 6 +- rtl/cv32e40px_popcnt.sv | 4 +- rtl/cv32e40px_prefetch_buffer.sv | 16 +- rtl/cv32e40px_prefetch_controller.sv | 8 +- rtl/cv32e40px_register_file_ff.sv | 2 +- rtl/cv32e40px_register_file_latch.sv | 6 +- rtl/cv32e40px_sleep_unit.sv | 24 +- rtl/cv32e40px_top.sv | 10 +- rtl/cv32e40px_x_disp.sv | 20 +- rtl/include/cv32e40px_apu_core_pkg.sv | 4 +- rtl/include/cv32e40px_core_v_xif_pkg.sv | 2 +- rtl/include/cv32e40px_fpu_pkg.sv | 2 +- rtl/include/cv32e40px_pkg.sv | 2 +- 43 files changed, 809 insertions(+), 809 deletions(-) delete mode 100644 bhv/cv32e40p_tb_wrapper.sv rename bhv/{cv32e40p_apu_tracer.sv => cv32e40px_apu_tracer.sv} (92%) rename bhv/{cv32e40p_core_log.sv => cv32e40px_core_log.sv} (87%) rename bhv/{cv32e40p_instr_trace.svh => cv32e40px_instr_trace.svh} (100%) rename bhv/{cv32e40p_rvfi.sv => cv32e40px_rvfi.sv} (99%) rename bhv/{cv32e40p_rvfi_trace.sv => cv32e40px_rvfi_trace.sv} (97%) rename bhv/{cv32e40p_sim_clock_gate.sv => cv32e40px_sim_clock_gate.sv} (88%) create mode 100644 bhv/cv32e40px_tb_wrapper.sv rename bhv/{cv32e40p_tracer.sv => cv32e40px_tracer.sv} (99%) rename bhv/include/{cv32e40p_rvfi_pkg.sv => cv32e40px_rvfi_pkg.sv} (97%) rename bhv/include/{cv32e40p_tracer_pkg.sv => cv32e40px_tracer_pkg.sv} (99%) diff --git a/bhv/cv32e40p_tb_wrapper.sv b/bhv/cv32e40p_tb_wrapper.sv deleted file mode 100644 index 14de3b607..000000000 --- a/bhv/cv32e40p_tb_wrapper.sv +++ /dev/null @@ -1,508 +0,0 @@ -// Copyright (c) 2020 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - -// Wrapper for a cv32e40p, containing cv32e40p_top, and rvfi_tracer -// -// Contributors: Davide Schiavone, OpenHW Group -// Yoann Pruvost, Dolphin Design - -`ifdef CV32E40P_ASSERT_ON -`include "cv32e40p_prefetch_controller_sva.sv" -`endif - -`ifdef CV32E40P_CORE_LOG -`include "cv32e40p_core_log.sv" -`endif - -`ifdef CV32E40P_APU_TRACE -`include "cv32e40p_apu_tracer.sv" -`endif - -`ifdef CV32E40P_TRACE_EXECUTION -`include "cv32e40p_tracer.sv" -`endif - -`ifdef CV32E40P_RVFI -`include "cv32e40p_rvfi.sv" -`endif - -`ifdef CV32E40P_RVFI_TRACE_EXECUTION -`include "cv32e40p_rvfi_trace.sv" -`endif - -module cv32e40p_tb_wrapper - import cv32e40p_pkg::*; -#( - parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) - parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) - parameter FPU = 0, // Floating Point Unit (interfaced via APU interface) - parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number - parameter FPU_OTHERS_LAT = 0, // Floating-Point COMParison/CONVersion computing lanes pipeline registers number - parameter ZFINX = 0, // Float-in-General Purpose registers - parameter NUM_MHPMCOUNTERS = 1 -) ( - // Clock and Reset - input logic clk_i, - input logic rst_ni, - - input logic pulp_clock_en_i, // PULP clock enable (only used if COREV_CLUSTER = 1) - input logic scan_cg_en_i, // Enable all clock gates for testing - - // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static - input logic [31:0] boot_addr_i, - input logic [31:0] mtvec_addr_i, - input logic [31:0] dm_halt_addr_i, - input logic [31:0] hart_id_i, - input logic [31:0] dm_exception_addr_i, - - // Instruction memory interface - output logic instr_req_o, - input logic instr_gnt_i, - input logic instr_rvalid_i, - output logic [31:0] instr_addr_o, - input logic [31:0] instr_rdata_i, - - // Data memory interface - output logic data_req_o, - input logic data_gnt_i, - input logic data_rvalid_i, - output logic data_we_o, - output logic [ 3:0] data_be_o, - output logic [31:0] data_addr_o, - output logic [31:0] data_wdata_o, - input logic [31:0] data_rdata_i, - - // Interrupt inputs - input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts - output logic irq_ack_o, - output logic [ 4:0] irq_id_o, - - // Debug Interface - input logic debug_req_i, - output logic debug_havereset_o, - output logic debug_running_o, - output logic debug_halted_o, - - // CPU Control Signals - input logic fetch_enable_i, - output logic core_sleep_o -); - -`ifdef CV32E40P_ASSERT_ON - - // RTL Assertions - bind cv32e40p_prefetch_controller: - cv32e40p_top_i.core_i.if_stage_i.prefetch_buffer_i.prefetch_controller_i - cv32e40p_prefetch_controller_sva - #( - .DEPTH (DEPTH), - .COREV_PULP (COREV_PULP), - .PULP_OBI (PULP_OBI), - .FIFO_ADDR_DEPTH(FIFO_ADDR_DEPTH) - ) prefetch_controller_sva (.*); - -`endif // CV32E40P_ASSERT_ON - -`ifdef CV32E40P_CORE_LOG - cv32e40p_core_log #( - .COREV_PULP (COREV_PULP), - .COREV_CLUSTER (COREV_CLUSTER), - .FPU (FPU), - .ZFINX (ZFINX), - .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS) - ) core_log_i ( - .clk_i (cv32e40p_top_i.core_i.id_stage_i.clk), - .is_decoding_i (cv32e40p_top_i.core_i.id_stage_i.is_decoding_o), - .illegal_insn_dec_i(cv32e40p_top_i.core_i.id_stage_i.illegal_insn_dec), - .hart_id_i (cv32e40p_top_i.core_i.hart_id_i), - .pc_id_i (cv32e40p_top_i.core_i.pc_id) - ); -`endif // CV32E40P_CORE_LOG - -`ifdef CV32E40P_APU_TRACE - cv32e40p_apu_tracer apu_tracer_i ( - .clk_i (cv32e40p_top_i.core_i.rst_ni), - .rst_n (cv32e40p_top_i.core_i.clk_i), - .hart_id_i (cv32e40p_top_i.core_i.hart_id_i), - .apu_valid_i (cv32e40p_top_i.core_i.ex_stage_i.apu_valid), - .apu_waddr_i (cv32e40p_top_i.core_i.ex_stage_i.apu_waddr), - .apu_result_i(cv32e40p_top_i.core_i.ex_stage_i.apu_result) - ); -`endif - -`ifdef CV32E40P_TRACE_EXECUTION - cv32e40p_tracer #( - .FPU (FPU), - .ZFINX(ZFINX) - ) tracer_i ( - .clk_i(cv32e40p_top_i.core_i.clk_i), // always-running clock for tracing - .rst_n(cv32e40p_top_i.core_i.rst_ni), - - .hart_id_i(cv32e40p_top_i.core_i.hart_id_i), - - .pc (cv32e40p_top_i.core_i.id_stage_i.pc_id_i), - .instr (cv32e40p_top_i.core_i.id_stage_i.instr), - .controller_state_i(cv32e40p_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs), - .compressed (cv32e40p_top_i.core_i.id_stage_i.is_compressed_i), - .id_valid (cv32e40p_top_i.core_i.id_stage_i.id_valid_o), - .is_decoding (cv32e40p_top_i.core_i.id_stage_i.is_decoding_o), - .is_illegal (cv32e40p_top_i.core_i.id_stage_i.illegal_insn_dec), - .trigger_match (cv32e40p_top_i.core_i.id_stage_i.trigger_match_i), - .rs1_value (cv32e40p_top_i.core_i.id_stage_i.operand_a_fw_id), - .rs2_value (cv32e40p_top_i.core_i.id_stage_i.operand_b_fw_id), - .rs3_value (cv32e40p_top_i.core_i.id_stage_i.alu_operand_c), - .rs2_value_vec (cv32e40p_top_i.core_i.id_stage_i.alu_operand_b), - - .rs1_is_fp(cv32e40p_top_i.core_i.id_stage_i.regfile_fp_a), - .rs2_is_fp(cv32e40p_top_i.core_i.id_stage_i.regfile_fp_b), - .rs3_is_fp(cv32e40p_top_i.core_i.id_stage_i.regfile_fp_c), - .rd_is_fp (cv32e40p_top_i.core_i.id_stage_i.regfile_fp_d), - - .ex_valid (cv32e40p_top_i.core_i.ex_valid), - .ex_reg_addr (cv32e40p_top_i.core_i.regfile_alu_waddr_fw), - .ex_reg_we (cv32e40p_top_i.core_i.regfile_alu_we_fw), - .ex_reg_wdata(cv32e40p_top_i.core_i.regfile_alu_wdata_fw), - - .ex_data_addr (cv32e40p_top_i.core_i.data_addr_o), - .ex_data_req (cv32e40p_top_i.core_i.data_req_o), - .ex_data_gnt (cv32e40p_top_i.core_i.data_gnt_i), - .ex_data_we (cv32e40p_top_i.core_i.data_we_o), - .ex_data_wdata (cv32e40p_top_i.core_i.data_wdata_o), - .data_misaligned(cv32e40p_top_i.core_i.data_misaligned), - - .ebrk_insn(cv32e40p_top_i.core_i.id_stage_i.ebrk_insn_dec), - .debug_mode(cv32e40p_top_i.core_i.debug_mode), - .ebrk_force_debug_mode(cv32e40p_top_i.core_i.id_stage_i.controller_i.ebrk_force_debug_mode), - - .wb_bypass(cv32e40p_top_i.core_i.ex_stage_i.branch_in_ex_i), - - .wb_valid (cv32e40p_top_i.core_i.wb_valid), - .wb_reg_addr (cv32e40p_top_i.core_i.regfile_waddr_fw_wb_o), - .wb_reg_we (cv32e40p_top_i.core_i.regfile_we_wb), - .wb_reg_wdata(cv32e40p_top_i.core_i.regfile_wdata), - - .imm_u_type (cv32e40p_top_i.core_i.id_stage_i.imm_u_type), - .imm_uj_type (cv32e40p_top_i.core_i.id_stage_i.imm_uj_type), - .imm_i_type (cv32e40p_top_i.core_i.id_stage_i.imm_i_type), - .imm_iz_type (cv32e40p_top_i.core_i.id_stage_i.imm_iz_type[11:0]), - .imm_z_type (cv32e40p_top_i.core_i.id_stage_i.imm_z_type), - .imm_s_type (cv32e40p_top_i.core_i.id_stage_i.imm_s_type), - .imm_sb_type (cv32e40p_top_i.core_i.id_stage_i.imm_sb_type), - .imm_s2_type (cv32e40p_top_i.core_i.id_stage_i.imm_s2_type), - .imm_s3_type (cv32e40p_top_i.core_i.id_stage_i.imm_s3_type), - .imm_vs_type (cv32e40p_top_i.core_i.id_stage_i.imm_vs_type), - .imm_vu_type (cv32e40p_top_i.core_i.id_stage_i.imm_vu_type), - .imm_shuffle_type (cv32e40p_top_i.core_i.id_stage_i.imm_shuffle_type), - .imm_clip_type (cv32e40p_top_i.core_i.id_stage_i.instr[11:7]), - .apu_en_i (cv32e40p_top_i.apu_req), - .apu_singlecycle_i(cv32e40p_top_i.core_i.ex_stage_i.apu_singlecycle), - .apu_multicycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_multicycle), - .apu_rvalid_i (cv32e40p_top_i.apu_rvalid) - ); -`endif - -`ifdef CV32E40P_RVFI - logic [1:0][31:0] hwlp_start_q; - logic [1:0][31:0] hwlp_end_q; - logic [1:0][31:0] hwlp_counter_q; - logic [1:0][31:0] hwlp_counter_n; - generate - if (COREV_PULP) begin - assign hwlp_start_q = cv32e40p_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_start_q ; - assign hwlp_end_q = cv32e40p_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_end_q; - assign hwlp_counter_q = cv32e40p_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_counter_q; - assign hwlp_counter_n = cv32e40p_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_counter_n; - end else begin - assign hwlp_start_q = '0; - assign hwlp_end_q = '0; - assign hwlp_counter_q = '0; - assign hwlp_counter_n = '0; - end - endgenerate - - cv32e40p_rvfi #( - .FPU (FPU), - .ZFINX(ZFINX) - ) rvfi_i ( - .clk_i (cv32e40p_top_i.core_i.clk_i), - .rst_ni(cv32e40p_top_i.core_i.rst_ni), - - .is_decoding_i (cv32e40p_top_i.core_i.id_stage_i.is_decoding_o), - .is_illegal_i (cv32e40p_top_i.core_i.id_stage_i.illegal_insn_dec), - .trigger_match_i (cv32e40p_top_i.core_i.id_stage_i.trigger_match_i), - .data_misaligned_i(cv32e40p_top_i.core_i.data_misaligned), - .lsu_data_we_ex_i (cv32e40p_top_i.core_i.data_we_ex), - .debug_mode_i (cv32e40p_top_i.core_i.debug_mode), - .debug_cause_i (cv32e40p_top_i.core_i.debug_cause), - //// Instr IF probes //// - .instr_req_i (cv32e40p_top_i.core_i.instr_req_o), - .instr_grant_i (cv32e40p_top_i.core_i.instr_gnt_i), - .instr_rvalid_i (cv32e40p_top_i.core_i.instr_rvalid_i), - .prefetch_req_i (cv32e40p_top_i.core_i.instr_req_int), - .pc_set_i (cv32e40p_top_i.core_i.pc_set), - - .instr_valid_id_i (cv32e40p_top_i.core_i.instr_valid_id), - .instr_rdata_id_i (cv32e40p_top_i.core_i.instr_rdata_id), - .is_fetch_failed_id_i(cv32e40p_top_i.core_i.is_fetch_failed_id), - .instr_req_int_i (cv32e40p_top_i.core_i.instr_req_int), - .clear_instr_valid_i (cv32e40p_top_i.core_i.clear_instr_valid), - //// IF probes //// - .instr_valid_if_i (cv32e40p_top_i.core_i.if_stage_i.instr_valid), - .if_valid_i (cv32e40p_top_i.core_i.if_stage_i.if_valid), - .if_ready_i (cv32e40p_top_i.core_i.if_stage_i.if_ready), - .instr_if_i (cv32e40p_top_i.core_i.if_stage_i.instr_aligned), - .pc_if_i (cv32e40p_top_i.core_i.pc_if), - //// ID probes //// - .pc_id_i (cv32e40p_top_i.core_i.id_stage_i.pc_id_i), - .id_valid_i (cv32e40p_top_i.core_i.id_stage_i.id_valid_o), - .id_ready_i (cv32e40p_top_i.core_i.id_stage_i.id_ready_o), - - .rs1_addr_id_i (cv32e40p_top_i.core_i.id_stage_i.regfile_addr_ra_id), - .rs2_addr_id_i (cv32e40p_top_i.core_i.id_stage_i.regfile_addr_rb_id), - .operand_a_fw_id_i (cv32e40p_top_i.core_i.id_stage_i.operand_a_fw_id), - .operand_b_fw_id_i (cv32e40p_top_i.core_i.id_stage_i.operand_b_fw_id), - // .instr (cv32e40p_top_i.core_i.id_stage_i.instr ), - .is_compressed_id_i(cv32e40p_top_i.core_i.id_stage_i.is_compressed_i), - .ebrk_insn_dec_i (cv32e40p_top_i.core_i.id_stage_i.ebrk_insn_dec), - .csr_cause_i (cv32e40p_top_i.core_i.csr_cause), - .debug_csr_save_i (cv32e40p_top_i.core_i.debug_csr_save), - - // HWLOOP regs - .hwlp_start_q_i (hwlp_start_q), - .hwlp_end_q_i (hwlp_end_q), - .hwlp_counter_q_i(hwlp_counter_q), - .hwlp_counter_n_i(hwlp_counter_n), - - .minstret_i (cv32e40p_top_i.core_i.id_stage_i.minstret), - //// EX probes //// - .ex_valid_i (cv32e40p_top_i.core_i.ex_valid), - .ex_ready_i (cv32e40p_top_i.core_i.ex_ready), - .ex_reg_addr_i (cv32e40p_top_i.core_i.regfile_alu_waddr_fw), - .ex_reg_we_i (cv32e40p_top_i.core_i.regfile_alu_we_fw), - .ex_reg_wdata_i (cv32e40p_top_i.core_i.regfile_alu_wdata_fw), - .apu_en_ex_i (cv32e40p_top_i.core_i.apu_en_ex), - .apu_singlecycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_singlecycle), - .apu_multicycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_multicycle), - .wb_contention_lsu_i(cv32e40p_top_i.core_i.ex_stage_i.wb_contention_lsu), - .wb_contention_i (cv32e40p_top_i.core_i.ex_stage_i.wb_contention), - - // .rf_we_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_we_fw_i), - // .rf_addr_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i), - // .rf_wdata_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i), - - //// WB probes //// - .wb_valid_i(cv32e40p_top_i.core_i.wb_valid), - - //// LSU probes //// - .data_we_ex_i (cv32e40p_top_i.core_i.data_we_ex), - .data_atop_ex_i (cv32e40p_top_i.core_i.data_atop_ex), - .data_type_ex_i (cv32e40p_top_i.core_i.data_type_ex), - .alu_operand_c_ex_i (cv32e40p_top_i.core_i.alu_operand_c_ex), - .data_reg_offset_ex_i(cv32e40p_top_i.core_i.data_reg_offset_ex), - .data_load_event_ex_i(cv32e40p_top_i.core_i.data_load_event_ex), - .data_sign_ext_ex_i (cv32e40p_top_i.core_i.data_sign_ext_ex), - .lsu_rdata_i (cv32e40p_top_i.core_i.lsu_rdata), - .data_req_ex_i (cv32e40p_top_i.core_i.data_req_ex), - .alu_operand_a_ex_i (cv32e40p_top_i.core_i.alu_operand_a_ex), - .alu_operand_b_ex_i (cv32e40p_top_i.core_i.alu_operand_b_ex), - .useincr_addr_ex_i (cv32e40p_top_i.core_i.useincr_addr_ex), - .data_misaligned_ex_i(cv32e40p_top_i.core_i.data_misaligned_ex), - .p_elw_start_i (cv32e40p_top_i.core_i.p_elw_start), - .p_elw_finish_i (cv32e40p_top_i.core_i.p_elw_finish), - .lsu_ready_ex_i (cv32e40p_top_i.core_i.lsu_ready_ex), - .lsu_ready_wb_i (cv32e40p_top_i.core_i.lsu_ready_wb), - - .data_req_pmp_i(cv32e40p_top_i.core_i.data_req_pmp), - .data_gnt_pmp_i(cv32e40p_top_i.core_i.data_gnt_pmp), - .data_rvalid_i(cv32e40p_top_i.core_i.data_rvalid_i), - .data_err_pmp_i(cv32e40p_top_i.core_i.data_err_pmp), - .data_addr_pmp_i(cv32e40p_top_i.core_i.data_addr_pmp), - .data_we_i(cv32e40p_top_i.core_i.data_we_o), - .data_atop_i(cv32e40p_top_i.core_i.data_atop_o), - .data_be_i(cv32e40p_top_i.core_i.data_be_o), - .data_wdata_i(cv32e40p_top_i.core_i.data_wdata_o), - .data_rdata_i(cv32e40p_top_i.core_i.data_rdata_i), - // Register writes - .rf_we_wb_i(cv32e40p_top_i.core_i.id_stage_i.regfile_we_wb_i), - .rf_addr_wb_i(cv32e40p_top_i.core_i.id_stage_i.regfile_waddr_wb_i), - .rf_wdata_wb_i(cv32e40p_top_i.core_i.id_stage_i.regfile_wdata_wb_i), - - // APU - .apu_req_i (cv32e40p_top_i.core_i.apu_req_o), - .apu_gnt_i (cv32e40p_top_i.core_i.apu_gnt_i), - .apu_rvalid_i(cv32e40p_top_i.core_i.apu_rvalid_i), - - // Controller FSM probes - .ctrl_fsm_cs_i(cv32e40p_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs), - .pc_mux_i (cv32e40p_top_i.core_i.id_stage_i.controller_i.pc_mux_o), - .exc_pc_mux_i (cv32e40p_top_i.core_i.id_stage_i.controller_i.exc_pc_mux_o), - - //CSR - .csr_addr_i (cv32e40p_top_i.core_i.cs_registers_i.csr_addr_i), - .csr_we_i (cv32e40p_top_i.core_i.cs_registers_i.csr_we_int), - .csr_wdata_int_i(cv32e40p_top_i.core_i.cs_registers_i.csr_wdata_int), - - .csr_mstatus_n_i (cv32e40p_top_i.core_i.cs_registers_i.mstatus_n), - .csr_mstatus_q_i (cv32e40p_top_i.core_i.cs_registers_i.mstatus_q), - .csr_mstatus_fs_n_i(cv32e40p_top_i.core_i.cs_registers_i.mstatus_fs_n), - .csr_mstatus_fs_q_i(cv32e40p_top_i.core_i.cs_registers_i.mstatus_fs_q), - - .csr_misa_n_i(cv32e40p_top_i.core_i.cs_registers_i.MISA_VALUE), // WARL - .csr_misa_q_i(cv32e40p_top_i.core_i.cs_registers_i.MISA_VALUE), - - .csr_tdata1_n_i (cv32e40p_top_i.core_i.cs_registers_i.tmatch_control_rdata),//csr_wdata_int ), - .csr_tdata1_q_i (cv32e40p_top_i.core_i.cs_registers_i.tmatch_control_rdata),//gen_trigger_regs.tmatch_control_exec_q ), - .csr_tdata1_we_i(cv32e40p_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_control_we), - - .csr_tinfo_n_i({16'h0, cv32e40p_top_i.core_i.cs_registers_i.tinfo_types}), - .csr_tinfo_q_i({16'h0, cv32e40p_top_i.core_i.cs_registers_i.tinfo_types}), - - .csr_mie_n_i (cv32e40p_top_i.core_i.cs_registers_i.mie_n), - .csr_mie_q_i (cv32e40p_top_i.core_i.cs_registers_i.mie_q), - .csr_mie_we_i (cv32e40p_top_i.core_i.cs_registers_i.csr_mie_we), - .csr_mtvec_n_i (cv32e40p_top_i.core_i.cs_registers_i.mtvec_n), - .csr_mtvec_q_i (cv32e40p_top_i.core_i.cs_registers_i.mtvec_q), - .csr_mtvec_mode_n_i(cv32e40p_top_i.core_i.cs_registers_i.mtvec_mode_n), - .csr_mtvec_mode_q_i(cv32e40p_top_i.core_i.cs_registers_i.mtvec_mode_q), - - .csr_mcountinhibit_q_i (cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_q), - .csr_mcountinhibit_n_i (cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_n), - .csr_mcountinhibit_we_i(cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_we), - - .csr_mscratch_q_i(cv32e40p_top_i.core_i.cs_registers_i.mscratch_q), - .csr_mscratch_n_i(cv32e40p_top_i.core_i.cs_registers_i.mscratch_n), - .csr_mepc_q_i(cv32e40p_top_i.core_i.cs_registers_i.mepc_q), - .csr_mepc_n_i(cv32e40p_top_i.core_i.cs_registers_i.mepc_n), - .csr_mcause_q_i(cv32e40p_top_i.core_i.cs_registers_i.mcause_q), - .csr_mcause_n_i(cv32e40p_top_i.core_i.cs_registers_i.mcause_n), - .csr_mip_n_i(cv32e40p_top_i.core_i.cs_registers_i.mip), - .csr_mip_q_i(cv32e40p_top_i.core_i.cs_registers_i.mip), - .csr_mip_we_i('0), //(cv32e40p_top_i.core_i.cs_registers_i.mip) - - - .csr_dcsr_q_i(cv32e40p_top_i.core_i.cs_registers_i.dcsr_q), - .csr_dcsr_n_i(cv32e40p_top_i.core_i.cs_registers_i.dcsr_n), - - .csr_dpc_n_i(cv32e40p_top_i.core_i.cs_registers_i.depc_n), - .csr_dpc_q_i(cv32e40p_top_i.core_i.cs_registers_i.depc_q), - .csr_dpc_we_i('0), //cv32e40p_top_i.core_i.cs_registers_i.), - .csr_dscratch0_n_i(cv32e40p_top_i.core_i.cs_registers_i.dscratch0_n), - .csr_dscratch0_q_i(cv32e40p_top_i.core_i.cs_registers_i.dscratch0_q), - .csr_dscratch0_we_i('0), //cv32e40p_top_i.core_i.cs_registers_i.), - - .csr_dscratch1_n_i(cv32e40p_top_i.core_i.cs_registers_i.dscratch1_n), - .csr_dscratch1_q_i(cv32e40p_top_i.core_i.cs_registers_i.dscratch1_q), - .csr_dscratch1_we_i('0), //cv32e40p_top_i.core_i.cs_registers_i.), - - .csr_mhpmcounter_q_i (cv32e40p_top_i.core_i.cs_registers_i.mhpmcounter_q), - .csr_mhpmcounter_write_lower_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmcounter_write_lower), - .csr_mhpmcounter_write_upper_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmcounter_write_upper), - - .csr_mvendorid_i({ - MVENDORID_BANK, MVENDORID_OFFSET - }), //TODO: get this from the design instead of the pkg - .csr_marchid_i(MARCHID), //TODO: get this from the design instead of the pkg - - .csr_fcsr_fflags_n_i (cv32e40p_top_i.core_i.cs_registers_i.fflags_n), - .csr_fcsr_fflags_q_i (cv32e40p_top_i.core_i.cs_registers_i.fflags_q), - .csr_fcsr_fflags_we_i(cv32e40p_top_i.core_i.cs_registers_i.fflags_we_i), - .csr_fcsr_frm_n_i (cv32e40p_top_i.core_i.cs_registers_i.frm_n), - .csr_fcsr_frm_q_i (cv32e40p_top_i.core_i.cs_registers_i.frm_q) - ); -`endif - -`ifdef CV32E40P_RVFI_TRACE_EXECUTION - bind cv32e40p_rvfi: rvfi_i cv32e40p_rvfi_trace #( - .FPU (FPU), - .ZFINX(ZFINX) - ) cv32e40p_tracer_i ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .hart_id_i(cv32e40p_top_i.core_i.hart_id_i), - - .imm_s3_type(cv32e40p_top_i.core_i.id_stage_i.imm_s3_type), - - .rvfi_valid(rvfi_valid), - .rvfi_insn(rvfi_insn), - .rvfi_pc_rdata(rvfi_pc_rdata), - .rvfi_rd_addr(rvfi_rd_addr), - .rvfi_rd_wdata(rvfi_rd_wdata), - .rvfi_frd_wvalid(rvfi_frd_wvalid), - .rvfi_frd_addr(rvfi_frd_addr), - .rvfi_frd_wdata(rvfi_frd_wdata), - .rvfi_rs1_addr(rvfi_rs1_addr), - .rvfi_rs2_addr(rvfi_rs2_addr), - .rvfi_rs1_rdata(rvfi_rs1_rdata), - .rvfi_rs2_rdata(rvfi_rs2_rdata), - .rvfi_frs1_addr(rvfi_frs1_addr), - .rvfi_frs2_addr(rvfi_frs2_addr), - .rvfi_frs1_rvalid(rvfi_frs1_rvalid), - .rvfi_frs2_rvalid(rvfi_frs2_rvalid), - .rvfi_frs1_rdata(rvfi_frs1_rdata), - .rvfi_frs2_rdata(rvfi_frs2_rdata) - ); -`endif - // Instantiate the Core and the optinal FPU - cv32e40p_top #( - .COREV_PULP (COREV_PULP), - .COREV_CLUSTER (COREV_CLUSTER), - .FPU (FPU), - .FPU_ADDMUL_LAT (FPU_ADDMUL_LAT), - .FPU_OTHERS_LAT (FPU_OTHERS_LAT), - .ZFINX (ZFINX), - .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS) - ) cv32e40p_top_i ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - .pulp_clock_en_i(pulp_clock_en_i), - .scan_cg_en_i (scan_cg_en_i), - - .boot_addr_i (boot_addr_i), - .mtvec_addr_i (mtvec_addr_i), - .dm_halt_addr_i (dm_halt_addr_i), - .hart_id_i (hart_id_i), - .dm_exception_addr_i(dm_exception_addr_i), - - .instr_req_o (instr_req_o), - .instr_gnt_i (instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_addr_o (instr_addr_o), - .instr_rdata_i (instr_rdata_i), - - .data_req_o (data_req_o), - .data_gnt_i (data_gnt_i), - .data_rvalid_i(data_rvalid_i), - .data_we_o (data_we_o), - .data_be_o (data_be_o), - .data_addr_o (data_addr_o), - .data_wdata_o (data_wdata_o), - .data_rdata_i (data_rdata_i), - - .irq_i (irq_i), - .irq_ack_o(irq_ack_o), - .irq_id_o (irq_id_o), - - .debug_req_i (debug_req_i), - .debug_havereset_o(debug_havereset_o), - .debug_running_o (debug_running_o), - .debug_halted_o (debug_halted_o), - - .fetch_enable_i(fetch_enable_i), - .core_sleep_o (core_sleep_o) - ); - -endmodule diff --git a/bhv/cv32e40p_apu_tracer.sv b/bhv/cv32e40px_apu_tracer.sv similarity index 92% rename from bhv/cv32e40p_apu_tracer.sv rename to bhv/cv32e40px_apu_tracer.sv index 6183b00d8..f48e49cee 100644 --- a/bhv/cv32e40p_apu_tracer.sv +++ b/bhv/cv32e40px_apu_tracer.sv @@ -21,7 +21,7 @@ //////////////////////////////////////////////////////////////////////////////// // Engineer: Arjan Bink - arjan.bink@silabs.com // // // -// Design Name: cv32e40p_apu_tracer.sv (APU trace) // +// Design Name: cv32e40px_apu_tracer.sv (APU trace) // // Project Name: CV32E40P // // Language: SystemVerilog // // // @@ -30,14 +30,14 @@ // - APU register file write address // // - APU register file write data // // // -// Note: This code was here from cv32e40p_core.sv in order to // +// Note: This code was here from cv32e40px_core.sv in order to // // remove the use of global defines in the RTL code. // // // //////////////////////////////////////////////////////////////////////////////// `ifdef CV32E40P_APU_TRACE -module cv32e40p_apu_tracer ( +module cv32e40px_apu_tracer ( input logic clk_i, input logic rst_n, input logic [31:0] hart_id_i, @@ -74,6 +74,6 @@ module cv32e40p_apu_tracer ( $fclose(apu_trace); end -endmodule // cv32e40p_apu_tracer +endmodule // cv32e40px_apu_tracer `endif // CV32E40P_APU_TRACE diff --git a/bhv/cv32e40p_core_log.sv b/bhv/cv32e40px_core_log.sv similarity index 87% rename from bhv/cv32e40p_core_log.sv rename to bhv/cv32e40px_core_log.sv index 8c2824eeb..4544143d2 100644 --- a/bhv/cv32e40p_core_log.sv +++ b/bhv/cv32e40px_core_log.sv @@ -21,7 +21,7 @@ //////////////////////////////////////////////////////////////////////////////// // Engineer: Arjan Bink - arjan.bink@silabs.com // // // -// Design Name: cv32e40p_core_log.sv (cv32e40p_core simulation log) // +// Design Name: cv32e40px_core_log.sv (cv32e40px_core simulation log) // // Project Name: CV32E40P // // Language: SystemVerilog // // // @@ -30,13 +30,13 @@ // - top level parameter settings // // - illegal instructions // // // -// Note: This code was here from cv32e40p_core.sv and // -// cv32e40p_controller.sv in order to remove the use of // +// Note: This code was here from cv32e40px_core.sv and // +// cv32e40px_controller.sv in order to remove the use of // // global defines in the RTL code. // // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_core_log #( +module cv32e40px_core_log #( parameter COREV_PULP = 1, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) parameter FPU = 0, // Floating Point Unit (interfaced via APU interface) @@ -53,7 +53,7 @@ module cv32e40p_core_log #( // Log top level parameter values initial begin $display( - "[cv32e40p_core]: COREV_PULP = %d, COREV_CLUSTER = %d, FPU %d, ZFINX %d, NUM_MHPMCOUNTERS %d", + "[cv32e40px_core]: COREV_PULP = %d, COREV_CLUSTER = %d, FPU %d, ZFINX %d, NUM_MHPMCOUNTERS %d", COREV_PULP, COREV_CLUSTER, FPU, ZFINX, NUM_MHPMCOUNTERS); end @@ -65,4 +65,4 @@ module cv32e40p_core_log #( end end -endmodule // cv32e40p_core_log +endmodule // cv32e40px_core_log diff --git a/bhv/cv32e40p_instr_trace.svh b/bhv/cv32e40px_instr_trace.svh similarity index 100% rename from bhv/cv32e40p_instr_trace.svh rename to bhv/cv32e40px_instr_trace.svh diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40px_rvfi.sv similarity index 99% rename from bhv/cv32e40p_rvfi.sv rename to bhv/cv32e40px_rvfi.sv index 7bdb5245d..51861918f 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40px_rvfi.sv @@ -20,11 +20,11 @@ // Halfdan Bechmann, Silicon Labs // Yoann Pruvost, Dolphin Design -`include "cv32e40p_rvfi_pkg.sv" +`include "cv32e40px_rvfi_pkg.sv" -module cv32e40p_rvfi - import cv32e40p_pkg::*; - import cv32e40p_rvfi_pkg::*; +module cv32e40px_rvfi + import cv32e40px_pkg::*; + import cv32e40px_rvfi_pkg::*; #( parameter FPU = 0, parameter ZFINX = 0 @@ -1709,4 +1709,4 @@ module cv32e40p_rvfi join end -endmodule // cv32e40p_rvfi +endmodule // cv32e40px_rvfi diff --git a/bhv/cv32e40p_rvfi_trace.sv b/bhv/cv32e40px_rvfi_trace.sv similarity index 97% rename from bhv/cv32e40p_rvfi_trace.sv rename to bhv/cv32e40px_rvfi_trace.sv index 6ed4b773e..a77cd0b38 100644 --- a/bhv/cv32e40p_rvfi_trace.sv +++ b/bhv/cv32e40px_rvfi_trace.sv @@ -19,8 +19,8 @@ // Contributors: Halfdan Bechmann, Silicon Labs // Yoann Pruvost, Dolphin Design -module cv32e40p_rvfi_trace - import cv32e40p_pkg::*; +module cv32e40px_rvfi_trace + import cv32e40px_pkg::*; #( parameter FPU = 0, parameter ZFINX = 0 @@ -56,7 +56,7 @@ module cv32e40p_rvfi_trace input logic [31:0] rvfi_frs2_rdata ); - import cv32e40p_tracer_pkg::*; + import cv32e40px_tracer_pkg::*; logic rst_n; assign rst_n = rst_ni; @@ -136,7 +136,7 @@ module cv32e40p_rvfi_trace assign imm_shuffle_type = '0; assign imm_clip_type = '0; - cv32e40p_compressed_decoder #( + cv32e40px_compressed_decoder #( .FPU(FPU) ) rvfi_trace_decompress_i ( .instr_i(rvfi_insn), @@ -144,7 +144,7 @@ module cv32e40p_rvfi_trace .is_compressed_o(is_compressed) ); - `include "cv32e40p_instr_trace.svh" + `include "cv32e40px_instr_trace.svh" instr_trace_t trace_retire; function instr_trace_t trace_new_instr(); diff --git a/bhv/cv32e40p_sim_clock_gate.sv b/bhv/cv32e40px_sim_clock_gate.sv similarity index 88% rename from bhv/cv32e40p_sim_clock_gate.sv rename to bhv/cv32e40px_sim_clock_gate.sv index 65d2bfefb..dde7b5344 100644 --- a/bhv/cv32e40p_sim_clock_gate.sv +++ b/bhv/cv32e40px_sim_clock_gate.sv @@ -8,11 +8,11 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// !!! cv32e40p_sim_clock_gate file is meant for simulation only !!! +// !!! cv32e40px_sim_clock_gate file is meant for simulation only !!! // !!! It must not be used for ASIC synthesis !!! // !!! It must not be used for FPGA synthesis !!! -module cv32e40p_clock_gate ( +module cv32e40px_clock_gate ( input logic clk_i, input logic en_i, input logic scan_cg_en_i, @@ -27,4 +27,4 @@ module cv32e40p_clock_gate ( assign clk_o = clk_i & clk_en; -endmodule // cv32e40p_clock_gate +endmodule // cv32e40px_clock_gate diff --git a/bhv/cv32e40px_tb_wrapper.sv b/bhv/cv32e40px_tb_wrapper.sv new file mode 100644 index 000000000..1b40b80ed --- /dev/null +++ b/bhv/cv32e40px_tb_wrapper.sv @@ -0,0 +1,508 @@ +// Copyright (c) 2020 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +// Wrapper for a cv32e40px, containing cv32e40px_top, and rvfi_tracer +// +// Contributors: Davide Schiavone, OpenHW Group +// Yoann Pruvost, Dolphin Design + +`ifdef CV32E40P_ASSERT_ON +`include "cv32e40px_prefetch_controller_sva.sv" +`endif + +`ifdef CV32E40P_CORE_LOG +`include "cv32e40px_core_log.sv" +`endif + +`ifdef CV32E40P_APU_TRACE +`include "cv32e40px_apu_tracer.sv" +`endif + +`ifdef CV32E40P_TRACE_EXECUTION +`include "cv32e40px_tracer.sv" +`endif + +`ifdef CV32E40P_RVFI +`include "cv32e40px_rvfi.sv" +`endif + +`ifdef CV32E40P_RVFI_TRACE_EXECUTION +`include "cv32e40px_rvfi_trace.sv" +`endif + +module cv32e40px_tb_wrapper + import cv32e40px_pkg::*; +#( + parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) + parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) + parameter FPU = 0, // Floating Point Unit (interfaced via APU interface) + parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number + parameter FPU_OTHERS_LAT = 0, // Floating-Point COMParison/CONVersion computing lanes pipeline registers number + parameter ZFINX = 0, // Float-in-General Purpose registers + parameter NUM_MHPMCOUNTERS = 1 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic pulp_clock_en_i, // PULP clock enable (only used if COREV_CLUSTER = 1) + input logic scan_cg_en_i, // Enable all clock gates for testing + + // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static + input logic [31:0] boot_addr_i, + input logic [31:0] mtvec_addr_i, + input logic [31:0] dm_halt_addr_i, + input logic [31:0] hart_id_i, + input logic [31:0] dm_exception_addr_i, + + // Instruction memory interface + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + + // Data memory interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [ 3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + // Interrupt inputs + input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts + output logic irq_ack_o, + output logic [ 4:0] irq_id_o, + + // Debug Interface + input logic debug_req_i, + output logic debug_havereset_o, + output logic debug_running_o, + output logic debug_halted_o, + + // CPU Control Signals + input logic fetch_enable_i, + output logic core_sleep_o +); + +`ifdef CV32E40P_ASSERT_ON + + // RTL Assertions + bind cv32e40px_prefetch_controller: + cv32e40px_top_i.core_i.if_stage_i.prefetch_buffer_i.prefetch_controller_i + cv32e40px_prefetch_controller_sva + #( + .DEPTH (DEPTH), + .COREV_PULP (COREV_PULP), + .PULP_OBI (PULP_OBI), + .FIFO_ADDR_DEPTH(FIFO_ADDR_DEPTH) + ) prefetch_controller_sva (.*); + +`endif // CV32E40P_ASSERT_ON + +`ifdef CV32E40P_CORE_LOG + cv32e40px_core_log #( + .COREV_PULP (COREV_PULP), + .COREV_CLUSTER (COREV_CLUSTER), + .FPU (FPU), + .ZFINX (ZFINX), + .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS) + ) core_log_i ( + .clk_i (cv32e40px_top_i.core_i.id_stage_i.clk), + .is_decoding_i (cv32e40px_top_i.core_i.id_stage_i.is_decoding_o), + .illegal_insn_dec_i(cv32e40px_top_i.core_i.id_stage_i.illegal_insn_dec), + .hart_id_i (cv32e40px_top_i.core_i.hart_id_i), + .pc_id_i (cv32e40px_top_i.core_i.pc_id) + ); +`endif // CV32E40P_CORE_LOG + +`ifdef CV32E40P_APU_TRACE + cv32e40px_apu_tracer apu_tracer_i ( + .clk_i (cv32e40px_top_i.core_i.rst_ni), + .rst_n (cv32e40px_top_i.core_i.clk_i), + .hart_id_i (cv32e40px_top_i.core_i.hart_id_i), + .apu_valid_i (cv32e40px_top_i.core_i.ex_stage_i.apu_valid), + .apu_waddr_i (cv32e40px_top_i.core_i.ex_stage_i.apu_waddr), + .apu_result_i(cv32e40px_top_i.core_i.ex_stage_i.apu_result) + ); +`endif + +`ifdef CV32E40P_TRACE_EXECUTION + cv32e40px_tracer #( + .FPU (FPU), + .ZFINX(ZFINX) + ) tracer_i ( + .clk_i(cv32e40px_top_i.core_i.clk_i), // always-running clock for tracing + .rst_n(cv32e40px_top_i.core_i.rst_ni), + + .hart_id_i(cv32e40px_top_i.core_i.hart_id_i), + + .pc (cv32e40px_top_i.core_i.id_stage_i.pc_id_i), + .instr (cv32e40px_top_i.core_i.id_stage_i.instr), + .controller_state_i(cv32e40px_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs), + .compressed (cv32e40px_top_i.core_i.id_stage_i.is_compressed_i), + .id_valid (cv32e40px_top_i.core_i.id_stage_i.id_valid_o), + .is_decoding (cv32e40px_top_i.core_i.id_stage_i.is_decoding_o), + .is_illegal (cv32e40px_top_i.core_i.id_stage_i.illegal_insn_dec), + .trigger_match (cv32e40px_top_i.core_i.id_stage_i.trigger_match_i), + .rs1_value (cv32e40px_top_i.core_i.id_stage_i.operand_a_fw_id), + .rs2_value (cv32e40px_top_i.core_i.id_stage_i.operand_b_fw_id), + .rs3_value (cv32e40px_top_i.core_i.id_stage_i.alu_operand_c), + .rs2_value_vec (cv32e40px_top_i.core_i.id_stage_i.alu_operand_b), + + .rs1_is_fp(cv32e40px_top_i.core_i.id_stage_i.regfile_fp_a), + .rs2_is_fp(cv32e40px_top_i.core_i.id_stage_i.regfile_fp_b), + .rs3_is_fp(cv32e40px_top_i.core_i.id_stage_i.regfile_fp_c), + .rd_is_fp (cv32e40px_top_i.core_i.id_stage_i.regfile_fp_d), + + .ex_valid (cv32e40px_top_i.core_i.ex_valid), + .ex_reg_addr (cv32e40px_top_i.core_i.regfile_alu_waddr_fw), + .ex_reg_we (cv32e40px_top_i.core_i.regfile_alu_we_fw), + .ex_reg_wdata(cv32e40px_top_i.core_i.regfile_alu_wdata_fw), + + .ex_data_addr (cv32e40px_top_i.core_i.data_addr_o), + .ex_data_req (cv32e40px_top_i.core_i.data_req_o), + .ex_data_gnt (cv32e40px_top_i.core_i.data_gnt_i), + .ex_data_we (cv32e40px_top_i.core_i.data_we_o), + .ex_data_wdata (cv32e40px_top_i.core_i.data_wdata_o), + .data_misaligned(cv32e40px_top_i.core_i.data_misaligned), + + .ebrk_insn(cv32e40px_top_i.core_i.id_stage_i.ebrk_insn_dec), + .debug_mode(cv32e40px_top_i.core_i.debug_mode), + .ebrk_force_debug_mode(cv32e40px_top_i.core_i.id_stage_i.controller_i.ebrk_force_debug_mode), + + .wb_bypass(cv32e40px_top_i.core_i.ex_stage_i.branch_in_ex_i), + + .wb_valid (cv32e40px_top_i.core_i.wb_valid), + .wb_reg_addr (cv32e40px_top_i.core_i.regfile_waddr_fw_wb_o), + .wb_reg_we (cv32e40px_top_i.core_i.regfile_we_wb), + .wb_reg_wdata(cv32e40px_top_i.core_i.regfile_wdata), + + .imm_u_type (cv32e40px_top_i.core_i.id_stage_i.imm_u_type), + .imm_uj_type (cv32e40px_top_i.core_i.id_stage_i.imm_uj_type), + .imm_i_type (cv32e40px_top_i.core_i.id_stage_i.imm_i_type), + .imm_iz_type (cv32e40px_top_i.core_i.id_stage_i.imm_iz_type[11:0]), + .imm_z_type (cv32e40px_top_i.core_i.id_stage_i.imm_z_type), + .imm_s_type (cv32e40px_top_i.core_i.id_stage_i.imm_s_type), + .imm_sb_type (cv32e40px_top_i.core_i.id_stage_i.imm_sb_type), + .imm_s2_type (cv32e40px_top_i.core_i.id_stage_i.imm_s2_type), + .imm_s3_type (cv32e40px_top_i.core_i.id_stage_i.imm_s3_type), + .imm_vs_type (cv32e40px_top_i.core_i.id_stage_i.imm_vs_type), + .imm_vu_type (cv32e40px_top_i.core_i.id_stage_i.imm_vu_type), + .imm_shuffle_type (cv32e40px_top_i.core_i.id_stage_i.imm_shuffle_type), + .imm_clip_type (cv32e40px_top_i.core_i.id_stage_i.instr[11:7]), + .apu_en_i (cv32e40px_top_i.apu_req), + .apu_singlecycle_i(cv32e40px_top_i.core_i.ex_stage_i.apu_singlecycle), + .apu_multicycle_i (cv32e40px_top_i.core_i.ex_stage_i.apu_multicycle), + .apu_rvalid_i (cv32e40px_top_i.apu_rvalid) + ); +`endif + +`ifdef CV32E40P_RVFI + logic [1:0][31:0] hwlp_start_q; + logic [1:0][31:0] hwlp_end_q; + logic [1:0][31:0] hwlp_counter_q; + logic [1:0][31:0] hwlp_counter_n; + generate + if (COREV_PULP) begin + assign hwlp_start_q = cv32e40px_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_start_q ; + assign hwlp_end_q = cv32e40px_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_end_q; + assign hwlp_counter_q = cv32e40px_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_counter_q; + assign hwlp_counter_n = cv32e40px_top_i.core_i.id_stage_i.gen_hwloop_regs.hwloop_regs_i.hwlp_counter_n; + end else begin + assign hwlp_start_q = '0; + assign hwlp_end_q = '0; + assign hwlp_counter_q = '0; + assign hwlp_counter_n = '0; + end + endgenerate + + cv32e40px_rvfi #( + .FPU (FPU), + .ZFINX(ZFINX) + ) rvfi_i ( + .clk_i (cv32e40px_top_i.core_i.clk_i), + .rst_ni(cv32e40px_top_i.core_i.rst_ni), + + .is_decoding_i (cv32e40px_top_i.core_i.id_stage_i.is_decoding_o), + .is_illegal_i (cv32e40px_top_i.core_i.id_stage_i.illegal_insn_dec), + .trigger_match_i (cv32e40px_top_i.core_i.id_stage_i.trigger_match_i), + .data_misaligned_i(cv32e40px_top_i.core_i.data_misaligned), + .lsu_data_we_ex_i (cv32e40px_top_i.core_i.data_we_ex), + .debug_mode_i (cv32e40px_top_i.core_i.debug_mode), + .debug_cause_i (cv32e40px_top_i.core_i.debug_cause), + //// Instr IF probes //// + .instr_req_i (cv32e40px_top_i.core_i.instr_req_o), + .instr_grant_i (cv32e40px_top_i.core_i.instr_gnt_i), + .instr_rvalid_i (cv32e40px_top_i.core_i.instr_rvalid_i), + .prefetch_req_i (cv32e40px_top_i.core_i.instr_req_int), + .pc_set_i (cv32e40px_top_i.core_i.pc_set), + + .instr_valid_id_i (cv32e40px_top_i.core_i.instr_valid_id), + .instr_rdata_id_i (cv32e40px_top_i.core_i.instr_rdata_id), + .is_fetch_failed_id_i(cv32e40px_top_i.core_i.is_fetch_failed_id), + .instr_req_int_i (cv32e40px_top_i.core_i.instr_req_int), + .clear_instr_valid_i (cv32e40px_top_i.core_i.clear_instr_valid), + //// IF probes //// + .instr_valid_if_i (cv32e40px_top_i.core_i.if_stage_i.instr_valid), + .if_valid_i (cv32e40px_top_i.core_i.if_stage_i.if_valid), + .if_ready_i (cv32e40px_top_i.core_i.if_stage_i.if_ready), + .instr_if_i (cv32e40px_top_i.core_i.if_stage_i.instr_aligned), + .pc_if_i (cv32e40px_top_i.core_i.pc_if), + //// ID probes //// + .pc_id_i (cv32e40px_top_i.core_i.id_stage_i.pc_id_i), + .id_valid_i (cv32e40px_top_i.core_i.id_stage_i.id_valid_o), + .id_ready_i (cv32e40px_top_i.core_i.id_stage_i.id_ready_o), + + .rs1_addr_id_i (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_ra_id), + .rs2_addr_id_i (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_rb_id), + .operand_a_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_a_fw_id), + .operand_b_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_b_fw_id), + // .instr (cv32e40px_top_i.core_i.id_stage_i.instr ), + .is_compressed_id_i(cv32e40px_top_i.core_i.id_stage_i.is_compressed_i), + .ebrk_insn_dec_i (cv32e40px_top_i.core_i.id_stage_i.ebrk_insn_dec), + .csr_cause_i (cv32e40px_top_i.core_i.csr_cause), + .debug_csr_save_i (cv32e40px_top_i.core_i.debug_csr_save), + + // HWLOOP regs + .hwlp_start_q_i (hwlp_start_q), + .hwlp_end_q_i (hwlp_end_q), + .hwlp_counter_q_i(hwlp_counter_q), + .hwlp_counter_n_i(hwlp_counter_n), + + .minstret_i (cv32e40px_top_i.core_i.id_stage_i.minstret), + //// EX probes //// + .ex_valid_i (cv32e40px_top_i.core_i.ex_valid), + .ex_ready_i (cv32e40px_top_i.core_i.ex_ready), + .ex_reg_addr_i (cv32e40px_top_i.core_i.regfile_alu_waddr_fw), + .ex_reg_we_i (cv32e40px_top_i.core_i.regfile_alu_we_fw), + .ex_reg_wdata_i (cv32e40px_top_i.core_i.regfile_alu_wdata_fw), + .apu_en_ex_i (cv32e40px_top_i.core_i.apu_en_ex), + .apu_singlecycle_i (cv32e40px_top_i.core_i.ex_stage_i.apu_singlecycle), + .apu_multicycle_i (cv32e40px_top_i.core_i.ex_stage_i.apu_multicycle), + .wb_contention_lsu_i(cv32e40px_top_i.core_i.ex_stage_i.wb_contention_lsu), + .wb_contention_i (cv32e40px_top_i.core_i.ex_stage_i.wb_contention), + + // .rf_we_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_we_fw_i), + // .rf_addr_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i), + // .rf_wdata_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i), + + //// WB probes //// + .wb_valid_i(cv32e40px_top_i.core_i.wb_valid), + + //// LSU probes //// + .data_we_ex_i (cv32e40px_top_i.core_i.data_we_ex), + .data_atop_ex_i (cv32e40px_top_i.core_i.data_atop_ex), + .data_type_ex_i (cv32e40px_top_i.core_i.data_type_ex), + .alu_operand_c_ex_i (cv32e40px_top_i.core_i.alu_operand_c_ex), + .data_reg_offset_ex_i(cv32e40px_top_i.core_i.data_reg_offset_ex), + .data_load_event_ex_i(cv32e40px_top_i.core_i.data_load_event_ex), + .data_sign_ext_ex_i (cv32e40px_top_i.core_i.data_sign_ext_ex), + .lsu_rdata_i (cv32e40px_top_i.core_i.lsu_rdata), + .data_req_ex_i (cv32e40px_top_i.core_i.data_req_ex), + .alu_operand_a_ex_i (cv32e40px_top_i.core_i.alu_operand_a_ex), + .alu_operand_b_ex_i (cv32e40px_top_i.core_i.alu_operand_b_ex), + .useincr_addr_ex_i (cv32e40px_top_i.core_i.useincr_addr_ex), + .data_misaligned_ex_i(cv32e40px_top_i.core_i.data_misaligned_ex), + .p_elw_start_i (cv32e40px_top_i.core_i.p_elw_start), + .p_elw_finish_i (cv32e40px_top_i.core_i.p_elw_finish), + .lsu_ready_ex_i (cv32e40px_top_i.core_i.lsu_ready_ex), + .lsu_ready_wb_i (cv32e40px_top_i.core_i.lsu_ready_wb), + + .data_req_pmp_i(cv32e40px_top_i.core_i.data_req_pmp), + .data_gnt_pmp_i(cv32e40px_top_i.core_i.data_gnt_pmp), + .data_rvalid_i(cv32e40px_top_i.core_i.data_rvalid_i), + .data_err_pmp_i(cv32e40px_top_i.core_i.data_err_pmp), + .data_addr_pmp_i(cv32e40px_top_i.core_i.data_addr_pmp), + .data_we_i(cv32e40px_top_i.core_i.data_we_o), + .data_atop_i(cv32e40px_top_i.core_i.data_atop_o), + .data_be_i(cv32e40px_top_i.core_i.data_be_o), + .data_wdata_i(cv32e40px_top_i.core_i.data_wdata_o), + .data_rdata_i(cv32e40px_top_i.core_i.data_rdata_i), + // Register writes + .rf_we_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_we_wb_i), + .rf_addr_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_waddr_wb_i), + .rf_wdata_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_wdata_wb_i), + + // APU + .apu_req_i (cv32e40px_top_i.core_i.apu_req_o), + .apu_gnt_i (cv32e40px_top_i.core_i.apu_gnt_i), + .apu_rvalid_i(cv32e40px_top_i.core_i.apu_rvalid_i), + + // Controller FSM probes + .ctrl_fsm_cs_i(cv32e40px_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs), + .pc_mux_i (cv32e40px_top_i.core_i.id_stage_i.controller_i.pc_mux_o), + .exc_pc_mux_i (cv32e40px_top_i.core_i.id_stage_i.controller_i.exc_pc_mux_o), + + //CSR + .csr_addr_i (cv32e40px_top_i.core_i.cs_registers_i.csr_addr_i), + .csr_we_i (cv32e40px_top_i.core_i.cs_registers_i.csr_we_int), + .csr_wdata_int_i(cv32e40px_top_i.core_i.cs_registers_i.csr_wdata_int), + + .csr_mstatus_n_i (cv32e40px_top_i.core_i.cs_registers_i.mstatus_n), + .csr_mstatus_q_i (cv32e40px_top_i.core_i.cs_registers_i.mstatus_q), + .csr_mstatus_fs_n_i(cv32e40px_top_i.core_i.cs_registers_i.mstatus_fs_n), + .csr_mstatus_fs_q_i(cv32e40px_top_i.core_i.cs_registers_i.mstatus_fs_q), + + .csr_misa_n_i(cv32e40px_top_i.core_i.cs_registers_i.MISA_VALUE), // WARL + .csr_misa_q_i(cv32e40px_top_i.core_i.cs_registers_i.MISA_VALUE), + + .csr_tdata1_n_i (cv32e40px_top_i.core_i.cs_registers_i.tmatch_control_rdata),//csr_wdata_int ), + .csr_tdata1_q_i (cv32e40px_top_i.core_i.cs_registers_i.tmatch_control_rdata),//gen_trigger_regs.tmatch_control_exec_q ), + .csr_tdata1_we_i(cv32e40px_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_control_we), + + .csr_tinfo_n_i({16'h0, cv32e40px_top_i.core_i.cs_registers_i.tinfo_types}), + .csr_tinfo_q_i({16'h0, cv32e40px_top_i.core_i.cs_registers_i.tinfo_types}), + + .csr_mie_n_i (cv32e40px_top_i.core_i.cs_registers_i.mie_n), + .csr_mie_q_i (cv32e40px_top_i.core_i.cs_registers_i.mie_q), + .csr_mie_we_i (cv32e40px_top_i.core_i.cs_registers_i.csr_mie_we), + .csr_mtvec_n_i (cv32e40px_top_i.core_i.cs_registers_i.mtvec_n), + .csr_mtvec_q_i (cv32e40px_top_i.core_i.cs_registers_i.mtvec_q), + .csr_mtvec_mode_n_i(cv32e40px_top_i.core_i.cs_registers_i.mtvec_mode_n), + .csr_mtvec_mode_q_i(cv32e40px_top_i.core_i.cs_registers_i.mtvec_mode_q), + + .csr_mcountinhibit_q_i (cv32e40px_top_i.core_i.cs_registers_i.mcountinhibit_q), + .csr_mcountinhibit_n_i (cv32e40px_top_i.core_i.cs_registers_i.mcountinhibit_n), + .csr_mcountinhibit_we_i(cv32e40px_top_i.core_i.cs_registers_i.mcountinhibit_we), + + .csr_mscratch_q_i(cv32e40px_top_i.core_i.cs_registers_i.mscratch_q), + .csr_mscratch_n_i(cv32e40px_top_i.core_i.cs_registers_i.mscratch_n), + .csr_mepc_q_i(cv32e40px_top_i.core_i.cs_registers_i.mepc_q), + .csr_mepc_n_i(cv32e40px_top_i.core_i.cs_registers_i.mepc_n), + .csr_mcause_q_i(cv32e40px_top_i.core_i.cs_registers_i.mcause_q), + .csr_mcause_n_i(cv32e40px_top_i.core_i.cs_registers_i.mcause_n), + .csr_mip_n_i(cv32e40px_top_i.core_i.cs_registers_i.mip), + .csr_mip_q_i(cv32e40px_top_i.core_i.cs_registers_i.mip), + .csr_mip_we_i('0), //(cv32e40px_top_i.core_i.cs_registers_i.mip) + + + .csr_dcsr_q_i(cv32e40px_top_i.core_i.cs_registers_i.dcsr_q), + .csr_dcsr_n_i(cv32e40px_top_i.core_i.cs_registers_i.dcsr_n), + + .csr_dpc_n_i(cv32e40px_top_i.core_i.cs_registers_i.depc_n), + .csr_dpc_q_i(cv32e40px_top_i.core_i.cs_registers_i.depc_q), + .csr_dpc_we_i('0), //cv32e40px_top_i.core_i.cs_registers_i.), + .csr_dscratch0_n_i(cv32e40px_top_i.core_i.cs_registers_i.dscratch0_n), + .csr_dscratch0_q_i(cv32e40px_top_i.core_i.cs_registers_i.dscratch0_q), + .csr_dscratch0_we_i('0), //cv32e40px_top_i.core_i.cs_registers_i.), + + .csr_dscratch1_n_i(cv32e40px_top_i.core_i.cs_registers_i.dscratch1_n), + .csr_dscratch1_q_i(cv32e40px_top_i.core_i.cs_registers_i.dscratch1_q), + .csr_dscratch1_we_i('0), //cv32e40px_top_i.core_i.cs_registers_i.), + + .csr_mhpmcounter_q_i (cv32e40px_top_i.core_i.cs_registers_i.mhpmcounter_q), + .csr_mhpmcounter_write_lower_i(cv32e40px_top_i.core_i.cs_registers_i.mhpmcounter_write_lower), + .csr_mhpmcounter_write_upper_i(cv32e40px_top_i.core_i.cs_registers_i.mhpmcounter_write_upper), + + .csr_mvendorid_i({ + MVENDORID_BANK, MVENDORID_OFFSET + }), //TODO: get this from the design instead of the pkg + .csr_marchid_i(MARCHID), //TODO: get this from the design instead of the pkg + + .csr_fcsr_fflags_n_i (cv32e40px_top_i.core_i.cs_registers_i.fflags_n), + .csr_fcsr_fflags_q_i (cv32e40px_top_i.core_i.cs_registers_i.fflags_q), + .csr_fcsr_fflags_we_i(cv32e40px_top_i.core_i.cs_registers_i.fflags_we_i), + .csr_fcsr_frm_n_i (cv32e40px_top_i.core_i.cs_registers_i.frm_n), + .csr_fcsr_frm_q_i (cv32e40px_top_i.core_i.cs_registers_i.frm_q) + ); +`endif + +`ifdef CV32E40P_RVFI_TRACE_EXECUTION + bind cv32e40px_rvfi: rvfi_i cv32e40px_rvfi_trace #( + .FPU (FPU), + .ZFINX(ZFINX) + ) cv32e40px_tracer_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .hart_id_i(cv32e40px_top_i.core_i.hart_id_i), + + .imm_s3_type(cv32e40px_top_i.core_i.id_stage_i.imm_s3_type), + + .rvfi_valid(rvfi_valid), + .rvfi_insn(rvfi_insn), + .rvfi_pc_rdata(rvfi_pc_rdata), + .rvfi_rd_addr(rvfi_rd_addr), + .rvfi_rd_wdata(rvfi_rd_wdata), + .rvfi_frd_wvalid(rvfi_frd_wvalid), + .rvfi_frd_addr(rvfi_frd_addr), + .rvfi_frd_wdata(rvfi_frd_wdata), + .rvfi_rs1_addr(rvfi_rs1_addr), + .rvfi_rs2_addr(rvfi_rs2_addr), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_frs1_addr(rvfi_frs1_addr), + .rvfi_frs2_addr(rvfi_frs2_addr), + .rvfi_frs1_rvalid(rvfi_frs1_rvalid), + .rvfi_frs2_rvalid(rvfi_frs2_rvalid), + .rvfi_frs1_rdata(rvfi_frs1_rdata), + .rvfi_frs2_rdata(rvfi_frs2_rdata) + ); +`endif + // Instantiate the Core and the optinal FPU + cv32e40px_top #( + .COREV_PULP (COREV_PULP), + .COREV_CLUSTER (COREV_CLUSTER), + .FPU (FPU), + .FPU_ADDMUL_LAT (FPU_ADDMUL_LAT), + .FPU_OTHERS_LAT (FPU_OTHERS_LAT), + .ZFINX (ZFINX), + .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS) + ) cv32e40px_top_i ( + .clk_i (clk_i), + .rst_ni(rst_ni), + + .pulp_clock_en_i(pulp_clock_en_i), + .scan_cg_en_i (scan_cg_en_i), + + .boot_addr_i (boot_addr_i), + .mtvec_addr_i (mtvec_addr_i), + .dm_halt_addr_i (dm_halt_addr_i), + .hart_id_i (hart_id_i), + .dm_exception_addr_i(dm_exception_addr_i), + + .instr_req_o (instr_req_o), + .instr_gnt_i (instr_gnt_i), + .instr_rvalid_i(instr_rvalid_i), + .instr_addr_o (instr_addr_o), + .instr_rdata_i (instr_rdata_i), + + .data_req_o (data_req_o), + .data_gnt_i (data_gnt_i), + .data_rvalid_i(data_rvalid_i), + .data_we_o (data_we_o), + .data_be_o (data_be_o), + .data_addr_o (data_addr_o), + .data_wdata_o (data_wdata_o), + .data_rdata_i (data_rdata_i), + + .irq_i (irq_i), + .irq_ack_o(irq_ack_o), + .irq_id_o (irq_id_o), + + .debug_req_i (debug_req_i), + .debug_havereset_o(debug_havereset_o), + .debug_running_o (debug_running_o), + .debug_halted_o (debug_halted_o), + + .fetch_enable_i(fetch_enable_i), + .core_sleep_o (core_sleep_o) + ); + +endmodule diff --git a/bhv/cv32e40p_tracer.sv b/bhv/cv32e40px_tracer.sv similarity index 99% rename from bhv/cv32e40p_tracer.sv rename to bhv/cv32e40px_tracer.sv index 8208f2e61..c0c13315b 100644 --- a/bhv/cv32e40p_tracer.sv +++ b/bhv/cv32e40px_tracer.sv @@ -24,8 +24,8 @@ `include "uvm_macros.svh" -module cv32e40p_tracer - import cv32e40p_pkg::*; +module cv32e40px_tracer + import cv32e40px_pkg::*; import uvm_pkg::*; #( parameter FPU = 0, @@ -103,7 +103,7 @@ module cv32e40p_tracer ); - import cv32e40p_tracer_pkg::*; + import cv32e40px_tracer_pkg::*; // Make clock a bit to avoid x->0 transitions in tracer logic bit clk_i_d, eval_comb; @@ -124,7 +124,7 @@ module cv32e40p_tracer logic [31:0] pc_wb_delay_stage; logic [31:0] pc_retire_head_q; - `include "cv32e40p_instr_trace.svh" + `include "cv32e40px_instr_trace.svh" string info_tag; @@ -554,7 +554,7 @@ module cv32e40p_tracer end end -endmodule : cv32e40p_tracer +endmodule : cv32e40px_tracer `endif // CV32E40P_TRACE_EXECUTION diff --git a/bhv/include/cv32e40p_rvfi_pkg.sv b/bhv/include/cv32e40px_rvfi_pkg.sv similarity index 97% rename from bhv/include/cv32e40p_rvfi_pkg.sv rename to bhv/include/cv32e40px_rvfi_pkg.sv index 688795690..9a131a68b 100644 --- a/bhv/include/cv32e40p_rvfi_pkg.sv +++ b/bhv/include/cv32e40px_rvfi_pkg.sv @@ -20,8 +20,8 @@ // Halfdan Bechmann, Silicon Labs // Yoann Pruvost, Dolphin Design -package cv32e40p_rvfi_pkg; - import cv32e40p_pkg::*; +package cv32e40px_rvfi_pkg; + import cv32e40px_pkg::*; // RVFI only supports MHPMCOUNTER_WIDTH == 64 parameter MHPMCOUNTER_WORDS = MHPMCOUNTER_WIDTH / 32; @@ -123,4 +123,4 @@ package cv32e40p_rvfi_pkg; logic trap; } rvfi_trap_t; -endpackage // cv32e40p_rvfi_pkg +endpackage // cv32e40px_rvfi_pkg diff --git a/bhv/include/cv32e40p_tracer_pkg.sv b/bhv/include/cv32e40px_tracer_pkg.sv similarity index 99% rename from bhv/include/cv32e40p_tracer_pkg.sv rename to bhv/include/cv32e40px_tracer_pkg.sv index 18e503f3b..e1a2a641a 100644 --- a/bhv/include/cv32e40p_tracer_pkg.sv +++ b/bhv/include/cv32e40px_tracer_pkg.sv @@ -19,8 +19,8 @@ // Contributors: Steve Richmond, Silicon Labs // Pascal Gouedo, Dolphin Design -package cv32e40p_tracer_pkg; - import cv32e40p_pkg::*; +package cv32e40px_tracer_pkg; + import cv32e40px_pkg::*; // settings parameter bit SymbolicRegs = 0; // show abi names for registers diff --git a/rtl/cv32e40px_aligner.sv b/rtl/cv32e40px_aligner.sv index a61f7e928..290d1edff 100644 --- a/rtl/cv32e40px_aligner.sv +++ b/rtl/cv32e40px_aligner.sv @@ -20,7 +20,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_aligner ( +module cv32e40px_aligner ( input logic clk, input logic rst_n, diff --git a/rtl/cv32e40px_alu.sv b/rtl/cv32e40px_alu.sv index aa900a787..2d33dbaa3 100644 --- a/rtl/cv32e40px_alu.sv +++ b/rtl/cv32e40px_alu.sv @@ -25,8 +25,8 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_alu - import cv32e40p_pkg::*; +module cv32e40px_alu + import cv32e40px_pkg::*; ( input logic clk, input logic rst_n, @@ -741,7 +741,7 @@ module cv32e40p_alu logic [ 4:0] fl1_result; // holds the index of the last '1' logic [ 5:0] bitop_result; // result of all bitop operations muxed together - cv32e40p_popcnt popcnt_i ( + cv32e40px_popcnt popcnt_i ( .in_i (operand_a_i), .result_o(cnt_result) ); @@ -761,7 +761,7 @@ module cv32e40p_alu endcase end - cv32e40p_ff_one ff_one_i ( + cv32e40px_ff_one ff_one_i ( .in_i (ff_input), .first_one_o(ff1_result), .no_ones_o (ff_no_one) @@ -895,7 +895,7 @@ module cv32e40p_alu (operator_i == ALU_REM) || (operator_i == ALU_REMU)); // inputs A and B are swapped - cv32e40p_alu_div alu_div_i ( + cv32e40px_alu_div alu_div_i ( .Clk_CI (clk), .Rst_RBI(rst_n), diff --git a/rtl/cv32e40px_alu_div.sv b/rtl/cv32e40px_alu_div.sv index a7449e01c..5b6281fbe 100644 --- a/rtl/cv32e40px_alu_div.sv +++ b/rtl/cv32e40px_alu_div.sv @@ -23,7 +23,7 @@ // /////////////////////////////////////////////////////////////////////////////// -module cv32e40p_alu_div #( +module cv32e40px_alu_div #( parameter C_WIDTH = 32, parameter C_LOG_WIDTH = 6 ) ( diff --git a/rtl/cv32e40px_apu_disp.sv b/rtl/cv32e40px_apu_disp.sv index adc9a3485..51d323781 100644 --- a/rtl/cv32e40px_apu_disp.sv +++ b/rtl/cv32e40px_apu_disp.sv @@ -22,7 +22,7 @@ // interconnect. // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_apu_disp ( +module cv32e40px_apu_disp ( input logic clk_i, input logic rst_ni, diff --git a/rtl/cv32e40px_compressed_decoder.sv b/rtl/cv32e40px_compressed_decoder.sv index 4621c754d..1ce411fd8 100644 --- a/rtl/cv32e40px_compressed_decoder.sv +++ b/rtl/cv32e40px_compressed_decoder.sv @@ -24,7 +24,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_compressed_decoder #( +module cv32e40px_compressed_decoder #( parameter FPU = 0, parameter ZFINX = 0 ) ( @@ -34,7 +34,7 @@ module cv32e40p_compressed_decoder #( output logic illegal_instr_o ); - import cv32e40p_pkg::*; + import cv32e40px_pkg::*; ////////////////////////////////////////////////////////////////////////////////////////////////////// // ____ _ ____ _ // diff --git a/rtl/cv32e40px_controller.sv b/rtl/cv32e40px_controller.sv index 672e3e12b..a5b611d16 100644 --- a/rtl/cv32e40px_controller.sv +++ b/rtl/cv32e40px_controller.sv @@ -28,7 +28,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_controller import cv32e40p_pkg::*; +module cv32e40px_controller import cv32e40px_pkg::*; #( parameter COREV_CLUSTER = 0, parameter COREV_PULP = 1 @@ -1587,4 +1587,4 @@ endgenerate `endif -endmodule // cv32e40p_controller +endmodule // cv32e40px_controller diff --git a/rtl/cv32e40px_core.sv b/rtl/cv32e40px_core.sv index 9bc0fef4d..2991b77f6 100644 --- a/rtl/cv32e40px_core.sv +++ b/rtl/cv32e40px_core.sv @@ -28,9 +28,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_core - import cv32e40p_apu_core_pkg::*; - import cv32e40p_core_v_xif_pkg::*; +module cv32e40px_core + import cv32e40px_apu_core_pkg::*; + import cv32e40px_core_v_xif_pkg::*; #( parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) @@ -135,7 +135,7 @@ module cv32e40p_core output logic core_sleep_o ); - import cv32e40p_pkg::*; + import cv32e40px_pkg::*; // Unused parameters and signals (left in code for future design extensions) localparam PULP_SECURE = 0; @@ -419,7 +419,7 @@ module cv32e40p_core logic clk; logic fetch_enable; - cv32e40p_sleep_unit #( + cv32e40px_sleep_unit #( .COREV_CLUSTER(COREV_CLUSTER) ) sleep_unit_i ( // Clock, reset interface @@ -460,7 +460,7 @@ module cv32e40p_core // |___|_| |____/ |_/_/ \_\____|_____| // // // ////////////////////////////////////////////////// - cv32e40p_if_stage #( + cv32e40px_if_stage #( .COREV_PULP (COREV_PULP), .PULP_OBI (PULP_OBI), .PULP_SECURE(PULP_SECURE), @@ -557,7 +557,7 @@ module cv32e40p_core // |___|____/ |____/ |_/_/ \_\____|_____| // // // ///////////////////////////////////////////////// - cv32e40p_id_stage #( + cv32e40px_id_stage #( .COREV_X_IF (COREV_X_IF), .COREV_PULP (COREV_PULP), .COREV_CLUSTER (COREV_CLUSTER), @@ -823,7 +823,7 @@ module cv32e40p_core // |_____/_/\_\ |____/ |_/_/ \_\____|_____| // // // ///////////////////////////////////////////////////// - cv32e40p_ex_stage #( + cv32e40px_ex_stage #( .FPU (FPU), .APU_NARGS_CPU (APU_NARGS_CPU), .APU_WOP_CPU (APU_WOP_CPU), @@ -963,7 +963,7 @@ module cv32e40p_core // // //////////////////////////////////////////////////////////////////////////////////////// - cv32e40p_load_store_unit #( + cv32e40px_load_store_unit #( .PULP_OBI(PULP_OBI) ) load_store_unit_i ( .clk (clk), @@ -1027,7 +1027,7 @@ module cv32e40p_core // Control and Status Registers // ////////////////////////////////////// - cv32e40p_cs_registers #( + cv32e40px_cs_registers #( .N_HWLP (N_HWLP), .A_EXTENSION (A_EXTENSION), .FPU (FPU), @@ -1150,7 +1150,7 @@ module cv32e40p_core generate if (PULP_SECURE && USE_PMP) begin : gen_pmp - cv32e40p_pmp #( + cv32e40px_pmp #( .N_PMP_ENTRIES(N_PMP_ENTRIES) ) pmp_unit_i ( .clk (clk), diff --git a/rtl/cv32e40px_cs_registers.sv b/rtl/cv32e40px_cs_registers.sv index 23ede7970..1f1d56b81 100644 --- a/rtl/cv32e40px_cs_registers.sv +++ b/rtl/cv32e40px_cs_registers.sv @@ -27,8 +27,8 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_cs_registers - import cv32e40p_pkg::*; +module cv32e40px_cs_registers + import cv32e40px_pkg::*; #( parameter N_HWLP = 2, parameter APU = 0, @@ -280,7 +280,7 @@ module cv32e40p_cs_registers //////////////////////////////////////////// // NOTE!!!: Any new CSR register added in this file must also be - // added to the valid CSR register list cv32e40p_decoder.v + // added to the valid CSR register list cv32e40px_decoder.v genvar j; diff --git a/rtl/cv32e40px_decoder.sv b/rtl/cv32e40px_decoder.sv index d03027bae..3d55fdbc8 100644 --- a/rtl/cv32e40px_decoder.sv +++ b/rtl/cv32e40px_decoder.sv @@ -25,10 +25,10 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_decoder - import cv32e40p_pkg::*; - import cv32e40p_apu_core_pkg::*; - import cv32e40p_fpu_pkg::*; +module cv32e40px_decoder + import cv32e40px_pkg::*; + import cv32e40px_apu_core_pkg::*; + import cv32e40px_fpu_pkg::*; #( parameter COREV_PULP = 1, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) parameter COREV_CLUSTER = 0, // PULP ISA Extension cv.elw (need COREV_PULP = 1) @@ -109,9 +109,9 @@ module cv32e40p_decoder input logic fs_off_i, // Floating-Point State field from MSTATUS input logic [C_RM-1:0] frm_i, // Rounding mode from float CSR - output logic [cv32e40p_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_dst_fmt_o, // fpu destination format - output logic [cv32e40p_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_src_fmt_o, // fpu source format - output logic [cv32e40p_fpu_pkg::INT_FORMAT_BITS-1:0] fpu_int_fmt_o, // fpu integer format (for casts) + output logic [cv32e40px_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_dst_fmt_o, // fpu destination format + output logic [cv32e40px_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_src_fmt_o, // fpu source format + output logic [cv32e40px_fpu_pkg::INT_FORMAT_BITS-1:0] fpu_int_fmt_o, // fpu integer format (for casts) // APU output logic apu_en_o, @@ -179,7 +179,7 @@ module cv32e40p_decoder // this instruction needs floating-point rounding-mode verification logic check_fprm; - logic [cv32e40p_fpu_pkg::OP_BITS-1:0] fpu_op; // fpu operation + logic [cv32e40px_fpu_pkg::OP_BITS-1:0] fpu_op; // fpu operation logic fpu_op_mod; // fpu operation modifier logic fpu_vec_op; // fpu vectorial operation // unittypes for latencies to help us decode for APU @@ -225,12 +225,12 @@ module cv32e40p_decoder apu_op_o = '0; apu_lat_o = '0; fp_rnd_mode_o = '0; - fpu_op = cv32e40p_fpu_pkg::SGNJ; + fpu_op = cv32e40px_fpu_pkg::SGNJ; fpu_op_mod = 1'b0; fpu_vec_op = 1'b0; - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP32; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP32; - fpu_int_fmt_o = cv32e40p_fpu_pkg::INT32; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP32; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP32; + fpu_int_fmt_o = cv32e40px_fpu_pkg::INT32; check_fprm = 1'b0; fp_op_group = ADDMUL; @@ -555,22 +555,22 @@ module cv32e40p_decoder unique case (instr_rdata_i[13:12]) // FP32 2'b00: begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP32; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP32; alu_vec_mode_o = VEC_MODE32; end // FP16ALT 2'b01: begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; alu_vec_mode_o = VEC_MODE16; end // FP16 2'b10: begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16; alu_vec_mode_o = VEC_MODE16; end // FP8 2'b11: begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP8; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP8; alu_vec_mode_o = VEC_MODE8; end endcase @@ -582,7 +582,7 @@ module cv32e40p_decoder unique case (instr_rdata_i[29:25]) inside // vfadd.vfmt - Vectorial FP Addition 5'b00001: begin - fpu_op = cv32e40p_fpu_pkg::ADD; + fpu_op = cv32e40px_fpu_pkg::ADD; fp_op_group = ADDMUL; // FPnew needs addition operands as operand B and C alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; @@ -592,7 +592,7 @@ module cv32e40p_decoder end // vfsub.vfmt - Vectorial FP Subtraction 5'b00010: begin - fpu_op = cv32e40p_fpu_pkg::ADD; + fpu_op = cv32e40px_fpu_pkg::ADD; fpu_op_mod = 1'b1; fp_op_group = ADDMUL; // FPnew needs addition operands as operand B and C @@ -603,24 +603,24 @@ module cv32e40p_decoder end // vfmul.vfmt - Vectorial FP Multiplication 5'b00011: begin - fpu_op = cv32e40p_fpu_pkg::MUL; + fpu_op = cv32e40px_fpu_pkg::MUL; fp_op_group = ADDMUL; end // vfdiv.vfmt - Vectorial FP Division 5'b00100: begin - fpu_op = cv32e40p_fpu_pkg::DIV; + fpu_op = cv32e40px_fpu_pkg::DIV; fp_op_group = DIVSQRT; end // vfmin.vfmt - Vectorial FP Minimum 5'b00101: begin - fpu_op = cv32e40p_fpu_pkg::MINMAX; + fpu_op = cv32e40px_fpu_pkg::MINMAX; fp_rnd_mode_o = 3'b000; // min fp_op_group = NONCOMP; check_fprm = 1'b0; // instruction encoded in rm end // vfmax.vfmt - Vectorial FP Maximum 5'b00110: begin - fpu_op = cv32e40p_fpu_pkg::MINMAX; + fpu_op = cv32e40px_fpu_pkg::MINMAX; fp_rnd_mode_o = 3'b001; // max fp_op_group = NONCOMP; check_fprm = 1'b0; // instruction encoded in rm @@ -628,7 +628,7 @@ module cv32e40p_decoder // vfsqrt.vfmt - Vectorial FP Square Root 5'b00111: begin regb_used_o = 1'b0; - fpu_op = cv32e40p_fpu_pkg::SQRT; + fpu_op = cv32e40px_fpu_pkg::SQRT; fp_op_group = DIVSQRT; // rs2 and R must be zero if ((instr_rdata_i[24:20] != 5'b00000) || instr_rdata_i[14]) begin @@ -644,7 +644,7 @@ module cv32e40p_decoder end else begin reg_fp_c_o = 1'b0; end - fpu_op = cv32e40p_fpu_pkg::FMADD; + fpu_op = cv32e40px_fpu_pkg::FMADD; fp_op_group = ADDMUL; end // vfmre.vfmt - Vectorial FP Multiply-Reduce @@ -656,7 +656,7 @@ module cv32e40p_decoder end else begin reg_fp_c_o = 1'b0; end - fpu_op = cv32e40p_fpu_pkg::FMADD; + fpu_op = cv32e40px_fpu_pkg::FMADD; fpu_op_mod = 1'b1; fp_op_group = ADDMUL; end @@ -669,7 +669,7 @@ module cv32e40p_decoder // vfmv.{x.vfmt/vfmt.x} - Vectorial FP Reg <-> GP Reg Moves 5'b00000: begin alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit - fpu_op = cv32e40p_fpu_pkg::SGNJ; + fpu_op = cv32e40px_fpu_pkg::SGNJ; fp_rnd_mode_o = 3'b011; // passthrough without checking nan-box fp_op_group = NONCOMP; check_fprm = 1'b0; @@ -687,7 +687,7 @@ module cv32e40p_decoder // vfclass.vfmt - Vectorial FP Classifications 5'b00001: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CLASSIFY; + fpu_op = cv32e40px_fpu_pkg::CLASSIFY; fp_rnd_mode_o = 3'b000; fp_op_group = NONCOMP; check_fprm = 1'b0; @@ -701,45 +701,45 @@ module cv32e40p_decoder // Integer width matches FP width unique case (instr_rdata_i[13:12]) // FP32 - 2'b00 : fpu_int_fmt_o = cv32e40p_fpu_pkg::INT32; + 2'b00 : fpu_int_fmt_o = cv32e40px_fpu_pkg::INT32; // FP16[ALT] 2'b01, - 2'b10: fpu_int_fmt_o = cv32e40p_fpu_pkg::INT16; + 2'b10: fpu_int_fmt_o = cv32e40px_fpu_pkg::INT16; // FP8 - 2'b11: fpu_int_fmt_o = cv32e40p_fpu_pkg::INT8; + 2'b11: fpu_int_fmt_o = cv32e40px_fpu_pkg::INT8; endcase // Int to FP conversion if (instr_rdata_i[20]) begin reg_fp_a_o = 1'b0; // go from integer regfile - fpu_op = cv32e40p_fpu_pkg::I2F; + fpu_op = cv32e40px_fpu_pkg::I2F; end // FP to Int conversion else begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::F2I; + fpu_op = cv32e40px_fpu_pkg::F2I; end end // vfcvt.vfmt.vfmt - Vectorial FP <-> FP Conversions 5'b001??: begin - fpu_op = cv32e40p_fpu_pkg::F2F; + fpu_op = cv32e40px_fpu_pkg::F2F; fp_op_group = CONV; // check source format unique case (instr_rdata_i[21:20]) // Only process instruction if corresponding extension is active (static) 2'b00: begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP32; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP32; if (~C_RVF) illegal_insn_o = 1'b1; end 2'b01: begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; if (~C_XF16ALT) illegal_insn_o = 1'b1; end 2'b10: begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16; if (~C_XF16) illegal_insn_o = 1'b1; end 2'b11: begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP8; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP8; if (~C_XF8) illegal_insn_o = 1'b1; end endcase @@ -752,21 +752,21 @@ module cv32e40p_decoder end // vfsgnj.vfmt - Vectorial FP Sign Injection 5'b01101: begin - fpu_op = cv32e40p_fpu_pkg::SGNJ; + fpu_op = cv32e40px_fpu_pkg::SGNJ; fp_rnd_mode_o = 3'b000; // sgnj fp_op_group = NONCOMP; check_fprm = 1'b0; end // vfsgnjn.vfmt - Vectorial FP Negated Sign Injection 5'b01110: begin - fpu_op = cv32e40p_fpu_pkg::SGNJ; + fpu_op = cv32e40px_fpu_pkg::SGNJ; fp_rnd_mode_o = 3'b001; // sgnjn fp_op_group = NONCOMP; check_fprm = 1'b0; end // vfsgnjx.vfmt - Vectorial FP Xored Sign Injection 5'b01111: begin - fpu_op = cv32e40p_fpu_pkg::SGNJ; + fpu_op = cv32e40px_fpu_pkg::SGNJ; fp_rnd_mode_o = 3'b010; // sgnjx fp_op_group = NONCOMP; check_fprm = 1'b0; @@ -774,7 +774,7 @@ module cv32e40p_decoder // vfeq.vfmt - Vectorial FP Equals 5'b10000: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fp_rnd_mode_o = 3'b010; // eq fp_op_group = NONCOMP; check_fprm = 1'b0; @@ -782,7 +782,7 @@ module cv32e40p_decoder // vfne.vfmt - Vectorial FP Not Equals 5'b10001: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fpu_op_mod = 1'b1; // invert output fp_rnd_mode_o = 3'b010; // eq fp_op_group = NONCOMP; @@ -791,7 +791,7 @@ module cv32e40p_decoder // vflt.vfmt - Vectorial FP Less Than 5'b10010: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fp_rnd_mode_o = 3'b001; // lt fp_op_group = NONCOMP; check_fprm = 1'b0; @@ -799,7 +799,7 @@ module cv32e40p_decoder // vfge.vfmt - Vectorial FP Greater Than or Equals 5'b10011: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fpu_op_mod = 1'b1; // invert output fp_rnd_mode_o = 3'b001; // lt fp_op_group = NONCOMP; @@ -808,7 +808,7 @@ module cv32e40p_decoder // vfle.vfmt - Vectorial FP Less Than or Equals 5'b10100: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fp_rnd_mode_o = 3'b000; // le fp_op_group = NONCOMP; check_fprm = 1'b0; @@ -816,7 +816,7 @@ module cv32e40p_decoder // vfgt.vfmt - Vectorial FP Greater Than 5'b10101: begin reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fpu_op_mod = 1'b1; // invert output fp_rnd_mode_o = 3'b000; // le fp_op_group = NONCOMP; @@ -829,28 +829,28 @@ module cv32e40p_decoder fp_op_group = CONV; scalar_replication_o = 1'b0; - if (instr_rdata_i[25]) fpu_op = cv32e40p_fpu_pkg::CPKCD; // vfcpk{c/d} - else fpu_op = cv32e40p_fpu_pkg::CPKAB; // vfcpk{a/b} + if (instr_rdata_i[25]) fpu_op = cv32e40px_fpu_pkg::CPKCD; // vfcpk{c/d} + else fpu_op = cv32e40px_fpu_pkg::CPKAB; // vfcpk{a/b} // vfcpk{a-d}.vfmt.d - from double if (instr_rdata_i[26]) begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP64; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP64; if (~C_RVD) illegal_insn_o = 1'b1; end // vfcpk{a-d}.vfmt.s else begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP32; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP32; if (~C_RVF) illegal_insn_o = 1'b1; end // Resolve legal vfcpk / format combinations (mostly static) - if (fpu_op == cv32e40p_fpu_pkg::CPKCD) begin // vfcpk{c/d} not possible unless FP8 and FLEN>=64 + if (fpu_op == cv32e40px_fpu_pkg::CPKCD) begin // vfcpk{c/d} not possible unless FP8 and FLEN>=64 if (~C_XF8 || ~C_RVD) illegal_insn_o = 1'b1; end else begin if (instr_rdata_i[14]) begin // vfcpkb // vfcpkb not possible for FP32 - if (fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP32) illegal_insn_o = 1'b1; + if (fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP32) illegal_insn_o = 1'b1; // vfcpkb not possible for FP16[ALT] if not RVD - if (~C_RVD && (fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP8)) illegal_insn_o = 1'b1; + if (~C_RVD && (fpu_dst_fmt_o != cv32e40px_fpu_pkg::FP8)) illegal_insn_o = 1'b1; end end end @@ -862,15 +862,15 @@ module cv32e40p_decoder // check enabled formats (static) // need RVD for F vectors - if ((~C_RVF || ~C_RVD) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP32) illegal_insn_o = 1'b1; + if ((~C_RVF || ~C_RVD) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP32) illegal_insn_o = 1'b1; // need RVF for F16 vectors - if ((~C_XF16 || ~C_RVF) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP16) illegal_insn_o = 1'b1; + if ((~C_XF16 || ~C_RVF) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP16) illegal_insn_o = 1'b1; // need RVF for F16 vectors - if ((~C_XF16ALT || ~C_RVF) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP16ALT) begin + if ((~C_XF16ALT || ~C_RVF) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP16ALT) begin illegal_insn_o = 1'b1; end // need F16 for F8 vectors - if ((~C_XF8 || (~C_XF16 && ~C_XF16ALT)) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP8) begin + if ((~C_XF8 || (~C_XF16 && ~C_XF16ALT)) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP8) begin illegal_insn_o = 1'b1; end @@ -889,10 +889,10 @@ module cv32e40p_decoder // ADDMUL has format dependent latency ADDMUL : begin unique case (fpu_dst_fmt_o) - cv32e40p_fpu_pkg::FP32 : apu_lat_o = (FPU_ADDMUL_LAT<2)? FPU_ADDMUL_LAT+1: 2'h3; - cv32e40p_fpu_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; - cv32e40p_fpu_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; - cv32e40p_fpu_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; + cv32e40px_fpu_pkg::FP32 : apu_lat_o = (FPU_ADDMUL_LAT<2)? FPU_ADDMUL_LAT+1: 2'h3; + cv32e40px_fpu_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; + cv32e40px_fpu_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; + cv32e40px_fpu_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; default : ; endcase end @@ -1034,18 +1034,18 @@ module cv32e40p_decoder // Decode Formats (preliminary, can change for some ops) unique case (instr_rdata_i[26:25]) // FP32 - 2'b00: fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP32; + 2'b00: fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP32; // FP64 - 2'b01: fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP64; + 2'b01: fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP64; // FP16 or FP16ALT 2'b10: begin // FP16alt encoded in rm field - if (instr_rdata_i[14:12] == 3'b101) fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + if (instr_rdata_i[14:12] == 3'b101) fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; // this can still change to FP16ALT - else fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16; + else fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16; end // FP8 - 2'b11: fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP8; + 2'b11: fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP8; endcase // By default, src=dst @@ -1055,7 +1055,7 @@ module cv32e40p_decoder unique case (instr_rdata_i[31:27]) // fadd.fmt - FP Addition 5'b00000: begin - fpu_op = cv32e40p_fpu_pkg::ADD; + fpu_op = cv32e40px_fpu_pkg::ADD; fp_op_group = ADDMUL; apu_op_o = 2'b0; alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; @@ -1063,7 +1063,7 @@ module cv32e40p_decoder end // fsub.fmt - FP Subtraction 5'b00001: begin - fpu_op = cv32e40p_fpu_pkg::ADD; + fpu_op = cv32e40px_fpu_pkg::ADD; fpu_op_mod = 1'b1; fp_op_group = ADDMUL; apu_op_o = 2'b1; @@ -1072,18 +1072,18 @@ module cv32e40p_decoder end // fmul.fmt - FP Multiplication 5'b00010: begin - fpu_op = cv32e40p_fpu_pkg::MUL; + fpu_op = cv32e40px_fpu_pkg::MUL; fp_op_group = ADDMUL; end // fdiv.fmt - FP Division 5'b00011: begin - fpu_op = cv32e40p_fpu_pkg::DIV; + fpu_op = cv32e40px_fpu_pkg::DIV; fp_op_group = DIVSQRT; end // fsqrt.fmt - FP Square Root 5'b01011: begin regb_used_o = 1'b0; - fpu_op = cv32e40p_fpu_pkg::SQRT; + fpu_op = cv32e40px_fpu_pkg::SQRT; fp_op_group = DIVSQRT; apu_op_o = 1'b1; // rs2 must be zero @@ -1091,7 +1091,7 @@ module cv32e40p_decoder end // fsgn{j[n]/jx}.fmt - FP Sign Injection 5'b00100: begin - fpu_op = cv32e40p_fpu_pkg::SGNJ; + fpu_op = cv32e40px_fpu_pkg::SGNJ; fp_op_group = NONCOMP; check_fprm = 1'b0; // instruction encoded in rm, do the check here if (C_XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) @@ -1100,8 +1100,8 @@ module cv32e40p_decoder end // FP16ALT uses special encoding here if (instr_rdata_i[14]) begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end else begin fp_rnd_mode_o = {1'b0, instr_rdata_i[13:12]}; end @@ -1111,7 +1111,7 @@ module cv32e40p_decoder end // fmin/fmax.fmt - FP Minimum / Maximum 5'b00101: begin - fpu_op = cv32e40p_fpu_pkg::MINMAX; + fpu_op = cv32e40px_fpu_pkg::MINMAX; fp_op_group = NONCOMP; check_fprm = 1'b0; // instruction encoded in rm, do the check here if (C_XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) @@ -1120,8 +1120,8 @@ module cv32e40p_decoder end // FP16ALT uses special encoding here if (instr_rdata_i[14]) begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end else begin fp_rnd_mode_o = {1'b0, instr_rdata_i[13:12]}; end @@ -1132,7 +1132,7 @@ module cv32e40p_decoder // fcvt.fmt.fmt - FP to FP Conversion 5'b01000: begin regb_used_o = 1'b0; - fpu_op = cv32e40p_fpu_pkg::F2F; + fpu_op = cv32e40px_fpu_pkg::F2F; fp_op_group = CONV; // bits [22:20] used, other bits must be 0 if (instr_rdata_i[24:23]) illegal_insn_o = 1'b1; @@ -1141,23 +1141,23 @@ module cv32e40p_decoder // Only process instruction if corresponding extension is active (static) 3'b000: begin if (!(C_RVF && (C_XF16 || C_XF16ALT || C_XF8))) illegal_insn_o = 1'b1; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP32; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP32; end 3'b001: begin if (~C_RVD) illegal_insn_o = 1'b1; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP64; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP64; end 3'b010: begin if (~C_XF16) illegal_insn_o = 1'b1; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16; end 3'b110: begin if (~C_XF16ALT) illegal_insn_o = 1'b1; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end 3'b011: begin if (~C_XF8) illegal_insn_o = 1'b1; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP8; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP8; end default: illegal_insn_o = 1'b1; endcase @@ -1165,10 +1165,10 @@ module cv32e40p_decoder // fmulex.s.fmt - FP Expanding Multiplication to FP32 5'b01001: begin if (~C_XF16 && ~C_XF16ALT && ~C_XF8) illegal_insn_o = 1; - fpu_op = cv32e40p_fpu_pkg::MUL; + fpu_op = cv32e40px_fpu_pkg::MUL; fp_op_group = ADDMUL; // set dst format to FP32 - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP32; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP32; end // fmacex.s.fmt - FP Expanding Multipy-Accumulate to FP32 5'b01010: begin @@ -1180,14 +1180,14 @@ module cv32e40p_decoder end else begin reg_fp_c_o = 1'b0; end - fpu_op = cv32e40p_fpu_pkg::FMADD; + fpu_op = cv32e40px_fpu_pkg::FMADD; fp_op_group = ADDMUL; // set dst format to FP32 - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP32; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP32; end // feq/flt/fle.fmt - FP Comparisons 5'b10100: begin - fpu_op = cv32e40p_fpu_pkg::CMP; + fpu_op = cv32e40px_fpu_pkg::CMP; fp_op_group = NONCOMP; reg_fp_d_o = 1'b0; // go to integer regfile check_fprm = 1'b0; // instruction encoded in rm, do the check here @@ -1197,8 +1197,8 @@ module cv32e40p_decoder end // FP16ALT uses special encoding here if (instr_rdata_i[14]) begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end else begin fp_rnd_mode_o = {1'b0, instr_rdata_i[13:12]}; end @@ -1210,7 +1210,7 @@ module cv32e40p_decoder 5'b11000: begin regb_used_o = 1'b0; reg_fp_d_o = 1'b0; // go to integer regfile - fpu_op = cv32e40p_fpu_pkg::F2I; + fpu_op = cv32e40px_fpu_pkg::F2I; fp_op_group = CONV; fpu_op_mod = instr_rdata_i[20]; // signed/unsigned switch apu_op_o = 2'b1; @@ -1218,25 +1218,25 @@ module cv32e40p_decoder unique case (instr_rdata_i[26:25]) //fix for casting to different formats other than FP32 2'b00: begin if (~C_RVF) illegal_insn_o = 1; - else fpu_src_fmt_o = cv32e40p_fpu_pkg::FP32; + else fpu_src_fmt_o = cv32e40px_fpu_pkg::FP32; end 2'b01: begin if (~C_RVD) illegal_insn_o = 1; - else fpu_src_fmt_o = cv32e40p_fpu_pkg::FP64; + else fpu_src_fmt_o = cv32e40px_fpu_pkg::FP64; end 2'b10: begin if (instr_rdata_i[14:12] == 3'b101) begin if (~C_XF16ALT) illegal_insn_o = 1; - else fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + else fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end else if (~C_XF16) begin illegal_insn_o = 1; end else begin - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16; end end 2'b11: begin if (~C_XF8) illegal_insn_o = 1; - else fpu_src_fmt_o = cv32e40p_fpu_pkg::FP8; + else fpu_src_fmt_o = cv32e40px_fpu_pkg::FP8; end endcase // unique case (instr_rdata_i[26:25]) // bits [21:20] used, other bits must be 0 @@ -1246,7 +1246,7 @@ module cv32e40p_decoder 5'b11010: begin regb_used_o = 1'b0; reg_fp_a_o = 1'b0; // go from integer regfile - fpu_op = cv32e40p_fpu_pkg::I2F; + fpu_op = cv32e40px_fpu_pkg::I2F; fp_op_group = CONV; fpu_op_mod = instr_rdata_i[20]; // signed/unsigned switch apu_op_o = 2'b0; @@ -1262,22 +1262,22 @@ module cv32e40p_decoder // fmv.x.fmt - FPR to GPR Move if ((ZFINX == 0 && instr_rdata_i[14:12] == 3'b000) || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100)) begin alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit - fpu_op = cv32e40p_fpu_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding + fpu_op = cv32e40px_fpu_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding fpu_op_mod = 1'b1; // sign-extend result fp_rnd_mode_o = 3'b011; // passthrough without checking nan-box // FP16ALT uses special encoding here if (instr_rdata_i[14]) begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end // fclass.fmt - FP Classify end else if (instr_rdata_i[14:12] == 3'b001 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b101)) begin - fpu_op = cv32e40p_fpu_pkg::CLASSIFY; + fpu_op = cv32e40px_fpu_pkg::CLASSIFY; fp_rnd_mode_o = 3'b000; // FP16ALT uses special encoding here if (instr_rdata_i[14]) begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end end else begin illegal_insn_o = 1'b1; @@ -1290,7 +1290,7 @@ module cv32e40p_decoder regb_used_o = 1'b0; reg_fp_a_o = 1'b0; // go from integer regfile alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit - fpu_op = cv32e40p_fpu_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding + fpu_op = cv32e40px_fpu_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding fpu_op_mod = 1'b0; // nan-box result fp_op_group = NONCOMP; fp_rnd_mode_o = 3'b011; // passthrough without checking nan-box @@ -1298,8 +1298,8 @@ module cv32e40p_decoder if ((ZFINX == 0 && instr_rdata_i[14:12] == 3'b000) || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100)) begin // FP16ALT uses special encoding here if (instr_rdata_i[14]) begin - fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - fpu_src_fmt_o = cv32e40p_fpu_pkg::FP16ALT; + fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + fpu_src_fmt_o = cv32e40px_fpu_pkg::FP16ALT; end end else begin illegal_insn_o = 1'b1; @@ -1312,20 +1312,20 @@ module cv32e40p_decoder endcase // check enabled formats (static) - if (~C_RVF && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP32) illegal_insn_o = 1'b1; - if ((~C_RVD) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP64) illegal_insn_o = 1'b1; - if ((~C_XF16) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP16) illegal_insn_o = 1'b1; - if ((~C_XF16ALT) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP16ALT) begin + if (~C_RVF && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP32) illegal_insn_o = 1'b1; + if ((~C_RVD) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP64) illegal_insn_o = 1'b1; + if ((~C_XF16) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP16) illegal_insn_o = 1'b1; + if ((~C_XF16ALT) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP16ALT) begin illegal_insn_o = 1'b1; end - if ((~C_XF8) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP8) illegal_insn_o = 1'b1; + if ((~C_XF8) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP8) illegal_insn_o = 1'b1; // check rounding mode if (check_fprm) begin unique case (instr_rdata_i[14:12]) inside [3'b000:3'b100]: ; //legal rounding modes 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 - if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1; + if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40px_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1; // actual rounding mode from frm csr unique case (frm_i) inside [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes @@ -1350,11 +1350,11 @@ module cv32e40p_decoder // ADDMUL has format dependent latency ADDMUL : begin unique case (fpu_dst_fmt_o) - cv32e40p_fpu_pkg::FP32 : apu_lat_o = (FPU_ADDMUL_LAT<2)? FPU_ADDMUL_LAT+1: 2'h3; - cv32e40p_fpu_pkg::FP64 : apu_lat_o = (C_LAT_FP64<2) ? C_LAT_FP64+1 : 2'h3; - cv32e40p_fpu_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; - cv32e40p_fpu_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; - cv32e40p_fpu_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; + cv32e40px_fpu_pkg::FP32 : apu_lat_o = (FPU_ADDMUL_LAT<2)? FPU_ADDMUL_LAT+1: 2'h3; + cv32e40px_fpu_pkg::FP64 : apu_lat_o = (C_LAT_FP64<2) ? C_LAT_FP64+1 : 2'h3; + cv32e40px_fpu_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; + cv32e40px_fpu_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; + cv32e40px_fpu_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; default : ; endcase end @@ -1405,17 +1405,17 @@ module cv32e40p_decoder // Decode Formats unique case (instr_rdata_i[26:25]) // FP32 - 2'b00 : fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP32; + 2'b00 : fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP32; // FP64 - 2'b01 : fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP64; + 2'b01 : fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP64; // FP16 or FP16ALT 2'b10 : begin // FP16alt encoded in rm field - if (instr_rdata_i[14:12] == 3'b101) fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16ALT; - else fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP16; + if (instr_rdata_i[14:12] == 3'b101) fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16ALT; + else fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP16; end // FP8 - 2'b11 : fpu_dst_fmt_o = cv32e40p_fpu_pkg::FP8; + 2'b11 : fpu_dst_fmt_o = cv32e40px_fpu_pkg::FP8; endcase // By default, src=dst @@ -1425,23 +1425,23 @@ module cv32e40p_decoder unique case (instr_rdata_i[6:0]) // fmadd.fmt - FP Fused multiply-add OPCODE_OP_FMADD : begin - fpu_op = cv32e40p_fpu_pkg::FMADD; + fpu_op = cv32e40px_fpu_pkg::FMADD; apu_op_o = 2'b00; end // fmsub.fmt - FP Fused multiply-subtract OPCODE_OP_FMSUB : begin - fpu_op = cv32e40p_fpu_pkg::FMADD; + fpu_op = cv32e40px_fpu_pkg::FMADD; fpu_op_mod = 1'b1; apu_op_o = 2'b01; end // fnmsub.fmt - FP Negated fused multiply-subtract OPCODE_OP_FNMSUB : begin - fpu_op = cv32e40p_fpu_pkg::FNMSUB; + fpu_op = cv32e40px_fpu_pkg::FNMSUB; apu_op_o = 2'b10; end // fnmadd.fmt - FP Negated fused multiply-add OPCODE_OP_FNMADD : begin - fpu_op = cv32e40p_fpu_pkg::FNMSUB; + fpu_op = cv32e40px_fpu_pkg::FNMSUB; fpu_op_mod = 1'b1; apu_op_o = 2'b11; end @@ -1449,19 +1449,19 @@ module cv32e40p_decoder endcase // check enabled formats (static) - if (~C_RVF && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP32) illegal_insn_o = 1'b1; - if ((~C_RVD) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP64) illegal_insn_o = 1'b1; - if ((~C_XF16) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP16) illegal_insn_o = 1'b1; - if ((~C_XF16ALT) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP16ALT) begin + if (~C_RVF && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP32) illegal_insn_o = 1'b1; + if ((~C_RVD) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP64) illegal_insn_o = 1'b1; + if ((~C_XF16) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP16) illegal_insn_o = 1'b1; + if ((~C_XF16ALT) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP16ALT) begin illegal_insn_o = 1'b1; end - if ((~C_XF8) && fpu_dst_fmt_o == cv32e40p_fpu_pkg::FP8) illegal_insn_o = 1'b1; + if ((~C_XF8) && fpu_dst_fmt_o == cv32e40px_fpu_pkg::FP8) illegal_insn_o = 1'b1; // check rounding mode unique case (instr_rdata_i[14:12]) inside [3'b000:3'b100]: ; //legal rounding modes 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 - if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1; + if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40px_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1; // actual rounding mode from frm csr unique case (frm_i) inside [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes @@ -1483,11 +1483,11 @@ module cv32e40p_decoder // 1 = single cycle (no latency), 2 = one pipestage, 3 = two or more pipestages // format dependent latency unique case (fpu_dst_fmt_o) - cv32e40p_fpu_pkg::FP32 : apu_lat_o = (FPU_ADDMUL_LAT<2)? FPU_ADDMUL_LAT+1: 2'h3; - cv32e40p_fpu_pkg::FP64 : apu_lat_o = (C_LAT_FP64<2) ? C_LAT_FP64+1 : 2'h3; - cv32e40p_fpu_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; - cv32e40p_fpu_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; - cv32e40p_fpu_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; + cv32e40px_fpu_pkg::FP32 : apu_lat_o = (FPU_ADDMUL_LAT<2)? FPU_ADDMUL_LAT+1: 2'h3; + cv32e40px_fpu_pkg::FP64 : apu_lat_o = (C_LAT_FP64<2) ? C_LAT_FP64+1 : 2'h3; + cv32e40px_fpu_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; + cv32e40px_fpu_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; + cv32e40px_fpu_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; default : ; endcase @@ -2994,4 +2994,4 @@ module cv32e40p_decoder assign ctrl_transfer_insn_in_dec_o = ctrl_transfer_insn; assign regfile_alu_we_dec_o = regfile_alu_we; -endmodule // cv32e40p_decoder +endmodule // cv32e40px_decoder diff --git a/rtl/cv32e40px_ex_stage.sv b/rtl/cv32e40px_ex_stage.sv index bd4128017..1ce3d629a 100644 --- a/rtl/cv32e40px_ex_stage.sv +++ b/rtl/cv32e40px_ex_stage.sv @@ -29,10 +29,10 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_ex_stage - import cv32e40p_pkg::*; - import cv32e40p_apu_core_pkg::*; - import cv32e40p_core_v_xif_pkg::*; +module cv32e40px_ex_stage + import cv32e40px_pkg::*; + import cv32e40px_apu_core_pkg::*; + import cv32e40px_core_v_xif_pkg::*; #( parameter FPU = 0, parameter APU_NARGS_CPU = 3, @@ -270,7 +270,7 @@ module cv32e40p_ex_stage // // //////////////////////////// - cv32e40p_alu alu_i ( + cv32e40px_alu alu_i ( .clk (clk), .rst_n (rst_n), .enable_i (alu_en_i), @@ -305,7 +305,7 @@ module cv32e40p_ex_stage // // //////////////////////////////////////////////////////////////// - cv32e40p_mult mult_i ( + cv32e40px_mult mult_i ( .clk (clk), .rst_n(rst_n), @@ -346,7 +346,7 @@ module cv32e40p_ex_stage // // //////////////////////////////////////////////////// - cv32e40p_apu_disp apu_disp_i ( + cv32e40px_apu_disp apu_disp_i ( .clk_i (clk), .rst_ni(rst_n), diff --git a/rtl/cv32e40px_ff_one.sv b/rtl/cv32e40px_ff_one.sv index 57461c611..89e971d59 100644 --- a/rtl/cv32e40px_ff_one.sv +++ b/rtl/cv32e40px_ff_one.sv @@ -14,7 +14,7 @@ // Additional contributions by: // // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // -// Design Name: cv32e40p_ff_one // +// Design Name: cv32e40px_ff_one // // Project Name: RI5CY // // Language: SystemVerilog // // // @@ -22,7 +22,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_ff_one #( +module cv32e40px_ff_one #( parameter LEN = 32 ) ( input logic [LEN-1:0] in_i, diff --git a/rtl/cv32e40px_fifo.sv b/rtl/cv32e40px_fifo.sv index 496ac4ce0..65b8315e3 100644 --- a/rtl/cv32e40px_fifo.sv +++ b/rtl/cv32e40px_fifo.sv @@ -12,7 +12,7 @@ // Copy of fifo_v3 from https://github.com/pulp-platform/common_cells b2a4b2d3decdfc152ad9b4564a48ed3b2649fd6c -module cv32e40p_fifo #( +module cv32e40px_fifo #( parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 @@ -165,4 +165,4 @@ module cv32e40p_fifo #( else $fatal(1, "Trying to pop data although the FIFO is empty."); `endif -endmodule // cv32e40p_fifo +endmodule // cv32e40px_fifo diff --git a/rtl/cv32e40px_fp_wrapper.sv b/rtl/cv32e40px_fp_wrapper.sv index 042fa0f22..8502e3418 100644 --- a/rtl/cv32e40px_fp_wrapper.sv +++ b/rtl/cv32e40px_fp_wrapper.sv @@ -11,8 +11,8 @@ // Wrapper for a fpnew // Contributor: Davide Schiavone -module cv32e40p_fp_wrapper - import cv32e40p_apu_core_pkg::*; +module cv32e40px_fp_wrapper + import cv32e40px_apu_core_pkg::*; #( parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number parameter FPU_OTHERS_LAT = 0 // Floating-Point COMParison/CONVersion computing lanes pipeline registers number @@ -37,7 +37,7 @@ module cv32e40p_fp_wrapper ); - import cv32e40p_pkg::*; + import cv32e40px_pkg::*; import fpnew_pkg::*; logic [ fpnew_pkg::OP_BITS-1:0] fpu_op; @@ -123,5 +123,5 @@ module cv32e40p_fp_wrapper .busy_o ( /* unused */) ); -endmodule // cv32e40p_fp_wrapper +endmodule // cv32e40px_fp_wrapper diff --git a/rtl/cv32e40px_hwloop_regs.sv b/rtl/cv32e40px_hwloop_regs.sv index fc835fbe4..f131de8bf 100644 --- a/rtl/cv32e40px_hwloop_regs.sv +++ b/rtl/cv32e40px_hwloop_regs.sv @@ -22,7 +22,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_hwloop_regs #( +module cv32e40px_hwloop_regs #( parameter N_REGS = 2, parameter N_REG_BITS = $clog2(N_REGS) ) ( diff --git a/rtl/cv32e40px_id_stage.sv b/rtl/cv32e40px_id_stage.sv index 27bc35ad4..23cb2f8e5 100644 --- a/rtl/cv32e40px_id_stage.sv +++ b/rtl/cv32e40px_id_stage.sv @@ -27,9 +27,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_id_stage - import cv32e40p_pkg::*; - import cv32e40p_apu_core_pkg::*; +module cv32e40px_id_stage + import cv32e40px_pkg::*; + import cv32e40px_apu_core_pkg::*; #( parameter COREV_X_IF = 0, parameter COREV_PULP = 1, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) @@ -405,9 +405,9 @@ module cv32e40p_id_stage logic [1:0] mult_dot_signed; // Signed mode dot products (can be mixed types) // FPU signals - logic [cv32e40p_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_src_fmt; - logic [cv32e40p_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_dst_fmt; - logic [cv32e40p_fpu_pkg::INT_FORMAT_BITS-1:0] fpu_int_fmt; + logic [cv32e40px_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_src_fmt; + logic [cv32e40px_fpu_pkg::FP_FORMAT_BITS-1:0] fpu_dst_fmt; + logic [cv32e40px_fpu_pkg::INT_FORMAT_BITS-1:0] fpu_int_fmt; // APU signals logic apu_en; @@ -953,7 +953,7 @@ module cv32e40p_id_stage // // ///////////////////////////////////////////////////////// - cv32e40p_register_file #( + cv32e40px_register_file #( .ADDR_WIDTH(6), .DATA_WIDTH(32), .FPU (FPU), @@ -1000,7 +1000,7 @@ module cv32e40p_id_stage // // //////////////////////////////////////// - cv32e40p_x_disp x_disp_i ( + cv32e40px_x_disp x_disp_i ( // clock and reset .clk_i (clk), .rst_ni(rst_n), @@ -1143,7 +1143,7 @@ module cv32e40p_id_stage // // /////////////////////////////////////////////// - cv32e40p_decoder #( + cv32e40px_decoder #( .COREV_PULP (COREV_PULP), .COREV_CLUSTER (COREV_CLUSTER), .A_EXTENSION (A_EXTENSION), @@ -1282,7 +1282,7 @@ module cv32e40p_id_stage // // //////////////////////////////////////////////////////////////////// - cv32e40p_controller #( + cv32e40px_controller #( .COREV_CLUSTER(COREV_CLUSTER), .COREV_PULP (COREV_PULP) ) controller_i ( @@ -1464,7 +1464,7 @@ module cv32e40p_id_stage // // //////////////////////////////////////////////////////////////////////// - cv32e40p_int_controller #( + cv32e40px_int_controller #( .PULP_SECURE(PULP_SECURE) ) int_controller_i ( .clk (clk), @@ -1474,13 +1474,13 @@ module cv32e40p_id_stage .irq_i (irq_i), .irq_sec_i(irq_sec_i), - // To cv32e40p_controller + // To cv32e40px_controller .irq_req_ctrl_o(irq_req_ctrl), .irq_sec_ctrl_o(irq_sec_ctrl), .irq_id_ctrl_o (irq_id_ctrl), .irq_wu_ctrl_o (irq_wu_ctrl), - // To/from with cv32e40p_cs_registers + // To/from with cv32e40px_cs_registers .mie_bypass_i (mie_bypass_i), .mip_o (mip_o), .m_ie_i (m_irq_enable_i), @@ -1501,7 +1501,7 @@ module cv32e40p_id_stage /////////////////////////////////////////////// - cv32e40p_hwloop_regs #( + cv32e40px_hwloop_regs #( .N_REGS(N_HWLP) ) hwloop_regs_i ( .clk (clk), @@ -1875,10 +1875,10 @@ module cv32e40p_id_stage always_comb begin if (FPU == 1) begin - assert (APU_NDSFLAGS_CPU >= C_RM+2*cv32e40p_fpu_pkg::FP_FORMAT_BITS+cv32e40p_fpu_pkg::INT_FORMAT_BITS) + assert (APU_NDSFLAGS_CPU >= C_RM+2*cv32e40px_fpu_pkg::FP_FORMAT_BITS+cv32e40px_fpu_pkg::INT_FORMAT_BITS) else $error("[apu] APU_NDSFLAGS_CPU APU flagbits is smaller than %0d", - C_RM + 2 * cv32e40p_fpu_pkg::FP_FORMAT_BITS + cv32e40p_fpu_pkg::INT_FORMAT_BITS); + C_RM + 2 * cv32e40px_fpu_pkg::FP_FORMAT_BITS + cv32e40px_fpu_pkg::INT_FORMAT_BITS); end end @@ -2021,4 +2021,4 @@ module cv32e40p_id_stage `endif -endmodule // cv32e40p_id_stage +endmodule // cv32e40px_id_stage diff --git a/rtl/cv32e40px_if_stage.sv b/rtl/cv32e40px_if_stage.sv index c3020af10..526bdac27 100644 --- a/rtl/cv32e40px_if_stage.sv +++ b/rtl/cv32e40px_if_stage.sv @@ -25,7 +25,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_if_stage #( +module cv32e40px_if_stage #( parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) parameter PULP_OBI = 0, // Legacy PULP OBI behavior @@ -62,8 +62,8 @@ module cv32e40p_if_stage #( // compressed x-interface output logic x_compressed_valid_o, input logic x_compressed_ready_i, - output cv32e40p_core_v_xif_pkg::x_compressed_req_t x_compressed_req_o, - input cv32e40p_core_v_xif_pkg::x_compressed_resp_t x_compressed_resp_i, + output cv32e40px_core_v_xif_pkg::x_compressed_req_t x_compressed_req_o, + input cv32e40px_core_v_xif_pkg::x_compressed_resp_t x_compressed_resp_i, input logic [3:0] x_compressed_id_i, // Output of IF Pipeline stage @@ -107,7 +107,7 @@ module cv32e40p_if_stage #( output logic perf_imiss_o // Instruction Fetch Miss ); - import cv32e40p_pkg::*; + import cv32e40px_pkg::*; logic if_valid, if_ready; @@ -185,7 +185,7 @@ module cv32e40p_if_stage #( assign fetch_failed = 1'b0; // PMP is not supported in CV32E40P // prefetch buffer, caches a fixed number of instructions - cv32e40p_prefetch_buffer #( + cv32e40px_prefetch_buffer #( .PULP_OBI (PULP_OBI), .COREV_PULP(COREV_PULP) ) prefetch_buffer_i ( @@ -263,7 +263,7 @@ module cv32e40p_if_stage #( assign if_ready = fetch_valid & id_ready_i; assign if_valid = (~halt_if_i) & if_ready; - cv32e40p_aligner aligner_i ( + cv32e40px_aligner aligner_i ( .clk (clk), .rst_n (rst_n), .fetch_valid_i (fetch_valid), @@ -279,7 +279,7 @@ module cv32e40p_if_stage #( .pc_o (pc_if_o) ); - cv32e40p_compressed_decoder #( + cv32e40px_compressed_decoder #( .FPU (FPU), .ZFINX(ZFINX) ) compressed_decoder_i ( diff --git a/rtl/cv32e40px_int_controller.sv b/rtl/cv32e40px_int_controller.sv index af8489e0f..1e54b4e0a 100644 --- a/rtl/cv32e40px_int_controller.sv +++ b/rtl/cv32e40px_int_controller.sv @@ -21,8 +21,8 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_int_controller - import cv32e40p_pkg::*; +module cv32e40px_int_controller + import cv32e40px_pkg::*; #( parameter PULP_SECURE = 0 ) ( @@ -33,13 +33,13 @@ module cv32e40p_int_controller input logic [31:0] irq_i, // Level-triggered interrupt inputs input logic irq_sec_i, // Interrupt secure bit from EU - // To cv32e40p_controller + // To cv32e40px_controller output logic irq_req_ctrl_o, output logic irq_sec_ctrl_o, output logic [4:0] irq_id_ctrl_o, output logic irq_wu_ctrl_o, - // To/from cv32e40p_cs_registers + // To/from cv32e40px_cs_registers input logic [31:0] mie_bypass_i, // MIE CSR (bypass) output logic [31:0] mip_o, // MIP CSR input logic m_ie_i, // Interrupt enable bit from CSR (M mode) @@ -149,4 +149,4 @@ module cv32e40p_int_controller assign irq_sec_ctrl_o = irq_sec_q; -endmodule // cv32e40p_int_controller +endmodule // cv32e40px_int_controller diff --git a/rtl/cv32e40px_load_store_unit.sv b/rtl/cv32e40px_load_store_unit.sv index 8df1d8498..eea0f05f9 100644 --- a/rtl/cv32e40px_load_store_unit.sv +++ b/rtl/cv32e40px_load_store_unit.sv @@ -23,7 +23,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_load_store_unit #( +module cv32e40px_load_store_unit #( parameter PULP_OBI = 0 // Legacy PULP OBI behavior ) ( input logic clk, @@ -78,7 +78,7 @@ module cv32e40p_load_store_unit #( logic data_req_ex_filtered; // data request from ex stage filtered when it is misaligned and there is an on-going APU instruction - // Transaction request (to cv32e40p_obi_interface) + // Transaction request (to cv32e40px_obi_interface) logic trans_valid; logic trans_ready; logic [31:0] trans_addr; @@ -87,7 +87,7 @@ module cv32e40p_load_store_unit #( logic [31:0] trans_wdata; logic [5:0] trans_atop; - // Transaction response interface (from cv32e40p_obi_interface) + // Transaction response interface (from cv32e40px_obi_interface) logic resp_valid; logic [31:0] resp_rdata; logic resp_err; // Unused for now @@ -459,7 +459,7 @@ module cv32e40p_load_store_unit #( // OBI interface ////////////////////////////////////////////////////////////////////////////// - cv32e40p_obi_interface #( + cv32e40px_obi_interface #( .TRANS_STABLE(1) ) data_obi_i ( .clk (clk), diff --git a/rtl/cv32e40px_mult.sv b/rtl/cv32e40px_mult.sv index ea0da1937..4929ccb49 100644 --- a/rtl/cv32e40px_mult.sv +++ b/rtl/cv32e40px_mult.sv @@ -23,8 +23,8 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_mult - import cv32e40p_pkg::*; +module cv32e40px_mult + import cv32e40px_pkg::*; ( input logic clk, input logic rst_n, diff --git a/rtl/cv32e40px_obi_interface.sv b/rtl/cv32e40px_obi_interface.sv index b44fbeba1..9371ee974 100644 --- a/rtl/cv32e40px_obi_interface.sv +++ b/rtl/cv32e40px_obi_interface.sv @@ -35,7 +35,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_obi_interface #( +module cv32e40px_obi_interface #( parameter TRANS_STABLE = 0 // Are trans_addr_i, trans_we_i, trans_be_i, trans_wdata_i, trans_atop_i signals stable during a non-accepted transaction? ) ( input logic clk, @@ -196,11 +196,11 @@ module cv32e40p_obi_interface #( end // Always ready to accept a new transfer requests when previous A channel - // transfer has been granted. Note that cv32e40p_obi_interface does not limit + // transfer has been granted. Note that cv32e40px_obi_interface does not limit // the number of outstanding transactions in any way. assign trans_ready_o = (state_q == TRANSPARENT); end endgenerate -endmodule // cv32e40p_obi_interface +endmodule // cv32e40px_obi_interface diff --git a/rtl/cv32e40px_popcnt.sv b/rtl/cv32e40px_popcnt.sv index c7fe53e81..f45e230cb 100644 --- a/rtl/cv32e40px_popcnt.sv +++ b/rtl/cv32e40px_popcnt.sv @@ -14,7 +14,7 @@ // Additional contributions by: // // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // -// Design Name: cv32e40p_popcnt // +// Design Name: cv32e40px_popcnt // // Project Name: RI5CY // // Language: SystemVerilog // // // @@ -22,7 +22,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_popcnt ( +module cv32e40px_popcnt ( input logic [31:0] in_i, output logic [ 5:0] result_o ); diff --git a/rtl/cv32e40px_prefetch_buffer.sv b/rtl/cv32e40px_prefetch_buffer.sv index 596bdfe94..2464ef221 100644 --- a/rtl/cv32e40px_prefetch_buffer.sv +++ b/rtl/cv32e40px_prefetch_buffer.sv @@ -24,7 +24,7 @@ // clear_i clears the FIFO for the following cycle. in_addr_i can be sent in // this cycle already -module cv32e40p_prefetch_buffer #( +module cv32e40px_prefetch_buffer #( parameter PULP_OBI = 0, // Legacy PULP OBI behavior parameter COREV_PULP = 1 // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding p.elw) ) ( @@ -60,7 +60,7 @@ module cv32e40p_prefetch_buffer #( localparam FIFO_DEPTH = 2; //must be greater or equal to 2 //Set at least to 3 to avoid stalls compared to the master branch localparam int unsigned FIFO_ADDR_DEPTH = $clog2(FIFO_DEPTH); - // Transaction request (between cv32e40p_prefetch_controller and cv32e40p_obi_interface) + // Transaction request (between cv32e40px_prefetch_controller and cv32e40px_obi_interface) logic trans_valid; logic trans_ready; logic [ 31:0] trans_addr; @@ -74,7 +74,7 @@ module cv32e40p_prefetch_buffer #( logic fifo_pop; logic fifo_empty; - // Transaction response interface (between cv32e40p_obi_interface and cv32e40p_fetch_fifo) + // Transaction response interface (between cv32e40px_obi_interface and cv32e40px_fetch_fifo) logic resp_valid; logic [ 31:0] resp_rdata; logic resp_err; // Unused for now @@ -83,7 +83,7 @@ module cv32e40p_prefetch_buffer #( // Prefetch Controller ////////////////////////////////////////////////////////////////////////////// - cv32e40p_prefetch_controller #( + cv32e40px_prefetch_controller #( .DEPTH (FIFO_DEPTH), .PULP_OBI (PULP_OBI), .COREV_PULP(COREV_PULP) @@ -120,7 +120,7 @@ module cv32e40p_prefetch_buffer #( // Fetch FIFO && fall-through path ////////////////////////////////////////////////////////////////////////////// - cv32e40p_fifo #( + cv32e40px_fifo #( .FALL_THROUGH(1'b0), .DATA_WIDTH (32), .DEPTH (FIFO_DEPTH) @@ -147,7 +147,7 @@ module cv32e40p_prefetch_buffer #( // OBI interface ////////////////////////////////////////////////////////////////////////////// - cv32e40p_obi_interface #( + cv32e40px_obi_interface #( .TRANS_STABLE(0) // trans_* is NOT guaranteed stable during waited transfers; // this is ignored for legacy PULP behavior (not compliant to OBI) ) // Keep this parameter stuck to 0 to make HWLP work @@ -188,7 +188,7 @@ module cv32e40p_prefetch_buffer #( `ifdef CV32E40P_ASSERT_ON // FIFO_DEPTH must be greater than 1. Otherwise, the property - // p_hwlp_end_already_gnt_when_hwlp_branch in cv32e40p_prefetch_controller + // p_hwlp_end_already_gnt_when_hwlp_branch in cv32e40px_prefetch_controller // is not verified, since the prefetcher cannot ask for HWLP_END the cycle // in which HWLP_END-4 is being absorbed by ID. property p_fifo_depth_gt_1; @@ -251,4 +251,4 @@ module cv32e40p_prefetch_buffer #( `endif -endmodule // cv32e40p_prefetch_buffer +endmodule // cv32e40px_prefetch_buffer diff --git a/rtl/cv32e40px_prefetch_controller.sv b/rtl/cv32e40px_prefetch_controller.sv index d00406e54..a4cd3d0fe 100644 --- a/rtl/cv32e40px_prefetch_controller.sv +++ b/rtl/cv32e40px_prefetch_controller.sv @@ -37,7 +37,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_prefetch_controller #( +module cv32e40px_prefetch_controller #( parameter PULP_OBI = 0, // Legacy PULP OBI behavior parameter COREV_PULP = 1, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) parameter DEPTH = 4, // Prefetch FIFO Depth @@ -77,7 +77,7 @@ module cv32e40p_prefetch_controller #( input logic fifo_empty_i // FIFO is empty ); - import cv32e40p_pkg::*; + import cv32e40px_pkg::*; prefetch_state_e state_q, next_state; @@ -128,7 +128,7 @@ module cv32e40p_prefetch_controller #( // Assumes that corresponding response is at least 1 cycle after request // // - Only request transaction when fetch stage requires fetch (req_i), and - // - make sure that FIFO (cv32e40p_fetch_fifo) never overflows (fifo_cnt_i + cnt_q < DEPTH) + // - make sure that FIFO (cv32e40px_fetch_fifo) never overflows (fifo_cnt_i + cnt_q < DEPTH) ////////////////////////////////////////////////////////////////////////////// // Prefetcher will only perform word fetches @@ -360,4 +360,4 @@ module cv32e40p_prefetch_controller #( end end -endmodule // cv32e40p_prefetch_controller +endmodule // cv32e40px_prefetch_controller diff --git a/rtl/cv32e40px_register_file_ff.sv b/rtl/cv32e40px_register_file_ff.sv index 4d31c1277..1543f6e95 100644 --- a/rtl/cv32e40px_register_file_ff.sv +++ b/rtl/cv32e40px_register_file_ff.sv @@ -27,7 +27,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_register_file #( +module cv32e40px_register_file #( parameter ADDR_WIDTH = 5, parameter DATA_WIDTH = 32, parameter FPU = 0, diff --git a/rtl/cv32e40px_register_file_latch.sv b/rtl/cv32e40px_register_file_latch.sv index d8e2f4aa0..037db7c46 100644 --- a/rtl/cv32e40px_register_file_latch.sv +++ b/rtl/cv32e40px_register_file_latch.sv @@ -29,7 +29,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_register_file #( +module cv32e40px_register_file #( parameter ADDR_WIDTH = 5, parameter DATA_WIDTH = 32, parameter FPU = 0, @@ -106,7 +106,7 @@ module cv32e40p_register_file #( // WRITE : SAMPLE INPUT DATA //--------------------------------------------------------------------------- - cv32e40p_clock_gate CG_WE_GLOBAL ( + cv32e40px_clock_gate CG_WE_GLOBAL ( .clk_i (clk), .en_i (we_a_i | we_b_i), .scan_cg_en_i(scan_cg_en_i), @@ -148,7 +148,7 @@ module cv32e40p_register_file #( //----------------------------------------------------------------------------- generate for (x = 1; x < NUM_TOT_WORDS; x++) begin : gen_clock_gate - cv32e40p_clock_gate clock_gate_i ( + cv32e40px_clock_gate clock_gate_i ( .clk_i (clk_int), .en_i (waddr_onehot_a[x] | waddr_onehot_b[x]), .scan_cg_en_i(scan_cg_en_i), diff --git a/rtl/cv32e40px_sleep_unit.sv b/rtl/cv32e40px_sleep_unit.sv index 03e519487..d4872ec7a 100644 --- a/rtl/cv32e40px_sleep_unit.sv +++ b/rtl/cv32e40px_sleep_unit.sv @@ -53,7 +53,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_sleep_unit #( +module cv32e40px_sleep_unit #( parameter COREV_CLUSTER = 0 ) ( // Clock, reset interface @@ -85,7 +85,7 @@ module cv32e40p_sleep_unit #( input logic wake_from_sleep_i ); - import cv32e40p_pkg::*; + import cv32e40px_pkg::*; logic fetch_enable_q; // Sticky version of fetch_enable_i logic fetch_enable_d; @@ -126,7 +126,7 @@ module cv32e40p_sleep_unit #( assign clock_en = fetch_enable_q && (wake_from_sleep_i || core_busy_q); // Sleep only in response to WFI which leads to clock disable; debug_wfi_no_sleep_o in - // cv32e40p_controller determines the scenarios for which WFI can(not) cause sleep. + // cv32e40px_controller determines the scenarios for which WFI can(not) cause sleep. assign core_sleep_o = fetch_enable_q && !clock_en; // cv.elw does not exist for COREV_CLUSTER = 0 @@ -151,7 +151,7 @@ module cv32e40p_sleep_unit #( assign fetch_enable_o = fetch_enable_q; // Main clock gate of CV32E40P - cv32e40p_clock_gate core_clock_gate_i ( + cv32e40px_clock_gate core_clock_gate_i ( .clk_i (clk_ungated_i), .en_i (clock_en), .scan_cg_en_i(scan_cg_en_i), @@ -166,7 +166,7 @@ module cv32e40p_sleep_unit #( // Clock gate is disabled during RESET state of the controller property p_clock_en_0; - @(posedge clk_ungated_i) disable iff (!rst_n) ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::RESET) && (id_stage_i.controller_i.ctrl_fsm_ns == cv32e40p_pkg::RESET)) |-> (clock_en == 1'b0); + @(posedge clk_ungated_i) disable iff (!rst_n) ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::RESET) && (id_stage_i.controller_i.ctrl_fsm_ns == cv32e40px_pkg::RESET)) |-> (clock_en == 1'b0); endproperty a_clock_en_0 : @@ -174,7 +174,7 @@ module cv32e40p_sleep_unit #( // Clock gate is enabled when exit from RESET state is required property p_clock_en_1; - @(posedge clk_ungated_i) disable iff (!rst_n) ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::RESET) && (id_stage_i.controller_i.ctrl_fsm_ns != cv32e40p_pkg::RESET)) |-> (clock_en == 1'b1); + @(posedge clk_ungated_i) disable iff (!rst_n) ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::RESET) && (id_stage_i.controller_i.ctrl_fsm_ns != cv32e40px_pkg::RESET)) |-> (clock_en == 1'b1); endproperty a_clock_en_1 : @@ -193,7 +193,7 @@ module cv32e40p_sleep_unit #( // Clock gate is only possibly disabled in RESET or when COREV_CLUSTER disables clock property p_clock_en_3; - @(posedge clk_ungated_i) disable iff (!rst_n) (clock_en == 1'b0) -> ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::RESET) || (COREV_CLUSTER && !pulp_clock_en_i)); + @(posedge clk_ungated_i) disable iff (!rst_n) (clock_en == 1'b0) -> ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::RESET) || (COREV_CLUSTER && !pulp_clock_en_i)); endproperty a_clock_en_3 : @@ -220,7 +220,7 @@ module cv32e40p_sleep_unit #( // Clock gate is only possibly disabled in RESET or SLEEP property p_clock_en_4; - @(posedge clk_ungated_i) disable iff (!rst_n) (clock_en == 1'b0) -> ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::RESET) || (id_stage_i.controller_i.ctrl_fsm_ns == cv32e40p_pkg::SLEEP)); + @(posedge clk_ungated_i) disable iff (!rst_n) (clock_en == 1'b0) -> ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::RESET) || (id_stage_i.controller_i.ctrl_fsm_ns == cv32e40px_pkg::SLEEP)); endproperty a_clock_en_4 : @@ -228,7 +228,7 @@ module cv32e40p_sleep_unit #( // Clock gate is enabled when exit from SLEEP state is required property p_clock_en_5; - @(posedge clk_ungated_i) disable iff (!rst_n) ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::SLEEP) && (id_stage_i.controller_i.ctrl_fsm_ns != cv32e40p_pkg::SLEEP)) |-> (clock_en == 1'b1); + @(posedge clk_ungated_i) disable iff (!rst_n) ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::SLEEP) && (id_stage_i.controller_i.ctrl_fsm_ns != cv32e40px_pkg::SLEEP)) |-> (clock_en == 1'b1); endproperty a_clock_en_5 : @@ -236,7 +236,7 @@ module cv32e40p_sleep_unit #( // Core sleep is only signaled in SLEEP state property p_core_sleep; - @(posedge clk_ungated_i) disable iff (!rst_n) (core_sleep_o == 1'b1) -> ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::SLEEP)); + @(posedge clk_ungated_i) disable iff (!rst_n) (core_sleep_o == 1'b1) -> ((id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::SLEEP)); endproperty a_core_sleep : @@ -244,7 +244,7 @@ module cv32e40p_sleep_unit #( // Core can only become non-busy due to SLEEP entry property p_non_busy; - @(posedge clk_ungated_i) disable iff (!rst_n) (core_busy_d == 1'b0) |-> (id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::WAIT_SLEEP) || (id_stage_i.controller_i.ctrl_fsm_cs == cv32e40p_pkg::SLEEP); + @(posedge clk_ungated_i) disable iff (!rst_n) (core_busy_d == 1'b0) |-> (id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::WAIT_SLEEP) || (id_stage_i.controller_i.ctrl_fsm_cs == cv32e40px_pkg::SLEEP); endproperty a_non_busy : @@ -289,4 +289,4 @@ module cv32e40p_sleep_unit #( `endif -endmodule // cv32e40p_sleep_unit +endmodule // cv32e40px_sleep_unit diff --git a/rtl/cv32e40px_top.sv b/rtl/cv32e40px_top.sv index 1b5c9c829..4c9977bc2 100644 --- a/rtl/cv32e40px_top.sv +++ b/rtl/cv32e40px_top.sv @@ -11,7 +11,7 @@ // Top file instantiating a CV32E40P core and an optional FPU // Contributor: Davide Schiavone -module cv32e40p_top import cv32e40p_core_v_xif_pkg::*; #( +module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) @@ -100,7 +100,7 @@ module cv32e40p_top import cv32e40p_core_v_xif_pkg::*; #( output logic core_sleep_o ); - import cv32e40p_apu_core_pkg::*; + import cv32e40px_apu_core_pkg::*; // Core to FPU logic clk; @@ -116,7 +116,7 @@ module cv32e40p_top import cv32e40p_core_v_xif_pkg::*; #( logic [APU_NUSFLAGS_CPU-1:0] apu_rflags; // Instantiate the Core - cv32e40p_core #( + cv32e40px_core #( .COREV_X_IF (COREV_X_IF), .COREV_PULP (COREV_PULP), .COREV_CLUSTER (COREV_CLUSTER), @@ -178,7 +178,7 @@ module cv32e40p_top import cv32e40p_core_v_xif_pkg::*; #( generate if (FPU) begin : fpu_gen // FPU clock gate - cv32e40p_clock_gate core_clock_gate_i ( + cv32e40px_clock_gate core_clock_gate_i ( .clk_i (clk_i), .en_i (!core_sleep_o), .scan_cg_en_i(scan_cg_en_i), @@ -186,7 +186,7 @@ module cv32e40p_top import cv32e40p_core_v_xif_pkg::*; #( ); // Instantiate the FPU wrapper - cv32e40p_fp_wrapper #( + cv32e40px_fp_wrapper #( .FPU_ADDMUL_LAT(FPU_ADDMUL_LAT), .FPU_OTHERS_LAT(FPU_OTHERS_LAT) ) fp_wrapper_i ( diff --git a/rtl/cv32e40px_x_disp.sv b/rtl/cv32e40px_x_disp.sv index e7059b5c4..d75e8a0f8 100644 --- a/rtl/cv32e40px_x_disp.sv +++ b/rtl/cv32e40px_x_disp.sv @@ -12,15 +12,15 @@ // Engineer: Moritz Imfeld - moimfeld@student.ethz.ch // // // // Design Name: x-interface dispatcher // -// Project Name: cv32e40p // +// Project Name: cv32e40px // // Language: SystemVerilog // // // // Description: Dispatcher for sending instructions to the x-interface. // // // //////////////////////////////////////////////////////////////////////////////// -module cv32e40p_x_disp - import cv32e40p_core_v_xif_pkg::*; +module cv32e40px_x_disp + import cv32e40px_core_v_xif_pkg::*; ( // clock and reset input logic clk_i, @@ -91,7 +91,7 @@ module cv32e40p_x_disp input logic id_ready_i, input logic ex_valid_i, input logic ex_ready_i, - input cv32e40p_pkg::PrivLvl_t current_priv_lvl_i, + input cv32e40px_pkg::PrivLvl_t current_priv_lvl_i, input logic data_req_dec_i ); @@ -115,7 +115,7 @@ module cv32e40p_x_disp & ~(x_rs_addr_i[1] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[1] == waddr_wb_i & ~ex_valid_i); assign x_issue_req_rs_valid_o[2] = (~scoreboard_q[x_rs_addr_i[2]] | x_ex_fwd_o[2] | x_wb_fwd_o[2]) & ~(x_rs_addr_i[2] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[2] == waddr_wb_i & ~ex_valid_i); - assign x_issue_req_ecs_valid = 1'b1; // extension context status is not implemented in cv32e40p + assign x_issue_req_ecs_valid = 1'b1; // extension context status is not implemented in cv32e40px // commit interface assign x_commit_valid_o = x_issue_valid_o; @@ -170,10 +170,10 @@ module cv32e40p_x_disp always_comb begin x_issue_req_mode_o = 2'b11; case (current_priv_lvl_i) - cv32e40p_pkg::PRIV_LVL_M: x_issue_req_mode_o = 2'b11; - cv32e40p_pkg::PRIV_LVL_H: x_issue_req_mode_o = 2'b10; - cv32e40p_pkg::PRIV_LVL_S: x_issue_req_mode_o = 2'b01; - cv32e40p_pkg::PRIV_LVL_U: x_issue_req_mode_o = 2'b00; + cv32e40px_pkg::PRIV_LVL_M: x_issue_req_mode_o = 2'b11; + cv32e40px_pkg::PRIV_LVL_H: x_issue_req_mode_o = 2'b10; + cv32e40px_pkg::PRIV_LVL_S: x_issue_req_mode_o = 2'b01; + cv32e40px_pkg::PRIV_LVL_U: x_issue_req_mode_o = 2'b00; default: x_issue_req_mode_o = 2'b11; endcase end @@ -233,4 +233,4 @@ module cv32e40p_x_disp end end -endmodule : cv32e40p_x_disp +endmodule : cv32e40px_x_disp diff --git a/rtl/include/cv32e40px_apu_core_pkg.sv b/rtl/include/cv32e40px_apu_core_pkg.sv index 26cb42fa9..7e614b00d 100644 --- a/rtl/include/cv32e40px_apu_core_pkg.sv +++ b/rtl/include/cv32e40px_apu_core_pkg.sv @@ -19,7 +19,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -package cv32e40p_apu_core_pkg; +package cv32e40px_apu_core_pkg; // APU interface parameter APU_NARGS_CPU = 3; @@ -27,4 +27,4 @@ package cv32e40p_apu_core_pkg; parameter APU_NDSFLAGS_CPU = 15; parameter APU_NUSFLAGS_CPU = 5; -endpackage // cv32e40p_apu_core_pkg +endpackage // cv32e40px_apu_core_pkg diff --git a/rtl/include/cv32e40px_core_v_xif_pkg.sv b/rtl/include/cv32e40px_core_v_xif_pkg.sv index 71cd8804c..77c0887a6 100644 --- a/rtl/include/cv32e40px_core_v_xif_pkg.sv +++ b/rtl/include/cv32e40px_core_v_xif_pkg.sv @@ -11,7 +11,7 @@ // CORE-V-XIF Package // Contributor: Moritz Imfeld -package cv32e40p_core_v_xif_pkg; +package cv32e40px_core_v_xif_pkg; // cv-x-if parameters parameter int X_NUM_RS = 3; diff --git a/rtl/include/cv32e40px_fpu_pkg.sv b/rtl/include/cv32e40px_fpu_pkg.sv index fe2415325..5a3d2699a 100644 --- a/rtl/include/cv32e40px_fpu_pkg.sv +++ b/rtl/include/cv32e40px_fpu_pkg.sv @@ -35,7 +35,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -package cv32e40p_fpu_pkg; +package cv32e40px_fpu_pkg; // --------- // FP TYPES diff --git a/rtl/include/cv32e40px_pkg.sv b/rtl/include/cv32e40px_pkg.sv index 319e790b6..2441949c8 100644 --- a/rtl/include/cv32e40px_pkg.sv +++ b/rtl/include/cv32e40px_pkg.sv @@ -23,7 +23,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -package cv32e40p_pkg; +package cv32e40px_pkg; //////////////////////////////////////////////// // ___ ____ _ // From fed0713c7030ca324cf95ece0d0412cd04727109 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 20 Jul 2023 10:13:37 +0200 Subject: [PATCH 06/13] update top file --- rtl/cv32e40px_top.sv | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/rtl/cv32e40px_top.sv b/rtl/cv32e40px_top.sv index 4c9977bc2..93570e5cb 100644 --- a/rtl/cv32e40px_top.sv +++ b/rtl/cv32e40px_top.sv @@ -162,6 +162,38 @@ module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( .apu_result_i (apu_rdata), .apu_flags_i (apu_rflags), + // CORE-V-XIF + // Compressed interface + .x_compressed_valid_o(x_compressed_valid_o), + .x_compressed_ready_i(x_compressed_ready_i), + .x_compressed_req_o(x_compressed_req_o), + .x_compressed_resp_i(x_compressed_resp_i), + + // Issue Interface + .x_issue_valid_o(x_issue_valid_o), + .x_issue_ready_i(x_issue_ready_i), + .x_issue_req_o(x_issue_req_o), + .x_issue_resp_i(x_issue_resp_i), + + // Commit Interface + .x_commit_valid_o(x_commit_valid_o), + .x_commit_o(x_commit_o), + + // Memory request/response Interface + .x_mem_valid_i(x_mem_valid_i), + .x_mem_ready_o(x_mem_ready_o), + .x_mem_req_i(x_mem_req_i), + .x_mem_resp_o(x_mem_resp_o), + + // Memory Result Interface + .x_mem_result_valid_o(x_mem_result_valid_o), + .x_mem_result_o(x_mem_result_o), + + // Result Interface + .x_result_valid_i(x_result_valid_i), + .x_result_ready_o(x_result_ready_o), + .x_result_i(x_result_i), + .irq_i (irq_i), .irq_ack_o(irq_ack_o), .irq_id_o (irq_id_o), From 21a66269610a1f98f1712d3b887570f0b4657086 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 20 Jul 2023 14:43:45 +0200 Subject: [PATCH 07/13] fix undriven signals --- rtl/cv32e40px_core.sv | 2 ++ rtl/cv32e40px_id_stage.sv | 17 +++++++++++++++-- rtl/cv32e40px_if_stage.sv | 3 ++- rtl/include/cv32e40px_core_v_xif_pkg.sv | 2 +- 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/rtl/cv32e40px_core.sv b/rtl/cv32e40px_core.sv index 2991b77f6..36988b4eb 100644 --- a/rtl/cv32e40px_core.sv +++ b/rtl/cv32e40px_core.sv @@ -407,6 +407,8 @@ module cv32e40px_core assign apu_flags_o = apu_flags_ex; assign fflags_csr = apu_flags_i; + assign x_mem_result_o.dbg = '0; + ////////////////////////////////////////////////////////////////////////////////////////////// // ____ _ _ __ __ _ // // / ___| | ___ ___| | __ | \/ | __ _ _ __ __ _ __ _ ___ _ __ ___ ___ _ __ | |_ // diff --git a/rtl/cv32e40px_id_stage.sv b/rtl/cv32e40px_id_stage.sv index 23cb2f8e5..5daa857ac 100644 --- a/rtl/cv32e40px_id_stage.sv +++ b/rtl/cv32e40px_id_stage.sv @@ -30,6 +30,7 @@ module cv32e40px_id_stage import cv32e40px_pkg::*; import cv32e40px_apu_core_pkg::*; + import cv32e40px_core_v_xif_pkg::*; #( parameter COREV_X_IF = 0, parameter COREV_PULP = 1, // PULP ISA Extension (including PULP specific CSRs and hardware loop, excluding cv.elw) @@ -427,6 +428,7 @@ module cv32e40px_id_stage // X-Interface logic illegal_insn; + logic x_illegal_insn; logic [4:0] waddr_id; logic [4:0] waddr_ex; logic [4:0] waddr_wb; @@ -1129,7 +1131,18 @@ module cv32e40px_id_stage assign x_stall = 1'b0; assign x_result_valid_assigned_o = 1'b0; assign x_mem_valid = 1'b0; + assign x_mem_data_req = '0; + assign x_mem_data_type_id = '0; assign x_issue_valid_o = 1'b0; + assign x_compressed_id_o = '0; + assign x_issue_req_o = '0; + assign x_commit_valid_o = '0; + assign x_commit_o = '0; + assign x_mem_ready_o = '0; + assign x_mem_resp_o = '0; + assign x_mem_result_valid_o = '0; + assign x_mem_result_err_o = '0; + assign x_result_ready_o = '0; end : gen_no_x_disp endgenerate @@ -1759,7 +1772,7 @@ module cv32e40px_id_stage end x_mem_instr_ex_o <= 1'b0; - x_mem_id_ex_o <= 1'b0; + x_mem_id_ex_o <= '0; data_misaligned_ex_o <= 1'b0; @@ -1804,7 +1817,7 @@ module cv32e40px_id_stage x_mem_id_ex_o <= x_mem_req_i.id; end else begin x_mem_instr_ex_o <= 1'b0; - x_mem_id_ex_o <= 1'b0; + x_mem_id_ex_o <= '0; data_req_ex_o <= 1'b0; data_load_event_ex_o <= 1'b0; end diff --git a/rtl/cv32e40px_if_stage.sv b/rtl/cv32e40px_if_stage.sv index 526bdac27..b2456c2b1 100644 --- a/rtl/cv32e40px_if_stage.sv +++ b/rtl/cv32e40px_if_stage.sv @@ -311,10 +311,11 @@ module cv32e40px_if_stage #( end else begin assign instr_decompressed = instr_decompressed_dec; assign illegal_c_insn = illegal_c_insn_dec; + assign x_compressed_valid_o = '0; + assign x_compressed_req_o = '0; end endgenerate - //---------------------------------------------------------------------------- // Assertions //---------------------------------------------------------------------------- diff --git a/rtl/include/cv32e40px_core_v_xif_pkg.sv b/rtl/include/cv32e40px_core_v_xif_pkg.sv index 77c0887a6..32262458d 100644 --- a/rtl/include/cv32e40px_core_v_xif_pkg.sv +++ b/rtl/include/cv32e40px_core_v_xif_pkg.sv @@ -47,7 +47,7 @@ package cv32e40px_core_v_xif_pkg; typedef struct packed { logic accept; logic writeback; - logic float; + //logic float; logic dualwrite; logic dualread; logic loadstore; From bfb6b76b19e036ade7265eb78ac15b733f0d758a Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 20 Jul 2023 15:07:27 +0200 Subject: [PATCH 08/13] format verible --- rtl/cv32e40px_core.sv | 88 ++++++++++++------------- rtl/cv32e40px_ex_stage.sv | 8 +-- rtl/cv32e40px_id_stage.sv | 4 +- rtl/cv32e40px_if_stage.sv | 12 ++-- rtl/cv32e40px_top.sv | 32 ++++----- rtl/cv32e40px_x_disp.sv | 4 +- rtl/include/cv32e40px_core_v_xif_pkg.sv | 78 +++++++++++----------- 7 files changed, 114 insertions(+), 112 deletions(-) diff --git a/rtl/cv32e40px_core.sv b/rtl/cv32e40px_core.sv index 36988b4eb..05da683c5 100644 --- a/rtl/cv32e40px_core.sv +++ b/rtl/cv32e40px_core.sv @@ -89,24 +89,24 @@ module cv32e40px_core // CORE-V-XIF // Compressed interface output logic x_compressed_valid_o, - input logic x_compressed_ready_i, + input logic x_compressed_ready_i, output x_compressed_req_t x_compressed_req_o, - input x_compressed_resp_t x_compressed_resp_i, + input x_compressed_resp_t x_compressed_resp_i, // Issue Interface output logic x_issue_valid_o, - input logic x_issue_ready_i, + input logic x_issue_ready_i, output x_issue_req_t x_issue_req_o, - input x_issue_resp_t x_issue_resp_i, + input x_issue_resp_t x_issue_resp_i, // Commit Interface output logic x_commit_valid_o, output x_commit_t x_commit_o, // Memory request/response Interface - input logic x_mem_valid_i, + input logic x_mem_valid_i, output logic x_mem_ready_o, - input x_mem_req_t x_mem_req_i, + input x_mem_req_t x_mem_req_i, output x_mem_resp_t x_mem_resp_o, // Memory Result Interface @@ -114,9 +114,9 @@ module cv32e40px_core output x_mem_result_t x_mem_result_o, // Result Interface - input logic x_result_valid_i, + input logic x_result_valid_i, output logic x_result_ready_o, - input x_result_t x_result_i, + input x_result_t x_result_i, // Interrupt inputs @@ -259,12 +259,12 @@ module cv32e40px_core logic perf_apu_wb; // X-Interface - logic [ 3:0] x_compressed_id; - logic x_result_valid_assigned; - logic x_mem_instr; - logic [ 3:0] x_mem_id_ex; - logic x_mem_instr_wb; - logic [31:0] result_fw_to_x; + logic [ 3:0] x_compressed_id; + logic x_result_valid_assigned; + logic x_mem_instr; + logic [ 3:0] x_mem_id_ex; + logic x_mem_instr_wb; + logic [ 31:0] result_fw_to_x; // Register Write Control logic [ 5:0] regfile_waddr_ex; @@ -498,11 +498,11 @@ module cv32e40px_core // X-IF - .x_compressed_valid_o (x_compressed_valid_o), - .x_compressed_ready_i (x_compressed_ready_i), - .x_compressed_req_o (x_compressed_req_o), - .x_compressed_resp_i (x_compressed_resp_i), - .x_compressed_id_i (x_compressed_id), + .x_compressed_valid_o(x_compressed_valid_o), + .x_compressed_ready_i(x_compressed_ready_i), + .x_compressed_req_o (x_compressed_req_o), + .x_compressed_resp_i (x_compressed_resp_i), + .x_compressed_id_i (x_compressed_id), // outputs to ID stage .instr_valid_id_o (instr_valid_id), @@ -687,33 +687,33 @@ module cv32e40px_core // CORE-V-XIF // Compressed Interface - .x_compressed_id_o (x_compressed_id), + .x_compressed_id_o(x_compressed_id), // Issue Interface - .x_issue_valid_o (x_issue_valid_o), - .x_issue_ready_i (x_issue_ready_i), - .x_issue_req_o (x_issue_req_o), + .x_issue_valid_o(x_issue_valid_o), + .x_issue_ready_i(x_issue_ready_i), + .x_issue_req_o (x_issue_req_o), .x_issue_resp_i (x_issue_resp_i), // Commit Interface - .x_commit_valid_o (x_commit_valid_o), - .x_commit_o (x_commit_o), + .x_commit_valid_o(x_commit_valid_o), + .x_commit_o(x_commit_o), // Memory request/response Interface - .x_mem_valid_i (x_mem_valid_i), - .x_mem_ready_o (x_mem_ready_o), - .x_mem_req_i (x_mem_req_i), + .x_mem_valid_i(x_mem_valid_i), + .x_mem_ready_o(x_mem_ready_o), + .x_mem_req_i (x_mem_req_i), .x_mem_resp_o (x_mem_resp_o), // Memory Result Interface - .x_mem_result_valid_o (x_mem_result_valid_o), - .x_mem_result_err_o (x_mem_result_o.err), + .x_mem_result_valid_o(x_mem_result_valid_o), + .x_mem_result_err_o (x_mem_result_o.err), // Result Interface - .x_result_valid_i (x_result_valid_i), - .x_result_ready_o (x_result_ready_o), - .x_result_i (x_result_i), - .x_result_valid_assigned_o (x_result_valid_assigned), + .x_result_valid_i(x_result_valid_i), + .x_result_ready_o(x_result_ready_o), + .x_result_i(x_result_i), + .x_result_valid_assigned_o(x_result_valid_assigned), .x_mem_instr_ex_o(x_mem_instr), .x_mem_id_ex_o (x_mem_id_ex), @@ -905,16 +905,16 @@ module cv32e40px_core .apu_result_i (apu_result_i), // X-Interface - .x_result_valid_assigned_i (x_result_valid_assigned), - .x_result_rd_i (x_result_i.rd), - .x_result_data_i (x_result_i.data), - .x_result_we_i (x_result_i.we), - .x_mem_instr_i (x_mem_instr), - .x_mem_id_ex_i (x_mem_id_ex), - .x_mem_result_rdata_o (x_mem_result_o.rdata), - .x_mem_instr_wb_o (x_mem_instr_wb), - .x_mem_result_id_o (x_mem_result_o.id), - .result_fw_to_x_o (result_fw_to_x), + .x_result_valid_assigned_i(x_result_valid_assigned), + .x_result_rd_i (x_result_i.rd), + .x_result_data_i (x_result_i.data), + .x_result_we_i (x_result_i.we), + .x_mem_instr_i (x_mem_instr), + .x_mem_id_ex_i (x_mem_id_ex), + .x_mem_result_rdata_o (x_mem_result_o.rdata), + .x_mem_instr_wb_o (x_mem_instr_wb), + .x_mem_result_id_o (x_mem_result_o.id), + .result_fw_to_x_o (result_fw_to_x), .lsu_en_i (data_req_ex), .lsu_rdata_i(lsu_rdata), diff --git a/rtl/cv32e40px_ex_stage.sv b/rtl/cv32e40px_ex_stage.sv index 1ce3d629a..0ec00997e 100644 --- a/rtl/cv32e40px_ex_stage.sv +++ b/rtl/cv32e40px_ex_stage.sv @@ -257,8 +257,8 @@ module cv32e40px_ex_stage assign x_mem_result_rdata_o = lsu_rdata_i; // branch handling - assign branch_decision_o = alu_cmp_result; - assign jump_target_o = alu_operand_c_i; + assign branch_decision_o = alu_cmp_result; + assign jump_target_o = alu_operand_c_i; //////////////////////////// @@ -432,7 +432,7 @@ module cv32e40px_ex_stage if (ex_valid_o) // wb_ready_i is implied begin regfile_we_lsu <= regfile_we_i & ~lsu_err_i; - x_mem_instr_wb_o <= x_mem_instr_i; + x_mem_instr_wb_o <= x_mem_instr_i; x_mem_result_id_o <= x_mem_id_ex_i; if (regfile_we_i & ~lsu_err_i) begin regfile_waddr_lsu <= regfile_waddr_i; @@ -440,7 +440,7 @@ module cv32e40px_ex_stage end else if (wb_ready_i) begin // we are ready for a new instruction, but there is none available, // so we just flush the current one out of the pipe - regfile_we_lsu <= 1'b0; + regfile_we_lsu <= 1'b0; x_mem_instr_wb_o <= 1'b0; end end diff --git a/rtl/cv32e40px_id_stage.sv b/rtl/cv32e40px_id_stage.sv index 5daa857ac..e3b6640d9 100644 --- a/rtl/cv32e40px_id_stage.sv +++ b/rtl/cv32e40px_id_stage.sv @@ -183,7 +183,7 @@ module cv32e40px_id_stage // Core internal xif memory signals output logic x_mem_instr_ex_o, - output logic [3:0] x_mem_id_ex_o, + output logic [ 3:0] x_mem_id_ex_o, input logic x_mem_instr_wb_i, input logic [31:0] result_fw_to_x_i, @@ -1008,7 +1008,7 @@ module cv32e40px_id_stage .rst_ni(rst_n), // compressed interface - .x_compressed_id_o (x_compressed_id_o), + .x_compressed_id_o(x_compressed_id_o), // issue interface .x_issue_valid_o (x_issue_valid_o), diff --git a/rtl/cv32e40px_if_stage.sv b/rtl/cv32e40px_if_stage.sv index b2456c2b1..a36f89ae3 100644 --- a/rtl/cv32e40px_if_stage.sv +++ b/rtl/cv32e40px_if_stage.sv @@ -61,10 +61,10 @@ module cv32e40px_if_stage #( // compressed x-interface output logic x_compressed_valid_o, - input logic x_compressed_ready_i, + input logic x_compressed_ready_i, output cv32e40px_core_v_xif_pkg::x_compressed_req_t x_compressed_req_o, - input cv32e40px_core_v_xif_pkg::x_compressed_resp_t x_compressed_resp_i, - input logic [3:0] x_compressed_id_i, + input cv32e40px_core_v_xif_pkg::x_compressed_resp_t x_compressed_resp_i, + input logic [3:0] x_compressed_id_i, // Output of IF Pipeline stage output logic instr_valid_id_o, // instruction in IF/ID pipeline is valid @@ -294,7 +294,7 @@ module cv32e40px_if_stage #( if (COREV_X_IF) begin assign x_compressed_valid_o = illegal_c_insn_dec; assign x_compressed_req_o.instr = instr_aligned; - assign x_compressed_req_o.mode = 2'b00; // Machine Mode + assign x_compressed_req_o.mode = 2'b00; // Machine Mode assign x_compressed_req_o.id = x_compressed_id_i; always_comb begin @@ -309,8 +309,8 @@ module cv32e40px_if_stage #( end end end else begin - assign instr_decompressed = instr_decompressed_dec; - assign illegal_c_insn = illegal_c_insn_dec; + assign instr_decompressed = instr_decompressed_dec; + assign illegal_c_insn = illegal_c_insn_dec; assign x_compressed_valid_o = '0; assign x_compressed_req_o = '0; end diff --git a/rtl/cv32e40px_top.sv b/rtl/cv32e40px_top.sv index 93570e5cb..ad3dc9868 100644 --- a/rtl/cv32e40px_top.sv +++ b/rtl/cv32e40px_top.sv @@ -11,7 +11,9 @@ // Top file instantiating a CV32E40P core and an optional FPU // Contributor: Davide Schiavone -module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( +module cv32e40px_top + import cv32e40px_core_v_xif_pkg::*; +#( parameter COREV_X_IF = 0, parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) @@ -55,24 +57,24 @@ module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( // CORE-V-XIF // Compressed interface output logic x_compressed_valid_o, - input logic x_compressed_ready_i, + input logic x_compressed_ready_i, output x_compressed_req_t x_compressed_req_o, - input x_compressed_resp_t x_compressed_resp_i, + input x_compressed_resp_t x_compressed_resp_i, // Issue Interface output logic x_issue_valid_o, - input logic x_issue_ready_i, + input logic x_issue_ready_i, output x_issue_req_t x_issue_req_o, - input x_issue_resp_t x_issue_resp_i, + input x_issue_resp_t x_issue_resp_i, // Commit Interface output logic x_commit_valid_o, output x_commit_t x_commit_o, // Memory request/response Interface - input logic x_mem_valid_i, + input logic x_mem_valid_i, output logic x_mem_ready_o, - input x_mem_req_t x_mem_req_i, + input x_mem_req_t x_mem_req_i, output x_mem_resp_t x_mem_resp_o, // Memory Result Interface @@ -80,9 +82,9 @@ module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( output x_mem_result_t x_mem_result_o, // Result Interface - input logic x_result_valid_i, + input logic x_result_valid_i, output logic x_result_ready_o, - input x_result_t x_result_i, + input x_result_t x_result_i, // Interrupt inputs input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts @@ -166,14 +168,14 @@ module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( // Compressed interface .x_compressed_valid_o(x_compressed_valid_o), .x_compressed_ready_i(x_compressed_ready_i), - .x_compressed_req_o(x_compressed_req_o), - .x_compressed_resp_i(x_compressed_resp_i), + .x_compressed_req_o (x_compressed_req_o), + .x_compressed_resp_i (x_compressed_resp_i), // Issue Interface .x_issue_valid_o(x_issue_valid_o), .x_issue_ready_i(x_issue_ready_i), - .x_issue_req_o(x_issue_req_o), - .x_issue_resp_i(x_issue_resp_i), + .x_issue_req_o (x_issue_req_o), + .x_issue_resp_i (x_issue_resp_i), // Commit Interface .x_commit_valid_o(x_commit_valid_o), @@ -182,8 +184,8 @@ module cv32e40px_top import cv32e40px_core_v_xif_pkg::*; #( // Memory request/response Interface .x_mem_valid_i(x_mem_valid_i), .x_mem_ready_o(x_mem_ready_o), - .x_mem_req_i(x_mem_req_i), - .x_mem_resp_o(x_mem_resp_o), + .x_mem_req_i (x_mem_req_i), + .x_mem_resp_o (x_mem_resp_o), // Memory Result Interface .x_mem_result_valid_o(x_mem_result_valid_o), diff --git a/rtl/cv32e40px_x_disp.sv b/rtl/cv32e40px_x_disp.sv index d75e8a0f8..b2dea3482 100644 --- a/rtl/cv32e40px_x_disp.sv +++ b/rtl/cv32e40px_x_disp.sv @@ -52,7 +52,7 @@ module cv32e40px_x_disp input logic x_mem_req_last_i, // unused output logic x_mem_resp_exc_o, // hardwired to 0 output logic [5:0] x_mem_resp_exccode_o, // hardwired to 0 - output logic x_mem_resp_dbg_o, // hardwired to 0 + output logic x_mem_resp_dbg_o, // hardwired to 0 // memory result interface output logic x_mem_result_valid_o, @@ -115,7 +115,7 @@ module cv32e40px_x_disp & ~(x_rs_addr_i[1] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[1] == waddr_wb_i & ~ex_valid_i); assign x_issue_req_rs_valid_o[2] = (~scoreboard_q[x_rs_addr_i[2]] | x_ex_fwd_o[2] | x_wb_fwd_o[2]) & ~(x_rs_addr_i[2] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[2] == waddr_wb_i & ~ex_valid_i); - assign x_issue_req_ecs_valid = 1'b1; // extension context status is not implemented in cv32e40px + assign x_issue_req_ecs_valid = 1'b1; // extension context status is not implemented in cv32e40px // commit interface assign x_commit_valid_o = x_issue_valid_o; diff --git a/rtl/include/cv32e40px_core_v_xif_pkg.sv b/rtl/include/cv32e40px_core_v_xif_pkg.sv index 32262458d..ae52789ca 100644 --- a/rtl/include/cv32e40px_core_v_xif_pkg.sv +++ b/rtl/include/cv32e40px_core_v_xif_pkg.sv @@ -14,34 +14,34 @@ package cv32e40px_core_v_xif_pkg; // cv-x-if parameters - parameter int X_NUM_RS = 3; - parameter int X_ID_WIDTH = 4; - parameter int X_MEM_WIDTH = 32; - parameter int X_RFR_WIDTH = 32; - parameter int X_RFW_WIDTH = 32; - parameter logic [31:0] X_MISA = '0; - parameter logic [ 1:0] X_ECS_XS = '0; + parameter int X_NUM_RS = 3; + parameter int X_ID_WIDTH = 4; + parameter int X_MEM_WIDTH = 32; + parameter int X_RFR_WIDTH = 32; + parameter int X_RFW_WIDTH = 32; + parameter logic [31:0] X_MISA = '0; + parameter logic [1:0] X_ECS_XS = '0; // interface structs typedef struct packed { - logic [ 15:0] instr; - logic [ 1:0] mode; + logic [15:0] instr; + logic [1:0] mode; logic [X_ID_WIDTH-1:0] id; } x_compressed_req_t; typedef struct packed { logic [31:0] instr; - logic accept; + logic accept; } x_compressed_resp_t; typedef struct packed { - logic [ 31:0] instr; - logic [ 1:0] mode; - logic [ X_ID_WIDTH-1:0] id; - logic [ X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs; - logic [ X_NUM_RS-1:0] rs_valid; - logic [ 5:0] ecs; - logic ecs_valid; + logic [31:0] instr; + logic [1:0] mode; + logic [X_ID_WIDTH-1:0] id; + logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs; + logic [X_NUM_RS-1:0] rs_valid; + logic [5:0] ecs; + logic ecs_valid; } x_issue_req_t; typedef struct packed { @@ -56,41 +56,41 @@ package cv32e40px_core_v_xif_pkg; typedef struct packed { logic [X_ID_WIDTH-1:0] id; - logic commit_kill; + logic commit_kill; } x_commit_t; typedef struct packed { - logic [ X_ID_WIDTH-1:0] id; - logic [ 31:0] addr; - logic [ 1:0] mode; - logic [ 1:0] size; - logic we; + logic [X_ID_WIDTH-1:0] id; + logic [31:0] addr; + logic [1:0] mode; + logic [1:0] size; + logic we; logic [X_MEM_WIDTH-1:0] wdata; - logic last; - logic spec; + logic last; + logic spec; } x_mem_req_t; typedef struct packed { - logic exc; + logic exc; logic [5:0] exccode; - logic dbg; + logic dbg; } x_mem_resp_t; - typedef struct packed { - logic [ X_ID_WIDTH-1:0] id; + typedef struct packed { + logic [X_ID_WIDTH-1:0] id; logic [X_MEM_WIDTH-1:0] rdata; - logic err; - logic dbg; + logic err; + logic dbg; } x_mem_result_t; typedef struct packed { - logic [ X_ID_WIDTH-1:0] id; - logic [ X_RFW_WIDTH-1:0] data; - logic [ 4:0] rd; - logic we; - logic [ 2:0] ecswe; - logic [ 5:0] ecsdata; - logic exc; - logic [ 5:0] exccode; + logic [X_ID_WIDTH-1:0] id; + logic [X_RFW_WIDTH-1:0] data; + logic [4:0] rd; + logic we; + logic [2:0] ecswe; + logic [5:0] ecsdata; + logic exc; + logic [5:0] exccode; } x_result_t; endpackage From e0f581659a131ee875cb907022a5666bc4c077e9 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Wed, 4 Oct 2023 12:50:23 +0200 Subject: [PATCH 09/13] fix undriven signal --- rtl/cv32e40px_ex_stage.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/rtl/cv32e40px_ex_stage.sv b/rtl/cv32e40px_ex_stage.sv index e36b9738a..6ab1b01b3 100644 --- a/rtl/cv32e40px_ex_stage.sv +++ b/rtl/cv32e40px_ex_stage.sv @@ -448,6 +448,7 @@ module cv32e40px_ex_stage assign apu_read_dep_for_jalr_o = 1'b0; assign apu_write_dep_o = 1'b0; assign fpu_fflags_o = '0; + assign fpu_fflags_we_o = '0; end endgenerate From 326891e200365b2558511e6deb8e444eb8daf977 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Wed, 4 Oct 2023 12:51:49 +0200 Subject: [PATCH 10/13] remove unused signals --- rtl/cv32e40px_controller.sv | 1 - rtl/cv32e40px_id_stage.sv | 1 - 2 files changed, 2 deletions(-) diff --git a/rtl/cv32e40px_controller.sv b/rtl/cv32e40px_controller.sv index 2676940da..6516f9321 100644 --- a/rtl/cv32e40px_controller.sv +++ b/rtl/cv32e40px_controller.sv @@ -48,7 +48,6 @@ module cv32e40px_controller import cv32e40px_pkg::*; output logic deassert_we_o, // deassert write enable for next instruction input logic illegal_insn_i, // xif confirmed the invalid instruction - input logic illegal_insn_dec_i, // decoder encountered an invalid instruction input logic ecall_insn_i, // decoder encountered an ecall instruction input logic mret_insn_i, // decoder encountered an mret instruction input logic uret_insn_i, // decoder encountered an uret instruction diff --git a/rtl/cv32e40px_id_stage.sv b/rtl/cv32e40px_id_stage.sv index cb3a41b7b..50df28a0b 100644 --- a/rtl/cv32e40px_id_stage.sv +++ b/rtl/cv32e40px_id_stage.sv @@ -1336,7 +1336,6 @@ module cv32e40px_id_stage .deassert_we_o(deassert_we), .illegal_insn_i(illegal_insn), - .illegal_insn_dec_i(illegal_insn_dec), .ecall_insn_i (ecall_insn_dec), .mret_insn_i (mret_insn_dec), .uret_insn_i (uret_insn_dec), From 28ddffa13abfd42f6e475cfbacb6254040adc847 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 5 Oct 2023 15:59:40 +0200 Subject: [PATCH 11/13] update to newer spec --- rtl/cv32e40px_id_stage.sv | 10 +-- rtl/cv32e40px_x_disp.sv | 4 +- rtl/include/cv32e40px_core_v_xif_pkg.sv | 96 +++++++++++++------------ 3 files changed, 58 insertions(+), 52 deletions(-) diff --git a/rtl/cv32e40px_id_stage.sv b/rtl/cv32e40px_id_stage.sv index 50df28a0b..4c513d272 100644 --- a/rtl/cv32e40px_id_stage.sv +++ b/rtl/cv32e40px_id_stage.sv @@ -1015,7 +1015,7 @@ module cv32e40px_id_stage logic [1:0] x_mem_data_type_id; generate - if (COREV_X_IF) begin : gen_x_disp + if (COREV_X_IF != 0) begin : gen_x_disp //////////////////////////////////////// // __ __ ____ ___ ____ ____ // // \ \/ / | _ \_ _/ ___|| _ \ // @@ -1138,13 +1138,13 @@ module cv32e40px_id_stage always_comb begin x_mem_data_type_id = 2'b00; case (x_mem_req_i.size) - 2'b00: x_mem_data_type_id = 2'b10; // SB - 2'b01: x_mem_data_type_id = 2'b01; // SH - 2'b10: x_mem_data_type_id = 2'b00; // SW + 3'd0: x_mem_data_type_id = 2'b10; // SB + 3'd1: x_mem_data_type_id = 2'b01; // SH + 3'd2: x_mem_data_type_id = 2'b00; // SW + default: x_mem_data_type_id = 2'b00; // SW endcase end - end else begin : gen_no_x_disp // default illegal instruction assignment diff --git a/rtl/cv32e40px_x_disp.sv b/rtl/cv32e40px_x_disp.sv index b2dea3482..71bbf665f 100644 --- a/rtl/cv32e40px_x_disp.sv +++ b/rtl/cv32e40px_x_disp.sv @@ -98,7 +98,7 @@ module cv32e40px_x_disp // scoreboard, id and satus signals logic [31:0] scoreboard_q, scoreboard_d; logic [3:0] id_q, id_d; - logic [3:0] instr_offloaded_q, instr_offloaded_d; + logic instr_offloaded_q, instr_offloaded_d; logic [3:0] mem_counter_q, mem_counter_d; logic dep; logic outstanding_mem; @@ -182,7 +182,7 @@ module cv32e40px_x_disp always_comb begin scoreboard_d = scoreboard_q; if (x_issue_resp_writeback_i & x_issue_valid_o & x_issue_ready_i - & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & x_result_rd_i)) begin + & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & (x_result_rd_i != '0))) begin scoreboard_d[waddr_id_i] = 1'b1; end if (x_result_valid_i & x_result_we_i) begin diff --git a/rtl/include/cv32e40px_core_v_xif_pkg.sv b/rtl/include/cv32e40px_core_v_xif_pkg.sv index ae52789ca..b0473dde2 100644 --- a/rtl/include/cv32e40px_core_v_xif_pkg.sv +++ b/rtl/include/cv32e40px_core_v_xif_pkg.sv @@ -22,75 +22,81 @@ package cv32e40px_core_v_xif_pkg; parameter logic [31:0] X_MISA = '0; parameter logic [1:0] X_ECS_XS = '0; - // interface structs + localparam int XLEN = 32; + typedef struct packed { - logic [15:0] instr; - logic [1:0] mode; - logic [X_ID_WIDTH-1:0] id; + logic [ 15:0] instr; // Offloaded compressed instruction + logic [ 1:0] mode; // Privilege level + logic [X_ID_WIDTH-1:0] id; // Identification number of the offloaded compressed instruction } x_compressed_req_t; typedef struct packed { - logic [31:0] instr; - logic accept; + logic [31:0] instr; // Uncompressed instruction + logic accept; // Is the offloaded compressed instruction (id) accepted by the coprocessor? } x_compressed_resp_t; typedef struct packed { - logic [31:0] instr; - logic [1:0] mode; - logic [X_ID_WIDTH-1:0] id; - logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs; - logic [X_NUM_RS-1:0] rs_valid; - logic [5:0] ecs; - logic ecs_valid; + logic [ 31:0] instr; // Offloaded instruction + logic [ 1:0] mode; // Privilege level + logic [X_ID_WIDTH-1:0] id; // Identification of the offloaded instruction + logic [X_NUM_RS -1:0][X_RFR_WIDTH-1:0] rs; // Register file source operands for the offloaded instruction + logic [X_NUM_RS -1:0] rs_valid; // Validity of the register file source operand(s) + logic [ 5:0] ecs; // Extension Context Status ({mstatus.xs, mstatus.fs, mstatus.vs}) + logic ecs_valid; // Validity of the Extension Context Status } x_issue_req_t; typedef struct packed { - logic accept; - logic writeback; - //logic float; - logic dualwrite; - logic dualread; - logic loadstore; - logic exc; + logic accept; // Is the offloaded instruction (id) accepted by the coprocessor? + logic writeback; // Will the coprocessor perform a writeback in the core to rd? + logic dualwrite; // Will the coprocessor perform a dual writeback in the core to rd and rd+1? + logic [2:0] dualread; // Will the coprocessor require dual reads from rs1\rs2\rs3 and rs1+1\rs2+1\rs3+1? + logic loadstore; // Is the offloaded instruction a load/store instruction? + logic ecswrite ; // Will the coprocessor write the Extension Context Status in mstatus? + logic exc; // Can the offloaded instruction possibly cause a synchronous exception in the coprocessor itself? } x_issue_resp_t; typedef struct packed { - logic [X_ID_WIDTH-1:0] id; - logic commit_kill; + logic [X_ID_WIDTH-1:0] id; // Identification of the offloaded instruction + logic commit_kill; // Shall an offloaded instruction be killed? } x_commit_t; typedef struct packed { - logic [X_ID_WIDTH-1:0] id; - logic [31:0] addr; - logic [1:0] mode; - logic [1:0] size; - logic we; - logic [X_MEM_WIDTH-1:0] wdata; - logic last; - logic spec; + logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction + logic [ 31:0] addr; // Virtual address of the memory transaction + logic [ 1:0] mode; // Privilege level + logic we; // Write enable of the memory transaction + logic [ 2:0] size; // Size of the memory transaction + logic [X_MEM_WIDTH/8-1:0] be; // Byte enables for memory transaction + logic [ 1:0] attr; // Memory transaction attributes + logic [X_MEM_WIDTH -1:0] wdata; // Write data of a store memory transaction + logic last; // Is this the last memory transaction for the offloaded instruction? + logic spec; // Is the memory transaction speculative? } x_mem_req_t; typedef struct packed { - logic exc; - logic [5:0] exccode; - logic dbg; + logic exc; // Did the memory request cause a synchronous exception? + logic [5:0] exccode; // Exception code + logic dbg; // Did the memory request cause a debug trigger match with ``mcontrol.timing`` = 0? } x_mem_resp_t; typedef struct packed { - logic [X_ID_WIDTH-1:0] id; - logic [X_MEM_WIDTH-1:0] rdata; - logic err; - logic dbg; + logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction + logic [X_MEM_WIDTH-1:0] rdata; // Read data of a read memory transaction + logic err; // Did the instruction cause a bus error? + logic dbg; // Did the read data cause a debug trigger match with ``mcontrol.timing`` = 0? } x_mem_result_t; typedef struct packed { - logic [X_ID_WIDTH-1:0] id; - logic [X_RFW_WIDTH-1:0] data; - logic [4:0] rd; - logic we; - logic [2:0] ecswe; - logic [5:0] ecsdata; - logic exc; - logic [5:0] exccode; + logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction + logic [X_RFW_WIDTH -1:0] data; // Register file write data value(s) + logic [ 4:0] rd; // Register file destination address(es) + logic [X_RFW_WIDTH/XLEN-1:0] we; // Register file write enable(s) + logic [ 5:0] ecsdata; // Write data value for {mstatus.xs, mstatus.fs, mstatus.vs} + logic [ 2:0] ecswe; // Write enables for {mstatus.xs, mstatus.fs, mstatus.vs} + logic exc; // Did the instruction cause a synchronous exception? + logic [ 5:0] exccode; // Exception code + logic err; // Did the instruction cause a bus error? + logic dbg; // Did the instruction cause a debug trigger match with ``mcontrol.timing`` = 0? } x_result_t; + endpackage From d81cd5c36616e0fbf28dafd2ca9b202fdcc7b777 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 5 Oct 2023 17:18:35 +0200 Subject: [PATCH 12/13] fix parameter in if_stage --- rtl/cv32e40px_core.sv | 1 + rtl/cv32e40px_if_stage.sv | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/rtl/cv32e40px_core.sv b/rtl/cv32e40px_core.sv index f0fc87967..fc301b914 100644 --- a/rtl/cv32e40px_core.sv +++ b/rtl/cv32e40px_core.sv @@ -463,6 +463,7 @@ module cv32e40px_core // // ////////////////////////////////////////////////// cv32e40px_if_stage #( + .COREV_X_IF (COREV_X_IF), .COREV_PULP (COREV_PULP), .PULP_OBI (PULP_OBI), .PULP_SECURE(PULP_SECURE), diff --git a/rtl/cv32e40px_if_stage.sv b/rtl/cv32e40px_if_stage.sv index a36f89ae3..2b02e0a79 100644 --- a/rtl/cv32e40px_if_stage.sv +++ b/rtl/cv32e40px_if_stage.sv @@ -291,9 +291,9 @@ module cv32e40px_if_stage #( generate - if (COREV_X_IF) begin + if (COREV_X_IF != 0) begin assign x_compressed_valid_o = illegal_c_insn_dec; - assign x_compressed_req_o.instr = instr_aligned; + assign x_compressed_req_o.instr = instr_aligned[15:0]; assign x_compressed_req_o.mode = 2'b00; // Machine Mode assign x_compressed_req_o.id = x_compressed_id_i; From 2c4204dae90c07de14aa24dcca1730637239c4e8 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Thu, 5 Oct 2023 17:31:00 +0200 Subject: [PATCH 13/13] fix verible --- rtl/include/cv32e40px_core_v_xif_pkg.sv | 86 ++++++++++++------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/rtl/include/cv32e40px_core_v_xif_pkg.sv b/rtl/include/cv32e40px_core_v_xif_pkg.sv index b0473dde2..499fec318 100644 --- a/rtl/include/cv32e40px_core_v_xif_pkg.sv +++ b/rtl/include/cv32e40px_core_v_xif_pkg.sv @@ -25,78 +25,78 @@ package cv32e40px_core_v_xif_pkg; localparam int XLEN = 32; typedef struct packed { - logic [ 15:0] instr; // Offloaded compressed instruction - logic [ 1:0] mode; // Privilege level - logic [X_ID_WIDTH-1:0] id; // Identification number of the offloaded compressed instruction + logic [15:0] instr; // Offloaded compressed instruction + logic [1:0] mode; // Privilege level + logic [X_ID_WIDTH-1:0] id; // Identification number of the offloaded compressed instruction } x_compressed_req_t; typedef struct packed { - logic [31:0] instr; // Uncompressed instruction - logic accept; // Is the offloaded compressed instruction (id) accepted by the coprocessor? + logic [31:0] instr; // Uncompressed instruction + logic accept; // Is the offloaded compressed instruction (id) accepted by the coprocessor? } x_compressed_resp_t; typedef struct packed { - logic [ 31:0] instr; // Offloaded instruction - logic [ 1:0] mode; // Privilege level - logic [X_ID_WIDTH-1:0] id; // Identification of the offloaded instruction + logic [31:0] instr; // Offloaded instruction + logic [1:0] mode; // Privilege level + logic [X_ID_WIDTH-1:0] id; // Identification of the offloaded instruction logic [X_NUM_RS -1:0][X_RFR_WIDTH-1:0] rs; // Register file source operands for the offloaded instruction - logic [X_NUM_RS -1:0] rs_valid; // Validity of the register file source operand(s) - logic [ 5:0] ecs; // Extension Context Status ({mstatus.xs, mstatus.fs, mstatus.vs}) - logic ecs_valid; // Validity of the Extension Context Status + logic [X_NUM_RS -1:0] rs_valid; // Validity of the register file source operand(s) + logic [5:0] ecs; // Extension Context Status ({mstatus.xs, mstatus.fs, mstatus.vs}) + logic ecs_valid; // Validity of the Extension Context Status } x_issue_req_t; typedef struct packed { - logic accept; // Is the offloaded instruction (id) accepted by the coprocessor? - logic writeback; // Will the coprocessor perform a writeback in the core to rd? - logic dualwrite; // Will the coprocessor perform a dual writeback in the core to rd and rd+1? + logic accept; // Is the offloaded instruction (id) accepted by the coprocessor? + logic writeback; // Will the coprocessor perform a writeback in the core to rd? + logic dualwrite; // Will the coprocessor perform a dual writeback in the core to rd and rd+1? logic [2:0] dualread; // Will the coprocessor require dual reads from rs1\rs2\rs3 and rs1+1\rs2+1\rs3+1? - logic loadstore; // Is the offloaded instruction a load/store instruction? - logic ecswrite ; // Will the coprocessor write the Extension Context Status in mstatus? + logic loadstore; // Is the offloaded instruction a load/store instruction? + logic ecswrite; // Will the coprocessor write the Extension Context Status in mstatus? logic exc; // Can the offloaded instruction possibly cause a synchronous exception in the coprocessor itself? } x_issue_resp_t; typedef struct packed { - logic [X_ID_WIDTH-1:0] id; // Identification of the offloaded instruction - logic commit_kill; // Shall an offloaded instruction be killed? + logic [X_ID_WIDTH-1:0] id; // Identification of the offloaded instruction + logic commit_kill; // Shall an offloaded instruction be killed? } x_commit_t; typedef struct packed { - logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction - logic [ 31:0] addr; // Virtual address of the memory transaction - logic [ 1:0] mode; // Privilege level - logic we; // Write enable of the memory transaction - logic [ 2:0] size; // Size of the memory transaction - logic [X_MEM_WIDTH/8-1:0] be; // Byte enables for memory transaction - logic [ 1:0] attr; // Memory transaction attributes - logic [X_MEM_WIDTH -1:0] wdata; // Write data of a store memory transaction - logic last; // Is this the last memory transaction for the offloaded instruction? - logic spec; // Is the memory transaction speculative? + logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction + logic [31:0] addr; // Virtual address of the memory transaction + logic [1:0] mode; // Privilege level + logic we; // Write enable of the memory transaction + logic [2:0] size; // Size of the memory transaction + logic [X_MEM_WIDTH/8-1:0] be; // Byte enables for memory transaction + logic [1:0] attr; // Memory transaction attributes + logic [X_MEM_WIDTH -1:0] wdata; // Write data of a store memory transaction + logic last; // Is this the last memory transaction for the offloaded instruction? + logic spec; // Is the memory transaction speculative? } x_mem_req_t; typedef struct packed { - logic exc; // Did the memory request cause a synchronous exception? + logic exc; // Did the memory request cause a synchronous exception? logic [5:0] exccode; // Exception code - logic dbg; // Did the memory request cause a debug trigger match with ``mcontrol.timing`` = 0? + logic dbg; // Did the memory request cause a debug trigger match with ``mcontrol.timing`` = 0? } x_mem_resp_t; typedef struct packed { - logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction + logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction logic [X_MEM_WIDTH-1:0] rdata; // Read data of a read memory transaction - logic err; // Did the instruction cause a bus error? - logic dbg; // Did the read data cause a debug trigger match with ``mcontrol.timing`` = 0? + logic err; // Did the instruction cause a bus error? + logic dbg; // Did the read data cause a debug trigger match with ``mcontrol.timing`` = 0? } x_mem_result_t; typedef struct packed { - logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction - logic [X_RFW_WIDTH -1:0] data; // Register file write data value(s) - logic [ 4:0] rd; // Register file destination address(es) - logic [X_RFW_WIDTH/XLEN-1:0] we; // Register file write enable(s) - logic [ 5:0] ecsdata; // Write data value for {mstatus.xs, mstatus.fs, mstatus.vs} - logic [ 2:0] ecswe; // Write enables for {mstatus.xs, mstatus.fs, mstatus.vs} - logic exc; // Did the instruction cause a synchronous exception? - logic [ 5:0] exccode; // Exception code - logic err; // Did the instruction cause a bus error? - logic dbg; // Did the instruction cause a debug trigger match with ``mcontrol.timing`` = 0? + logic [X_ID_WIDTH -1:0] id; // Identification of the offloaded instruction + logic [X_RFW_WIDTH -1:0] data; // Register file write data value(s) + logic [4:0] rd; // Register file destination address(es) + logic [X_RFW_WIDTH/XLEN-1:0] we; // Register file write enable(s) + logic [5:0] ecsdata; // Write data value for {mstatus.xs, mstatus.fs, mstatus.vs} + logic [2:0] ecswe; // Write enables for {mstatus.xs, mstatus.fs, mstatus.vs} + logic exc; // Did the instruction cause a synchronous exception? + logic [5:0] exccode; // Exception code + logic err; // Did the instruction cause a bus error? + logic dbg; // Did the instruction cause a debug trigger match with ``mcontrol.timing`` = 0? } x_result_t; endpackage