diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index 569d5c26b865..e004d5dfaeb4 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -2154,9 +2154,10 @@
 (rule 1 (val_already_extended (uextend _)) $true)
 (rule 1 (val_already_extended (sextend _)) $true)
 
-;; The result of `icmp` is zero or one, meaning that it's already sign extended
-;; to the full register width.
+;; The result of `icmp`/`fcmp` is zero or one, meaning that it's already sign
+;; extended to the full register width.
 (rule 1 (val_already_extended (icmp _ _ _)) $true)
+(rule 1 (val_already_extended (fcmp _ _ _)) $true)
 
 (type ExtendOp
   (enum
diff --git a/cranelift/filetests/filetests/isa/riscv64/extend.clif b/cranelift/filetests/filetests/isa/riscv64/extend.clif
index 604e31ea5fe9..445671f2c8af 100644
--- a/cranelift/filetests/filetests/isa/riscv64/extend.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/extend.clif
@@ -258,3 +258,21 @@ block0(v0: i8, v1: i64):
 ;   add a0, a0, a1
 ;   ret
 
+
+function %extend_fcmp(f64, f64) -> i64 {
+block0(v0: f64, v1: f64):
+  v3 = fcmp.f64 lt v0, v1
+  v4 = sextend.i64 v3
+  return v4
+}
+
+; VCode:
+; block0:
+;   flt.d a0,fa0,fa1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   flt.d a0, fa0, fa1
+;   ret
+