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Investigate impact of method entry alignment #9912

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AndyAyersMS opened this issue Mar 9, 2018 · 9 comments
Open

Investigate impact of method entry alignment #9912

AndyAyersMS opened this issue Mar 9, 2018 · 9 comments
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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI optimization
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@AndyAyersMS
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AndyAyersMS commented Mar 9, 2018

Current code alignment strategy seems a bit random. Best I can tell it is:

  • on x86 we generally 8 byte align jitted code, but we 16 byte align small methods. When prejitting we 16 byte align IBC hot methods, and otherwise 4 byte align.
  • on x64 we always 8 byte align when jitting and 16 byte align when prejitting 16 byte align.

Haven't looked at arm32 / arm64.

Over-aligning leads to wasted code space; under-aligning leads to possible perf issues ,either poor per or just randomly variable perf, as in #9815.

Generally speaking we'd prefer frequently-called methods to be maximally aligned and rarely called methods be minimally aligned. From a jit standpoint it seems like minopts/debug/tier0 code should always have minimum alignment; tier1 code should have maximum alignment, and the alignment of regularly optimized code is open for discussion.

Also note method entry alignment constrains loop top alignment (#11607).

category:cq
theme:basic-cq
skill-level:expert
cost:large
impact:small

@briansull
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briansull commented Mar 14, 2018

FYI: There might be subtle reasons for some of these choices such as "we 16 byte align small methods" on x86. Because of IP to MethodDesc look ups using a Nibble Map we may not allow more than 1 method per 16-byte region on x86.

AndyAyersMS referenced this issue in AndyAyersMS/coreclr Dec 7, 2018
Align Tier1, small and IBC hot methods to 16 byte boundaries for x64 and x86.
Consensus from various folks I polled was that this isn't as helpful for arm
architectures, so for now this is xarch only.

This ensures that instruction prefetch pulls in as much code as possible.

It should also improve performance stability in some benchmarks, as well as
opening the door for possible loop-top aligment padding.

Resolves #16873.
@AndyAyersMS
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We are already 16 byte aligning on x64, see notes in dotnet/coreclr#21518.

@msftgits msftgits transferred this issue from dotnet/coreclr Jan 31, 2020
@msftgits msftgits added this to the Future milestone Jan 31, 2020
@AndyAyersMS
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We're now 32 byte aligning Tier1 code, see #2249.

@adamsitnik
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We're now 32 byte aligning Tier1 code, see #2249.

@billwert @DrewScoggins this change might affect microbenchmarks. I hope that it's going to improve both the stability and perf

@kunalspathak
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Also note method entry alignment constrains loop top alignment (#11607).

I believe when you say #11607, you really meant #8108.

@AndyAyersMS
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I believe when you say #11607, you really meant #8108.

Yep. Unfortunately a number of issue links didn't get updated when we migrated from coreclr to runtime repo -- 11607 is the issue number over in coreclr.

@kunalspathak
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With #42909, we align method entries containing loops with 32-bytes.

@DrewScoggins
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This is a query that contains tests that we have seen marked as either regressions or improvements that had bimodal behavior, but after #42909, seemed to have stabilized. We should continue to track these and see if that is true.

https://github.com/DrewScoggins/performance-2/issues?q=is%3Aopen+is%3Aissue+label%3AAlignment

@BruceForstall BruceForstall added the JitUntriaged CLR JIT issues needing additional triage label Oct 28, 2020
@kunalspathak
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@AndyAyersMS - have you seen example of non-loop methods whose performance was affected because of misalignment? If not, I propose to close the issue.

@BruceForstall BruceForstall removed the JitUntriaged CLR JIT issues needing additional triage label Jan 24, 2023
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