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coverify

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  1. euvm euvm Public

    Embedded UVM (D Language port of IEEE UVM 1.0)

    D 30 14

  2. axi4reg axi4reg Public

    AXI4 VIP for Reg Verifiation

    SystemVerilog 3 4

  3. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    Random instruction generator for RISC-V processor verification

    D 1 8

  4. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1 1

  5. avst_adder_vl avst_adder_vl Public

    Reference eUVM testbench for verilator

    D 9

  6. verilator verilator Public

    Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    C++ 1

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