{"payload":{"header_redesign_enabled":false,"results":[{"id":"232916517","archived":false,"color":"#DAE1C2","followers":241,"has_funding_file":false,"hl_name":"chipsalliance/Cores-VeeR-EL2","hl_trunc_description":"VeeR EL2 Core","language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":232916517,"name":"Cores-VeeR-EL2","owner_id":46612642,"owner_login":"chipsalliance","updated_at":"2024-08-08T12:58:47.058Z","has_issues":true}},"sponsorable":false,"topics":["fpga","processor","riscv","rtl","risc-v","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","el2"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":43,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Achipsalliance%252FCores-VeeR-EL2%2B%2Blanguage%253ASystemVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/chipsalliance/Cores-VeeR-EL2/star":{"post":"QHuIvBmTzbNCo4oUY1Jw6xz7l2LgfP1Xru8PB4qQuZPz4XWZRrQ8XHwJKOhGBa0euRlPlN8lcIZ_UMM7Re6SaA"},"/chipsalliance/Cores-VeeR-EL2/unstar":{"post":"T7iLQthePEGist91gIzzkVTjAQUtShM0PZmcrRtAeJGwKftPy2hl6dlYaHJ76_Mv2klv5HN0Bw-gmcMAnPtDrQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"XGZHmXrA8UJcAbRGpkbS6PHd2lKj--PHPnifX0NPwRqtz2w4ifujDon1UcftLsBp792zvRA6YNYuEFK59lPJpQ"}}},"title":"Repository search results"}