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p3.gise
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p3.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="p3.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="ALU.vf"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ipcore_dir/RAM_B.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="socmf.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="socmf.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="socmf.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="socmf.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="socmf.drc" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="socmf.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="socmf.par" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="socmf.ptwx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="socmf.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="socmf.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="socmf.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="socmf.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="socmf.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="socmf.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="socmf_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="socmf_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="socmf_map.map" xil_pn:subbranch="Map"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="socmf_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="socmf_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="socmf_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="socmf_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="socmf_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="socmf_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="socmf_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="socmf_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="socmf_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1441287199" xil_pn:in_ck="-2864435316022474004" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7512141847003067708" xil_pn:start_ts="1441287199">
<status xil_pn:value="SuccessfullyRun"/>
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<outfile xil_pn:name="ipcore_dir/RAM_B.ngc"/>
<outfile xil_pn:name="ipcore_dir/RAM_B.v"/>
<outfile xil_pn:name="ipcore_dir/char_ram.ngc"/>
<outfile xil_pn:name="ipcore_dir/char_ram.v"/>
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<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1441178661" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7289283681993271343" xil_pn:start_ts="1441178661">
<status xil_pn:value="SuccessfullyRun"/>
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</transform>
<transform xil_pn:end_ts="1441178661" xil_pn:in_ck="-4518326498899385526" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1106364426758808884" xil_pn:start_ts="1441178661">
<status xil_pn:value="SuccessfullyRun"/>
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</transform>
<transform xil_pn:end_ts="1441178661" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-153030149395898746" xil_pn:start_ts="1441178661">
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<transform xil_pn:end_ts="1441287225" xil_pn:in_ck="-8734209133479401057" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8966374437252326261" xil_pn:start_ts="1441287199">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
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<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="socmf.lso"/>
<outfile xil_pn:name="socmf.ngc"/>
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<outfile xil_pn:name="socmf.prj"/>
<outfile xil_pn:name="socmf.stx"/>
<outfile xil_pn:name="socmf.syr"/>
<outfile xil_pn:name="socmf.xst"/>
<outfile xil_pn:name="socmf_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
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<transform xil_pn:end_ts="1441287232" xil_pn:in_ck="2143595480419052308" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5753010005008763267" xil_pn:start_ts="1441287225">
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</generated_project>