diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs
index 51e3c69f9a13..67d370071027 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/args.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@@ -310,6 +310,10 @@ impl IntegerCompare {
             ..self
         }
     }
+
+    pub(crate) fn regs(&self) -> [Reg; 2] {
+        [self.rs1, self.rs2]
+    }
 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index a3fd4e5db568..4e80f284cfd5 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -1520,25 +1520,68 @@ impl Inst {
                 ref x,
                 ref y,
             } => {
-                let label_true = sink.get_label();
-                let label_false = sink.get_label();
+                // The general form for this select is the following:
+                //
+                //     mv rd, x
+                //     b{cond} rcond, label_end
+                //     mv rd, y
+                // label_end:
+                //     ... etc
+                //
+                // This is built on the assumption that moves are cheap, but branches and jumps
+                // are not. So with this format we always avoid one jump instruction at the expense
+                // of an unconditional move.
+                //
+                // We also perform another optimization here. If the destination register is the same
+                // as one of the input registers, we can avoid emitting the first unconditional move
+                // and emit just the branch and the second move.
+                //
+                // To make sure that this happens as often as possible, we also try to invert the
+                // condition, so that if either of the input registers are the same as the destination
+                // we avoid that move.
+
                 let label_end = sink.get_label();
+
+                let xregs = x.regs();
+                let yregs = y.regs();
+                let dstregs: Vec<Reg> = dst.regs().into_iter().map(|r| r.to_reg()).collect();
+                let condregs = condition.regs();
+
+                // We are going to write to the destination register before evaluating
+                // the condition, so we need to make sure that the destination register
+                // is not one of the condition registers.
+                //
+                // This should never happen, since hopefully the regalloc constraints
+                // for this register are set up correctly.
+                debug_assert_ne!(dstregs, condregs);
+
+                // Check if we can invert the condition and avoid moving the y registers into
+                // the destination. This allows us to only emit the branch and one of the moves.
+                let (uncond_move, cond_move, condition) = if yregs == dstregs {
+                    (yregs, xregs, condition.inverse())
+                } else {
+                    (xregs, yregs, condition)
+                };
+
+                // Unconditonally move one of the values to the destination register.
+                //
+                // These moves may not end up being emitted if the source and
+                // destination registers are the same. That logic is built into
+                // the emit function for `Inst::Mov`.
+                for i in gen_moves(dst.regs(), uncond_move) {
+                    i.emit(sink, emit_info, state);
+                }
+
+                // If the condition passes we skip over the conditional move
                 Inst::CondBr {
-                    taken: CondBrTarget::Label(label_true),
-                    not_taken: CondBrTarget::Label(label_false),
+                    taken: CondBrTarget::Label(label_end),
+                    not_taken: CondBrTarget::Fallthrough,
                     kind: condition,
                 }
                 .emit(sink, emit_info, state);
-                sink.bind_label(label_true, &mut state.ctrl_plane);
-                // here is the true
-                // select the first value
-                for i in gen_moves(dst.regs(), x.regs()) {
-                    i.emit(sink, emit_info, state);
-                }
-                Inst::gen_jump(label_end).emit(sink, emit_info, state);
 
-                sink.bind_label(label_false, &mut state.ctrl_plane);
-                for i in gen_moves(dst.regs(), y.regs()) {
+                // Move the conditional value to the destination register.
+                for i in gen_moves(dst.regs(), cond_move) {
                     i.emit(sink, emit_info, state);
                 }
 
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index 9a950529b387..eee4af1cc9d7 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -459,14 +459,19 @@ fn riscv64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
             y,
             ..
         } => {
-            collector.reg_use(rs1);
-            collector.reg_use(rs2);
+            // Mark the condition registers as late use so that they don't overlap with the destination
+            // register. We may potentially write to the destination register before evaluating the
+            // condition.
+            collector.reg_late_use(rs1);
+            collector.reg_late_use(rs2);
+
             for reg in x.regs_mut() {
                 collector.reg_use(reg);
             }
             for reg in y.regs_mut() {
                 collector.reg_use(reg);
             }
+
             // If there's more than one destination register then use
             // `reg_early_def` to prevent destination registers from overlapping
             // with any operands. This ensures that the lowering doesn't have to
@@ -476,6 +481,8 @@ fn riscv64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
             // When there's only one destination register though don't use an
             // early def because once the register is written no other inputs
             // are read so it's ok for the destination to overlap the sources.
+            // The condition registers are already marked as late use so they
+            // won't overlap with the destination.
             match dst.regs_mut() {
                 [reg] => collector.reg_def(reg),
                 regs => {
diff --git a/cranelift/filetests/filetests/isa/riscv64/bitops.clif b/cranelift/filetests/filetests/isa/riscv64/bitops.clif
index 5081928dd7d2..724afe20809a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/bitops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/bitops.clif
@@ -154,9 +154,8 @@ block0(v0: i128):
 ;   addi a2, a2, -1
 ;   srli a4, a4, 1
 ;   j -0x18
-;   bnez a1, 0xc
 ;   mv a0, a3
-;   j 8
+;   beqz a1, 8
 ;   mv a0, zero
 ;   add a0, a5, a0
 ;   mv a1, zero
@@ -183,9 +182,8 @@ block0(v0: i8):
 ;   slli a2, a0, 0x38
 ;   srai a4, a2, 0x38
 ;   not a0, a4
-;   bgez a4, 0xc
 ;   mv a2, a0
-;   j 8
+;   bltz a4, 8
 ;   mv a2, a4
 ;   mv a0, zero
 ;   addi a5, zero, 0x40
@@ -222,9 +220,8 @@ block0(v0: i16):
 ;   slli a2, a0, 0x30
 ;   srai a4, a2, 0x30
 ;   not a0, a4
-;   bgez a4, 0xc
 ;   mv a2, a0
-;   j 8
+;   bltz a4, 8
 ;   mv a2, a4
 ;   mv a0, zero
 ;   addi a5, zero, 0x40
@@ -259,9 +256,8 @@ block0(v0: i32):
 ; block0: ; offset 0x0
 ;   sext.w a2, a0
 ;   not a4, a2
-;   bgez a2, 0xc
 ;   mv a0, a4
-;   j 8
+;   bltz a2, 8
 ;   mv a0, a2
 ;   mv a4, zero
 ;   addi a3, zero, 0x40
@@ -294,9 +290,8 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   not a2, a0
-;   bgez a0, 0xc
 ;   mv a4, a2
-;   j 8
+;   bltz a0, 8
 ;   mv a4, a0
 ;   mv a2, zero
 ;   addi a1, zero, 0x40
@@ -335,14 +330,12 @@ block0(v0: i128):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   not a3, a0
-;   bgez a1, 0xc
 ;   mv a5, a3
-;   j 8
+;   bltz a1, 8
 ;   mv a5, a0
 ;   not a2, a1
-;   bgez a1, 0xc
 ;   mv a3, a2
-;   j 8
+;   bltz a1, 8
 ;   mv a3, a1
 ;   mv a1, zero
 ;   addi a0, zero, 0x40
@@ -366,9 +359,8 @@ block0(v0: i128):
 ;   addi a4, a4, -1
 ;   srli a2, a2, 1
 ;   j -0x18
-;   bnez a3, 0xc
 ;   mv a2, a0
-;   j 8
+;   beqz a3, 8
 ;   mv a2, zero
 ;   add a3, a1, a2
 ;   addi a0, a3, -1
@@ -1444,10 +1436,10 @@ block0(v0: i128, v1: i8):
 ;   srl a0,a0,a3
 ;   select a3,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a3,a5
+;   or t0,a3,a5
 ;   li a3,64
-;   andi a2,a2,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a2 uge a3)
+;   andi a5,a2,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a3)
 ;   ret
 ;
 ; Disassembled:
@@ -1457,20 +1449,18 @@ block0(v0: i128, v1: i8):
 ;   sub a3, a3, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a3
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a0
 ;   sll a5, a1, a5
-;   or a5, a3, a5
+;   or t0, a3, a5
 ;   addi a3, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
+;   andi a5, a2, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
@@ -1511,10 +1501,9 @@ block0(v0: i128, v1: i128):
 ;   or a4, a3, a0
 ;   addi a3, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
 ;   mv a0, zero
 ;   mv a1, a5
-;   j 0xc
+;   bgeu a2, a3, 0xc
 ;   mv a0, a5
 ;   mv a1, a4
 ;   ret
@@ -1546,19 +1535,17 @@ block0(v0: i128, v1: i8):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi t0, zero, 0x40
 ;   srl a3, a1, a4
 ;   andi a4, a2, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a3
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -1615,10 +1602,9 @@ block0(v0: i128, v1: i128):
 ;   addi a3, zero, 0x40
 ;   srl a4, a1, a5
 ;   andi a5, a2, 0x7f
-;   bltu a5, a3, 0x10
 ;   mv a0, a4
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, s11
 ;   mv a1, a4
 ;   ld s11, 8(sp)
@@ -1658,25 +1644,22 @@ block0(v0: i128, v1: i8):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -1740,10 +1723,9 @@ block0(v0: i128, v1: i128):
 ;   mv a5, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, a5
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, s11
 ;   mv a1, a3
 ;   ld s11, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/brif.clif b/cranelift/filetests/filetests/isa/riscv64/brif.clif
index aee4456047d7..f998b0bf5da8 100644
--- a/cranelift/filetests/filetests/isa/riscv64/brif.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/brif.clif
@@ -349,34 +349,66 @@ block2:
 }
 
 ; VCode:
+;   addi sp,sp,-16
+;   sd ra,8(sp)
+;   sd fp,0(sp)
+;   mv fp,sp
+;   addi sp,sp,-16
+;   sd s1,8(sp)
 ; block0:
-;   slt a5,a3,a1
+;   slt s1,a3,a1
 ;   sltu a4,a2,a0
-;   xor a0,a3,a1
-;   select a1,a4,a5##condition=(a0 eq zero)
+;   xor a5,a3,a1
+;   select a1,a4,s1##condition=(a5 eq zero)
 ;   bne a1,zero,taken(label2),not_taken(label1)
 ; block1:
 ;   li a0,0
+;   ld s1,8(sp)
+;   addi sp,sp,16
+;   ld ra,8(sp)
+;   ld fp,0(sp)
+;   addi sp,sp,16
 ;   ret
 ; block2:
 ;   li a0,1
+;   ld s1,8(sp)
+;   addi sp,sp,16
+;   ld ra,8(sp)
+;   ld fp,0(sp)
+;   addi sp,sp,16
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slt a5, a3, a1
+;   addi sp, sp, -0x10
+;   sd ra, 8(sp)
+;   sd s0, 0(sp)
+;   mv s0, sp
+;   addi sp, sp, -0x10
+;   sd s1, 8(sp)
+; block1: ; offset 0x18
+;   slt s1, a3, a1
 ;   sltu a4, a2, a0
-;   xor a0, a3, a1
-;   bnez a0, 0xc
+;   xor a5, a3, a1
 ;   mv a1, a4
-;   j 8
-;   mv a1, a5
-;   bnez a1, 0xc
-; block1: ; offset 0x20
+;   beqz a5, 8
+;   mv a1, s1
+;   bnez a1, 0x20
+; block2: ; offset 0x34
 ;   mv a0, zero
+;   ld s1, 8(sp)
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
 ;   ret
-; block2: ; offset 0x28
+; block3: ; offset 0x50
 ;   addi a0, zero, 1
+;   ld s1, 8(sp)
+;   addi sp, sp, 0x10
+;   ld ra, 8(sp)
+;   ld s0, 0(sp)
+;   addi sp, sp, 0x10
 ;   ret
 
 function %brif_fcmp_f32(f32, f32) -> i8 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/ceil.clif b/cranelift/filetests/filetests/isa/riscv64/ceil.clif
index f7f0a32e91e4..8958ea25e6e9 100644
--- a/cranelift/filetests/filetests/isa/riscv64/ceil.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/ceil.clif
@@ -71,9 +71,8 @@ block0(v0: f64):
 ;   fsgnj.d fa4, fa2, fa0
 ;   fmv.d.x fa1, zero
 ;   fadd.d fa2, fa0, fa1, rne
-;   bnez a4, 0xc
 ;   fmv.d fa0, fa2
-;   j 8
+;   beqz a4, 8
 ;   fmv.d fa0, fa4
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/cls-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/cls-zbb.clif
index 1477bb8ba5d4..229b157beedf 100644
--- a/cranelift/filetests/filetests/isa/riscv64/cls-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/cls-zbb.clif
@@ -22,9 +22,8 @@ block0(v0: i8):
 ; block0: ; offset 0x0
 ;   .byte 0x13, 0x16, 0x45, 0x60
 ;   not a4, a2
-;   bgez a2, 0xc
 ;   mv a0, a4
-;   j 8
+;   bltz a2, 8
 ;   mv a0, a2
 ;   .byte 0x13, 0x16, 0x05, 0x60
 ;   addi a0, a2, -0x39
@@ -49,9 +48,8 @@ block0(v0: i16):
 ; block0: ; offset 0x0
 ;   .byte 0x13, 0x16, 0x55, 0x60
 ;   not a4, a2
-;   bgez a2, 0xc
 ;   mv a0, a4
-;   j 8
+;   bltz a2, 8
 ;   mv a0, a2
 ;   .byte 0x13, 0x16, 0x05, 0x60
 ;   addi a0, a2, -0x31
@@ -76,9 +74,8 @@ block0(v0: i32):
 ; block0: ; offset 0x0
 ;   sext.w a2, a0
 ;   not a4, a2
-;   bgez a2, 0xc
 ;   mv a0, a4
-;   j 8
+;   bltz a2, 8
 ;   mv a0, a2
 ;   .byte 0x13, 0x16, 0x05, 0x60
 ;   addi a0, a2, -0x21
@@ -101,9 +98,8 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   not a2, a0
-;   bgez a0, 0xc
 ;   mv a4, a2
-;   j 8
+;   bltz a0, 8
 ;   mv a4, a0
 ;   .byte 0x13, 0x15, 0x07, 0x60
 ;   addi a0, a0, -1
@@ -123,8 +119,8 @@ block0(v0: i128):
 ;   select a3,a2,a1##condition=(a1 slt zero)
 ;   clz a0,a3
 ;   clz a1,a5
-;   select a3,a1,zero##condition=(a3 eq zero)
-;   add a5,a0,a3
+;   select a4,a1,zero##condition=(a3 eq zero)
+;   add a5,a0,a4
 ;   addi a0,a5,-1
 ;   li a1,0
 ;   ret
@@ -132,22 +128,19 @@ block0(v0: i128):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   not a3, a0
-;   bgez a1, 0xc
 ;   mv a5, a3
-;   j 8
+;   bltz a1, 8
 ;   mv a5, a0
 ;   not a2, a1
-;   bgez a1, 0xc
 ;   mv a3, a2
-;   j 8
+;   bltz a1, 8
 ;   mv a3, a1
 ;   .byte 0x13, 0x95, 0x06, 0x60
 ;   .byte 0x93, 0x95, 0x07, 0x60
-;   bnez a3, 0xc
-;   mv a3, a1
-;   j 8
-;   mv a3, zero
-;   add a5, a0, a3
+;   mv a4, a1
+;   beqz a3, 8
+;   mv a4, zero
+;   add a5, a0, a4
 ;   addi a0, a5, -1
 ;   mv a1, zero
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/clz-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/clz-zbb.clif
index fda9f412930d..41789817995e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/clz-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/clz-zbb.clif
@@ -84,8 +84,8 @@ block0(v0: i128):
 ; block0:
 ;   clz a3,a1
 ;   clz a5,a0
-;   select a1,a5,zero##condition=(a1 eq zero)
-;   add a0,a3,a1
+;   select a2,a5,zero##condition=(a1 eq zero)
+;   add a0,a3,a2
 ;   li a1,0
 ;   ret
 ;
@@ -93,11 +93,10 @@ block0(v0: i128):
 ; block0: ; offset 0x0
 ;   .byte 0x93, 0x96, 0x05, 0x60
 ;   .byte 0x93, 0x17, 0x05, 0x60
-;   bnez a1, 0xc
-;   mv a1, a5
-;   j 8
-;   mv a1, zero
-;   add a0, a3, a1
+;   mv a2, a5
+;   beqz a1, 8
+;   mv a2, zero
+;   add a0, a3, a2
 ;   mv a1, zero
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condbr.clif b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
index 9ac16eec16ad..6912c0b5502e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condbr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
@@ -83,9 +83,8 @@ block0(v0: i128, v1: i128):
 ;   slt a5, a1, a3
 ;   sltu a2, a0, a2
 ;   xor a3, a1, a3
-;   bnez a3, 0xc
 ;   mv a0, a2
-;   j 8
+;   beqz a3, 8
 ;   mv a0, a5
 ;   ret
 
@@ -108,9 +107,8 @@ block0(v0: i128, v1: i128):
 ;   sltu a5, a1, a3
 ;   sltu a2, a0, a2
 ;   xor a3, a1, a3
-;   bnez a3, 0xc
 ;   mv a0, a2
-;   j 8
+;   beqz a3, 8
 ;   mv a0, a5
 ;   ret
 
@@ -183,9 +181,8 @@ block0(v0: i128, v1: i128):
 ;   slt a5, a3, a1
 ;   sltu a2, a2, a0
 ;   xor a3, a3, a1
-;   bnez a3, 0xc
 ;   mv a0, a2
-;   j 8
+;   beqz a3, 8
 ;   mv a0, a5
 ;   ret
 
@@ -208,9 +205,8 @@ block0(v0: i128, v1: i128):
 ;   sltu a5, a3, a1
 ;   sltu a2, a2, a0
 ;   xor a3, a3, a1
-;   bnez a3, 0xc
 ;   mv a0, a2
-;   j 8
+;   beqz a3, 8
 ;   mv a0, a5
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condops.clif b/cranelift/filetests/filetests/isa/riscv64/condops.clif
index 1f2f5dfa8daa..f134e0dde614 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condops.clif
@@ -23,9 +23,8 @@ block0(v0: i8, v1: i64, v2: i64):
 ;   addi a3, zero, 0x2a
 ;   andi a5, a0, 0xff
 ;   andi a3, a3, 0xff
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -89,9 +88,8 @@ block0(v0: i8, v1: i8, v2: i8):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   andi a4, a0, 0xff
-;   beqz a4, 0xc
 ;   mv a0, a1
-;   j 8
+;   bnez a4, 8
 ;   mv a0, a2
 ;   ret
 
@@ -116,9 +114,8 @@ block0(v0: i32, v1: i8, v2: i8):
 ;   addi a3, zero, 0x2a
 ;   sext.w a5, a0
 ;   sext.w a3, a3
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -157,10 +154,9 @@ block0(v0: i8, v1: i128, v2: i128):
 ; block1: ; offset 0x18
 ;   mv s4, a1
 ;   andi a5, a0, 0xff
-;   beqz a5, 0x10
 ;   mv a0, s4
 ;   mv a1, a2
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a3
 ;   mv a1, a4
 ;   ld s4, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/ctz-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/ctz-zbb.clif
index d5959eb63d3c..97c6ba309dfa 100644
--- a/cranelift/filetests/filetests/isa/riscv64/ctz-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/ctz-zbb.clif
@@ -92,9 +92,8 @@ block0(v0: i128):
 ; block0: ; offset 0x0
 ;   .byte 0x93, 0x96, 0x15, 0x60
 ;   .byte 0x93, 0x17, 0x15, 0x60
-;   bnez a0, 0xc
 ;   mv a1, a3
-;   j 8
+;   beqz a0, 8
 ;   mv a1, zero
 ;   add a0, a5, a1
 ;   mv a1, zero
diff --git a/cranelift/filetests/filetests/isa/riscv64/floor.clif b/cranelift/filetests/filetests/isa/riscv64/floor.clif
index 0ccdc91839fd..87d37139de96 100644
--- a/cranelift/filetests/filetests/isa/riscv64/floor.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/floor.clif
@@ -71,9 +71,8 @@ block0(v0: f64):
 ;   fsgnj.d fa4, fa2, fa0
 ;   fmv.d.x fa1, zero
 ;   fadd.d fa2, fa0, fa1, rne
-;   bnez a4, 0xc
 ;   fmv.d fa0, fa2
-;   j 8
+;   beqz a4, 8
 ;   fmv.d fa0, fa4
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/fmax.clif b/cranelift/filetests/filetests/isa/riscv64/fmax.clif
index c7939f36b57e..456ad8ca0823 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fmax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fmax.clif
@@ -25,9 +25,8 @@ block0(v0: f32, v1: f32):
 ;   and a1, a3, a5
 ;   fadd.s fa3, fa0, fa1, rne
 ;   fmax.s fa5, fa0, fa1
-;   beqz a1, 0xc
 ;   fmv.d fa0, fa5
-;   j 8
+;   bnez a1, 8
 ;   fmv.d fa0, fa3
 ;   ret
 
@@ -54,9 +53,8 @@ block0(v0: f64, v1: f64):
 ;   and a1, a3, a5
 ;   fadd.d fa3, fa0, fa1, rne
 ;   fmax.d fa5, fa0, fa1
-;   beqz a1, 0xc
 ;   fmv.d fa0, fa5
-;   j 8
+;   bnez a1, 8
 ;   fmv.d fa0, fa3
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/fmin.clif b/cranelift/filetests/filetests/isa/riscv64/fmin.clif
index cdc3b15bbdf2..dd208cb24a60 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fmin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fmin.clif
@@ -25,9 +25,8 @@ block0(v0: f32, v1: f32):
 ;   and a1, a3, a5
 ;   fadd.s fa3, fa0, fa1, rne
 ;   fmin.s fa5, fa0, fa1
-;   beqz a1, 0xc
 ;   fmv.d fa0, fa5
-;   j 8
+;   bnez a1, 8
 ;   fmv.d fa0, fa3
 ;   ret
 
@@ -54,9 +53,8 @@ block0(v0: f64, v1: f64):
 ;   and a1, a3, a5
 ;   fadd.d fa3, fa0, fa1, rne
 ;   fmin.d fa5, fa0, fa1
-;   beqz a1, 0xc
 ;   fmv.d fa0, fa5
-;   j 8
+;   bnez a1, 8
 ;   fmv.d fa0, fa3
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/iabs.clif b/cranelift/filetests/filetests/isa/riscv64/iabs.clif
index 6a91b7cb1dde..8c8290a8966e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/iabs.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iabs.clif
@@ -11,17 +11,18 @@ block0(v0: i8):
 ; block0:
 ;   slli a2,a0,56
 ;   srai a4,a2,56
-;   sub a0,zero,a4
-;   select a0,a4,a0##condition=(a4 sgt a0)
+;   sub a1,zero,a4
+;   select a0,a4,a1##condition=(a4 sgt a1)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a2, a0, 0x38
 ;   srai a4, a2, 0x38
-;   neg a0, a4
-;   bge a0, a4, 8
+;   neg a1, a4
 ;   mv a0, a4
+;   blt a1, a4, 8
+;   mv a0, a1
 ;   ret
 
 function %iabs_i16(i16) -> i16 {
@@ -34,17 +35,18 @@ block0(v0: i16):
 ; block0:
 ;   slli a2,a0,48
 ;   srai a4,a2,48
-;   sub a0,zero,a4
-;   select a0,a4,a0##condition=(a4 sgt a0)
+;   sub a1,zero,a4
+;   select a0,a4,a1##condition=(a4 sgt a1)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a2, a0, 0x30
 ;   srai a4, a2, 0x30
-;   neg a0, a4
-;   bge a0, a4, 8
+;   neg a1, a4
 ;   mv a0, a4
+;   blt a1, a4, 8
+;   mv a0, a1
 ;   ret
 
 function %iabs_i32(i32) -> i32 {
@@ -64,9 +66,8 @@ block0(v0: i32):
 ; block0: ; offset 0x0
 ;   sext.w a2, a0
 ;   neg a4, a2
-;   bge a4, a2, 0xc
 ;   mv a0, a2
-;   j 8
+;   blt a4, a2, 8
 ;   mv a0, a4
 ;   ret
 
@@ -79,13 +80,16 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   sub a2,zero,a0
-;   select a0,a0,a2##condition=(a0 sgt a2)
+;   mv a5,a0
+;   select a0,a5,a2##condition=(a5 sgt a2)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   neg a2, a0
-;   blt a2, a0, 8
+;   mv a5, a0
+;   mv a0, a5
+;   blt a2, a5, 8
 ;   mv a0, a2
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/ishl-const.clif b/cranelift/filetests/filetests/isa/riscv64/ishl-const.clif
index c46b536daa88..d50f69938565 100644
--- a/cranelift/filetests/filetests/isa/riscv64/ishl-const.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/ishl-const.clif
@@ -364,10 +364,10 @@ block0(v0: i128):
 ;   srl a0,a0,a2
 ;   select a2,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a2,a5
+;   or t0,a2,a5
 ;   li a2,64
-;   andi a3,a3,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a3 uge a2)
+;   andi a5,a3,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a2)
 ;   ret
 ;
 ; Disassembled:
@@ -378,20 +378,18 @@ block0(v0: i128):
 ;   sub a2, a2, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a2
-;   bnez a5, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a2, a0
 ;   sll a5, a1, a5
-;   or a5, a2, a5
+;   or t0, a2, a5
 ;   addi a2, zero, 0x40
-;   andi a3, a3, 0x7f
-;   bltu a3, a2, 0x10
+;   andi a5, a3, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a2, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_const_i16(i128) -> i128 {
@@ -411,10 +409,10 @@ block0(v0: i128):
 ;   srl a0,a0,a2
 ;   select a2,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a2,a5
+;   or t0,a2,a5
 ;   li a2,64
-;   andi a3,a3,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a3 uge a2)
+;   andi a5,a3,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a2)
 ;   ret
 ;
 ; Disassembled:
@@ -425,20 +423,18 @@ block0(v0: i128):
 ;   sub a2, a2, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a2
-;   bnez a5, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a2, a0
 ;   sll a5, a1, a5
-;   or a5, a2, a5
+;   or t0, a2, a5
 ;   addi a2, zero, 0x40
-;   andi a3, a3, 0x7f
-;   bltu a3, a2, 0x10
+;   andi a5, a3, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a2, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_const_i32(i128) -> i128 {
@@ -458,10 +454,10 @@ block0(v0: i128):
 ;   srl a0,a0,a2
 ;   select a2,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a2,a5
+;   or t0,a2,a5
 ;   li a2,64
-;   andi a3,a3,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a3 uge a2)
+;   andi a5,a3,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a2)
 ;   ret
 ;
 ; Disassembled:
@@ -472,20 +468,18 @@ block0(v0: i128):
 ;   sub a2, a2, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a2
-;   bnez a5, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a2, a0
 ;   sll a5, a1, a5
-;   or a5, a2, a5
+;   or t0, a2, a5
 ;   addi a2, zero, 0x40
-;   andi a3, a3, 0x7f
-;   bltu a3, a2, 0x10
+;   andi a5, a3, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a2, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_const_i64(i128) -> i128 {
@@ -505,10 +499,10 @@ block0(v0: i128):
 ;   srl a0,a0,a2
 ;   select a2,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a2,a5
+;   or t0,a2,a5
 ;   li a2,64
-;   andi a3,a3,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a3 uge a2)
+;   andi a5,a3,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a2)
 ;   ret
 ;
 ; Disassembled:
@@ -519,20 +513,18 @@ block0(v0: i128):
 ;   sub a2, a2, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a2
-;   bnez a5, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a2, a0
 ;   sll a5, a1, a5
-;   or a5, a2, a5
+;   or t0, a2, a5
 ;   addi a2, zero, 0x40
-;   andi a3, a3, 0x7f
-;   bltu a3, a2, 0x10
+;   andi a5, a3, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a2, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_const_i128(i128) -> i128 {
@@ -575,10 +567,9 @@ block0(v0: i128):
 ;   or a2, a3, a0
 ;   addi a3, zero, 0x40
 ;   andi a4, a4, 0x7f
-;   bltu a4, a3, 0x10
 ;   mv a0, zero
 ;   mv a1, a5
-;   j 0xc
+;   bgeu a4, a3, 0xc
 ;   mv a0, a5
 ;   mv a1, a2
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/ishl.clif b/cranelift/filetests/filetests/isa/riscv64/ishl.clif
index 3dbb73cdd11b..bff7536722b8 100644
--- a/cranelift/filetests/filetests/isa/riscv64/ishl.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/ishl.clif
@@ -358,10 +358,10 @@ block0(v0: i128, v1: i8):
 ;   srl a0,a0,a3
 ;   select a3,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a3,a5
+;   or t0,a3,a5
 ;   li a3,64
-;   andi a2,a2,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a2 uge a3)
+;   andi a5,a2,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a3)
 ;   ret
 ;
 ; Disassembled:
@@ -371,20 +371,18 @@ block0(v0: i128, v1: i8):
 ;   sub a3, a3, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a3
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a0
 ;   sll a5, a1, a5
-;   or a5, a3, a5
+;   or t0, a3, a5
 ;   addi a3, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
+;   andi a5, a2, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_i16(i128, i16) -> i128 {
@@ -402,10 +400,10 @@ block0(v0: i128, v1: i16):
 ;   srl a0,a0,a3
 ;   select a3,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a3,a5
+;   or t0,a3,a5
 ;   li a3,64
-;   andi a2,a2,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a2 uge a3)
+;   andi a5,a2,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a3)
 ;   ret
 ;
 ; Disassembled:
@@ -415,20 +413,18 @@ block0(v0: i128, v1: i16):
 ;   sub a3, a3, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a3
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a0
 ;   sll a5, a1, a5
-;   or a5, a3, a5
+;   or t0, a3, a5
 ;   addi a3, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
+;   andi a5, a2, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_i32(i128, i32) -> i128 {
@@ -446,10 +442,10 @@ block0(v0: i128, v1: i32):
 ;   srl a0,a0,a3
 ;   select a3,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a3,a5
+;   or t0,a3,a5
 ;   li a3,64
-;   andi a2,a2,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a2 uge a3)
+;   andi a5,a2,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a3)
 ;   ret
 ;
 ; Disassembled:
@@ -459,20 +455,18 @@ block0(v0: i128, v1: i32):
 ;   sub a3, a3, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a3
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a0
 ;   sll a5, a1, a5
-;   or a5, a3, a5
+;   or t0, a3, a5
 ;   addi a3, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
+;   andi a5, a2, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_i64(i128, i64) -> i128 {
@@ -490,10 +484,10 @@ block0(v0: i128, v1: i64):
 ;   srl a0,a0,a3
 ;   select a3,zero,a0##condition=(a5 eq zero)
 ;   sll a5,a1,a5
-;   or a5,a3,a5
+;   or t0,a3,a5
 ;   li a3,64
-;   andi a2,a2,127
-;   select [a0,a1],[zero,a4],[a4,a5]##condition=(a2 uge a3)
+;   andi a5,a2,127
+;   select [a0,a1],[zero,a4],[a4,t0]##condition=(a5 uge a3)
 ;   ret
 ;
 ; Disassembled:
@@ -503,20 +497,18 @@ block0(v0: i128, v1: i64):
 ;   sub a3, a3, a5
 ;   sll a4, a0, a5
 ;   srl a0, a0, a3
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a0
 ;   sll a5, a1, a5
-;   or a5, a3, a5
+;   or t0, a3, a5
 ;   addi a3, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
+;   andi a5, a2, 0x7f
 ;   mv a0, zero
 ;   mv a1, a4
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, a4
-;   mv a1, a5
+;   mv a1, t0
 ;   ret
 
 function %ishl_i128_i128(i128, i128) -> i128 {
@@ -557,10 +549,9 @@ block0(v0: i128, v1: i128):
 ;   or a4, a3, a0
 ;   addi a3, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a3, 0x10
 ;   mv a0, zero
 ;   mv a1, a5
-;   j 0xc
+;   bgeu a2, a3, 0xc
 ;   mv a0, a5
 ;   mv a1, a4
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/issue-6954.clif b/cranelift/filetests/filetests/isa/riscv64/issue-6954.clif
index 8984e97079c8..de62542f1db3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/issue-6954.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/issue-6954.clif
@@ -353,15 +353,13 @@ block0(v0: i16, v1: f32, v2: f64x2, v3: i32, v4: i8, v5: i64x2, v6: i8, v7: f32x
 ;   sw a3, 0x178(sp)
 ;   sh a2, 0x17c(sp)
 ;   sext.w a4, a1
-;   beqz a4, 0xc
 ;   .byte 0x57, 0x37, 0xf0, 0x9e
-;   j 8
+;   bnez a4, 8
 ;   .byte 0x57, 0x37, 0xf0, 0x9e
 ;   sext.w a4, a1
 ;   sext.w a4, a1
-;   beqz a4, 0xc
 ;   .byte 0xd7, 0x37, 0xe0, 0x9e
-;   j 8
+;   bnez a4, 8
 ;   .byte 0xd7, 0x37, 0xe0, 0x9e
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0x17, 0xa0, 0x4e
@@ -408,15 +406,13 @@ block0(v0: i16, v1: f32, v2: f64x2, v3: i32, v4: i8, v5: i64x2, v6: i8, v7: f32x
 ;   sc.w.aqrl a3, t5, (a1) ; trap: heap_oob
 ;   bnez a3, -0x34
 ;   mv a1, a4
-;   beqz a0, 0xc
 ;   .byte 0x57, 0x36, 0xf0, 0x9e
-;   j 8
+;   bnez a0, 8
 ;   .byte 0x57, 0x36, 0xf0, 0x9e
 ;   addi t6, sp, 0x21
 ;   .byte 0xa7, 0xf6, 0x0f, 0x02
-;   beqz a0, 0xc
 ;   .byte 0xd7, 0x36, 0xc0, 0x9e
-;   j 8
+;   bnez a0, 8
 ;   .byte 0xd7, 0x36, 0xc0, 0x9e
 ;   .byte 0x57, 0x70, 0x08, 0xcc
 ;   .byte 0x27, 0x07, 0x08, 0x02
diff --git a/cranelift/filetests/filetests/isa/riscv64/nan-canonicalization.clif b/cranelift/filetests/filetests/isa/riscv64/nan-canonicalization.clif
index 8f74386aff39..41f2f7792562 100644
--- a/cranelift/filetests/filetests/isa/riscv64/nan-canonicalization.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/nan-canonicalization.clif
@@ -58,9 +58,8 @@ block0(v0: f32, v1: f32):
 ;   feq.s a0, fa3, fa3
 ;   feq.s a2, fa3, fa3
 ;   and a4, a0, a2
-;   bnez a4, 0xc
 ;   fmv.d fa0, fa4
-;   j 8
+;   beqz a4, 8
 ;   fmv.d fa0, fa3
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/nearest.clif b/cranelift/filetests/filetests/isa/riscv64/nearest.clif
index 166248c1c93a..d1d6a284323f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/nearest.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/nearest.clif
@@ -70,9 +70,8 @@ block0(v0: f64):
 ;   fsgnj.d fa4, fa2, fa0
 ;   fmv.d.x fa1, zero
 ;   fadd.d fa2, fa0, fa1, rne
-;   bnez a4, 0xc
 ;   fmv.d fa0, fa2
-;   j 8
+;   beqz a4, 8
 ;   fmv.d fa0, fa4
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/rotl.clif b/cranelift/filetests/filetests/isa/riscv64/rotl.clif
index 152f01755b34..baa526eae016 100644
--- a/cranelift/filetests/filetests/isa/riscv64/rotl.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/rotl.clif
@@ -13,9 +13,10 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-16
-;   sd s7,8(sp)
-;   sd s9,0(sp)
+;   addi sp,sp,-32
+;   sd s1,24(sp)
+;   sd s7,16(sp)
+;   sd s9,8(sp)
 ; block0:
 ;   andi a5,a2,63
 ;   li a3,64
@@ -26,14 +27,15 @@ block0(v0: i128, v1: i128):
 ;   or a3,a3,s9
 ;   sll a1,a1,a5
 ;   srl a4,a0,a4
-;   select a5,zero,a4##condition=(a5 eq zero)
-;   or a5,a1,a5
+;   select a0,zero,a4##condition=(a5 eq zero)
+;   or s1,a1,a0
 ;   li a4,64
-;   andi a2,a2,127
-;   select [a0,a1],[a5,a3],[a3,a5]##condition=(a2 uge a4)
-;   ld s7,8(sp)
-;   ld s9,0(sp)
-;   addi sp,sp,16
+;   andi a5,a2,127
+;   select [a0,a1],[s1,a3],[a3,s1]##condition=(a5 uge a4)
+;   ld s1,24(sp)
+;   ld s7,16(sp)
+;   ld s9,8(sp)
+;   addi sp,sp,32
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -45,38 +47,37 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
-;   sd s9, 0(sp)
-; block1: ; offset 0x1c
+;   addi sp, sp, -0x20
+;   sd s1, 0x18(sp)
+;   sd s7, 0x10(sp)
+;   sd s9, 8(sp)
+; block1: ; offset 0x20
 ;   andi a5, a2, 0x3f
 ;   addi a3, zero, 0x40
 ;   sub a4, a3, a5
 ;   sll a3, a0, a5
 ;   srl s7, a1, a4
-;   bnez a5, 0xc
 ;   mv s9, zero
-;   j 8
+;   beqz a5, 8
 ;   mv s9, s7
 ;   or a3, a3, s9
 ;   sll a1, a1, a5
 ;   srl a4, a0, a4
-;   bnez a5, 0xc
-;   mv a5, zero
-;   j 8
-;   mv a5, a4
-;   or a5, a1, a5
+;   mv a0, zero
+;   beqz a5, 8
+;   mv a0, a4
+;   or s1, a1, a0
 ;   addi a4, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
-;   mv a0, a5
+;   andi a5, a2, 0x7f
+;   mv a0, s1
 ;   mv a1, a3
-;   j 0xc
+;   bgeu a5, a4, 0xc
 ;   mv a0, a3
-;   mv a1, a5
-;   ld s7, 8(sp)
-;   ld s9, 0(sp)
-;   addi sp, sp, 0x10
+;   mv a1, s1
+;   ld s1, 0x18(sp)
+;   ld s7, 0x10(sp)
+;   ld s9, 8(sp)
+;   addi sp, sp, 0x20
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -106,9 +107,8 @@ block0(v0: i64, v1: i64):
 ;   sub a1, a5, a3
 ;   sll a4, a0, a3
 ;   srl a5, a0, a1
-;   bnez a3, 0xc
 ;   mv a1, zero
-;   j 8
+;   beqz a3, 8
 ;   mv a1, a5
 ;   or a0, a4, a1
 ;   ret
@@ -141,9 +141,8 @@ block0(v0: i32, v1: i32):
 ;   sub a0, a3, a1
 ;   sll a2, a5, a1
 ;   srl a3, a5, a0
-;   bnez a1, 0xc
 ;   mv a5, zero
-;   j 8
+;   beqz a1, 8
 ;   mv a5, a3
 ;   or a0, a2, a5
 ;   ret
@@ -176,9 +175,8 @@ block0(v0: i16, v1: i16):
 ;   sub a0, a3, a1
 ;   sll a2, a5, a1
 ;   srl a3, a5, a0
-;   bnez a1, 0xc
 ;   mv a5, zero
-;   j 8
+;   beqz a1, 8
 ;   mv a5, a3
 ;   or a0, a2, a5
 ;   ret
@@ -209,9 +207,8 @@ block0(v0: i8, v1: i8):
 ;   sub a4, a1, a5
 ;   sll a0, a3, a5
 ;   srl a1, a3, a4
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a1
 ;   or a0, a0, a3
 ;   ret
@@ -243,9 +240,8 @@ block0(v0: i64):
 ;   sub a1, a5, a3
 ;   sll a4, a0, a3
 ;   srl a5, a0, a1
-;   bnez a3, 0xc
 ;   mv a1, zero
-;   j 8
+;   beqz a3, 8
 ;   mv a1, a5
 ;   or a0, a4, a1
 ;   ret
@@ -281,9 +277,8 @@ block0(v0: i32):
 ;   sub a0, a3, a1
 ;   sll a2, a5, a1
 ;   srl a3, a5, a0
-;   bnez a1, 0xc
 ;   mv a5, zero
-;   j 8
+;   beqz a1, 8
 ;   mv a5, a3
 ;   or a0, a2, a5
 ;   ret
@@ -319,9 +314,8 @@ block0(v0: i16):
 ;   sub a0, a3, a1
 ;   sll a2, a5, a1
 ;   srl a3, a5, a0
-;   bnez a1, 0xc
 ;   mv a5, zero
-;   j 8
+;   beqz a1, 8
 ;   mv a5, a3
 ;   or a0, a2, a5
 ;   ret
@@ -355,9 +349,8 @@ block0(v0: i8):
 ;   sub a4, a1, a5
 ;   sll a0, a3, a5
 ;   srl a1, a3, a4
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a1
 ;   or a0, a0, a3
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/rotr.clif b/cranelift/filetests/filetests/isa/riscv64/rotr.clif
index fe1e91863021..3528c4e07b29 100644
--- a/cranelift/filetests/filetests/isa/riscv64/rotr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/rotr.clif
@@ -13,9 +13,10 @@ block0(v0: i128, v1: i128):
 ;   sd ra,8(sp)
 ;   sd fp,0(sp)
 ;   mv fp,sp
-;   addi sp,sp,-16
-;   sd s7,8(sp)
-;   sd s9,0(sp)
+;   addi sp,sp,-32
+;   sd s1,24(sp)
+;   sd s7,16(sp)
+;   sd s9,8(sp)
 ; block0:
 ;   andi a5,a2,63
 ;   li a3,64
@@ -26,14 +27,15 @@ block0(v0: i128, v1: i128):
 ;   or a3,a3,s9
 ;   srl a1,a1,a5
 ;   sll a4,a0,a4
-;   select a5,zero,a4##condition=(a5 eq zero)
-;   or a5,a1,a5
+;   select a0,zero,a4##condition=(a5 eq zero)
+;   or s1,a1,a0
 ;   li a4,64
-;   andi a2,a2,127
-;   select [a0,a1],[a5,a3],[a3,a5]##condition=(a2 uge a4)
-;   ld s7,8(sp)
-;   ld s9,0(sp)
-;   addi sp,sp,16
+;   andi a5,a2,127
+;   select [a0,a1],[s1,a3],[a3,s1]##condition=(a5 uge a4)
+;   ld s1,24(sp)
+;   ld s7,16(sp)
+;   ld s9,8(sp)
+;   addi sp,sp,32
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   addi sp,sp,16
@@ -45,38 +47,37 @@ block0(v0: i128, v1: i128):
 ;   sd ra, 8(sp)
 ;   sd s0, 0(sp)
 ;   mv s0, sp
-;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
-;   sd s9, 0(sp)
-; block1: ; offset 0x1c
+;   addi sp, sp, -0x20
+;   sd s1, 0x18(sp)
+;   sd s7, 0x10(sp)
+;   sd s9, 8(sp)
+; block1: ; offset 0x20
 ;   andi a5, a2, 0x3f
 ;   addi a3, zero, 0x40
 ;   sub a4, a3, a5
 ;   srl a3, a0, a5
 ;   sll s7, a1, a4
-;   bnez a5, 0xc
 ;   mv s9, zero
-;   j 8
+;   beqz a5, 8
 ;   mv s9, s7
 ;   or a3, a3, s9
 ;   srl a1, a1, a5
 ;   sll a4, a0, a4
-;   bnez a5, 0xc
-;   mv a5, zero
-;   j 8
-;   mv a5, a4
-;   or a5, a1, a5
+;   mv a0, zero
+;   beqz a5, 8
+;   mv a0, a4
+;   or s1, a1, a0
 ;   addi a4, zero, 0x40
-;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
-;   mv a0, a5
+;   andi a5, a2, 0x7f
+;   mv a0, s1
 ;   mv a1, a3
-;   j 0xc
+;   bgeu a5, a4, 0xc
 ;   mv a0, a3
-;   mv a1, a5
-;   ld s7, 8(sp)
-;   ld s9, 0(sp)
-;   addi sp, sp, 0x10
+;   mv a1, s1
+;   ld s1, 0x18(sp)
+;   ld s7, 0x10(sp)
+;   ld s9, 8(sp)
+;   addi sp, sp, 0x20
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -106,9 +107,8 @@ block0(v0: i64, v1: i64):
 ;   sub a1, a5, a3
 ;   srl a4, a0, a3
 ;   sll a5, a0, a1
-;   bnez a3, 0xc
 ;   mv a1, zero
-;   j 8
+;   beqz a3, 8
 ;   mv a1, a5
 ;   or a0, a4, a1
 ;   ret
@@ -141,9 +141,8 @@ block0(v0: i32, v1: i32):
 ;   sub a0, a3, a1
 ;   srl a2, a5, a1
 ;   sll a3, a5, a0
-;   bnez a1, 0xc
 ;   mv a5, zero
-;   j 8
+;   beqz a1, 8
 ;   mv a5, a3
 ;   or a0, a2, a5
 ;   ret
@@ -176,9 +175,8 @@ block0(v0: i16, v1: i16):
 ;   sub a0, a3, a1
 ;   srl a2, a5, a1
 ;   sll a3, a5, a0
-;   bnez a1, 0xc
 ;   mv a5, zero
-;   j 8
+;   beqz a1, 8
 ;   mv a5, a3
 ;   or a0, a2, a5
 ;   ret
@@ -209,9 +207,8 @@ block0(v0: i8, v1: i8):
 ;   sub a4, a1, a5
 ;   srl a0, a3, a5
 ;   sll a1, a3, a4
-;   bnez a5, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a5, 8
 ;   mv a3, a1
 ;   or a0, a0, a3
 ;   ret
@@ -243,9 +240,8 @@ block0(v0: i64):
 ;   sub a1, a5, a3
 ;   srl a4, a0, a3
 ;   sll a5, a0, a1
-;   bnez a3, 0xc
 ;   mv a1, zero
-;   j 8
+;   beqz a3, 8
 ;   mv a1, a5
 ;   or a0, a4, a1
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/select.clif b/cranelift/filetests/filetests/isa/riscv64/select.clif
index 51d86299ab62..3b27d8eb704e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/select.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/select.clif
@@ -23,9 +23,8 @@ block0(v0: i8, v1: i8, v2: i8):
 ;   addi a3, zero, 0x2a
 ;   andi a5, a0, 0xff
 ;   andi a3, a3, 0xff
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -50,9 +49,8 @@ block0(v0: i8, v1: i16, v2: i16):
 ;   addi a3, zero, 0x2a
 ;   andi a5, a0, 0xff
 ;   andi a3, a3, 0xff
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -77,9 +75,8 @@ block0(v0: i8, v1: i32, v2: i32):
 ;   addi a3, zero, 0x2a
 ;   andi a5, a0, 0xff
 ;   andi a3, a3, 0xff
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -104,9 +101,8 @@ block0(v0: i8, v1: i64, v2: i64):
 ;   addi a3, zero, 0x2a
 ;   andi a5, a0, 0xff
 ;   andi a3, a3, 0xff
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -124,16 +120,17 @@ block0(v0: i8, v1: i128, v2: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s1,8(sp)
-;   sd s8,0(sp)
+;   sd s3,8(sp)
+;   sd s10,0(sp)
 ; block0:
-;   mv s8,a1
-;   li a5,42
-;   andi s1,a0,255
-;   andi a5,a5,255
-;   select [a0,a1],[s8,a2],[a3,a4]##condition=(s1 eq a5)
-;   ld s1,8(sp)
-;   ld s8,0(sp)
+;   mv s10,a1
+;   mv a1,a0
+;   li a0,42
+;   andi a5,a1,255
+;   andi s3,a0,255
+;   select [a0,a1],[s10,a2],[a3,a4]##condition=(a5 eq s3)
+;   ld s3,8(sp)
+;   ld s10,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -147,21 +144,21 @@ block0(v0: i8, v1: i128, v2: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s1, 8(sp)
-;   sd s8, 0(sp)
+;   sd s3, 8(sp)
+;   sd s10, 0(sp)
 ; block1: ; offset 0x1c
-;   mv s8, a1
-;   addi a5, zero, 0x2a
-;   andi s1, a0, 0xff
-;   andi a5, a5, 0xff
-;   bne s1, a5, 0x10
-;   mv a0, s8
+;   mv s10, a1
+;   mv a1, a0
+;   addi a0, zero, 0x2a
+;   andi a5, a1, 0xff
+;   andi s3, a0, 0xff
+;   mv a0, s10
 ;   mv a1, a2
-;   j 0xc
+;   beq a5, s3, 0xc
 ;   mv a0, a3
 ;   mv a1, a4
-;   ld s1, 8(sp)
-;   ld s8, 0(sp)
+;   ld s3, 8(sp)
+;   ld s10, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
@@ -178,24 +175,23 @@ block0(v0: i16, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a3,42
+;   li a4,42
 ;   slli a5,a0,48
-;   srai a4,a5,48
-;   slli a3,a3,48
-;   srai a5,a3,48
-;   select a0,a1,a2##condition=(a4 eq a5)
+;   srai a3,a5,48
+;   slli a4,a4,48
+;   srai a5,a4,48
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
+;   addi a4, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srai a4, a5, 0x30
-;   slli a3, a3, 0x30
-;   srai a5, a3, 0x30
-;   bne a4, a5, 0xc
+;   srai a3, a5, 0x30
+;   slli a4, a4, 0x30
+;   srai a5, a4, 0x30
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -209,24 +205,23 @@ block0(v0: i16, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a3,42
+;   li a4,42
 ;   slli a5,a0,48
-;   srai a4,a5,48
-;   slli a3,a3,48
-;   srai a5,a3,48
-;   select a0,a1,a2##condition=(a4 eq a5)
+;   srai a3,a5,48
+;   slli a4,a4,48
+;   srai a5,a4,48
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
+;   addi a4, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srai a4, a5, 0x30
-;   slli a3, a3, 0x30
-;   srai a5, a3, 0x30
-;   bne a4, a5, 0xc
+;   srai a3, a5, 0x30
+;   slli a4, a4, 0x30
+;   srai a5, a4, 0x30
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -240,24 +235,23 @@ block0(v0: i16, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a3,42
+;   li a4,42
 ;   slli a5,a0,48
-;   srai a4,a5,48
-;   slli a3,a3,48
-;   srai a5,a3,48
-;   select a0,a1,a2##condition=(a4 eq a5)
+;   srai a3,a5,48
+;   slli a4,a4,48
+;   srai a5,a4,48
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
+;   addi a4, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srai a4, a5, 0x30
-;   slli a3, a3, 0x30
-;   srai a5, a3, 0x30
-;   bne a4, a5, 0xc
+;   srai a3, a5, 0x30
+;   slli a4, a4, 0x30
+;   srai a5, a4, 0x30
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -271,24 +265,23 @@ block0(v0: i16, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a3,42
+;   li a4,42
 ;   slli a5,a0,48
-;   srai a4,a5,48
-;   slli a3,a3,48
-;   srai a5,a3,48
-;   select a0,a1,a2##condition=(a4 eq a5)
+;   srai a3,a5,48
+;   slli a4,a4,48
+;   srai a5,a4,48
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
+;   addi a4, zero, 0x2a
 ;   slli a5, a0, 0x30
-;   srai a4, a5, 0x30
-;   slli a3, a3, 0x30
-;   srai a5, a3, 0x30
-;   bne a4, a5, 0xc
+;   srai a3, a5, 0x30
+;   slli a4, a4, 0x30
+;   srai a5, a4, 0x30
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -340,10 +333,9 @@ block0(v0: i16, v1: i128, v2: i128):
 ;   srai a5, a1, 0x30
 ;   slli a0, s6, 0x30
 ;   srai s7, a0, 0x30
-;   bne a5, s7, 0x10
 ;   mv a0, t0
 ;   mv a1, a2
-;   j 0xc
+;   beq a5, s7, 0xc
 ;   mv a0, a3
 ;   mv a1, a4
 ;   ld s6, 8(sp)
@@ -375,9 +367,8 @@ block0(v0: i32, v1: i8, v2: i8):
 ;   addi a3, zero, 0x2a
 ;   sext.w a5, a0
 ;   sext.w a3, a3
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -402,9 +393,8 @@ block0(v0: i32, v1: i16, v2: i16):
 ;   addi a3, zero, 0x2a
 ;   sext.w a5, a0
 ;   sext.w a3, a3
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -429,9 +419,8 @@ block0(v0: i32, v1: i32, v2: i32):
 ;   addi a3, zero, 0x2a
 ;   sext.w a5, a0
 ;   sext.w a3, a3
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -456,9 +445,8 @@ block0(v0: i32, v1: i64, v2: i64):
 ;   addi a3, zero, 0x2a
 ;   sext.w a5, a0
 ;   sext.w a3, a3
-;   bne a5, a3, 0xc
 ;   mv a0, a1
-;   j 8
+;   beq a5, a3, 8
 ;   mv a0, a2
 ;   ret
 
@@ -476,16 +464,17 @@ block0(v0: i32, v1: i128, v2: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s1,8(sp)
-;   sd s8,0(sp)
+;   sd s3,8(sp)
+;   sd s10,0(sp)
 ; block0:
-;   mv s8,a1
-;   li a5,42
-;   sext.w s1,a0
-;   sext.w a5,a5
-;   select [a0,a1],[s8,a2],[a3,a4]##condition=(s1 eq a5)
-;   ld s1,8(sp)
-;   ld s8,0(sp)
+;   mv s10,a1
+;   mv a1,a0
+;   li a0,42
+;   sext.w a5,a1
+;   sext.w s3,a0
+;   select [a0,a1],[s10,a2],[a3,a4]##condition=(a5 eq s3)
+;   ld s3,8(sp)
+;   ld s10,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -499,21 +488,21 @@ block0(v0: i32, v1: i128, v2: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s1, 8(sp)
-;   sd s8, 0(sp)
+;   sd s3, 8(sp)
+;   sd s10, 0(sp)
 ; block1: ; offset 0x1c
-;   mv s8, a1
-;   addi a5, zero, 0x2a
-;   sext.w s1, a0
-;   sext.w a5, a5
-;   bne s1, a5, 0x10
-;   mv a0, s8
+;   mv s10, a1
+;   mv a1, a0
+;   addi a0, zero, 0x2a
+;   sext.w a5, a1
+;   sext.w s3, a0
+;   mv a0, s10
 ;   mv a1, a2
-;   j 0xc
+;   beq a5, s3, 0xc
 ;   mv a0, a3
 ;   mv a1, a4
-;   ld s1, 8(sp)
-;   ld s8, 0(sp)
+;   ld s3, 8(sp)
+;   ld s10, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
@@ -531,15 +520,16 @@ block0(v0: i64, v1: i8, v2: i8):
 ; VCode:
 ; block0:
 ;   li a5,42
-;   select a0,a1,a2##condition=(a0 eq a5)
+;   mv a3,a0
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a5, zero, 0x2a
-;   bne a0, a5, 0xc
+;   mv a3, a0
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -554,15 +544,16 @@ block0(v0: i64, v1: i16, v2: i16):
 ; VCode:
 ; block0:
 ;   li a5,42
-;   select a0,a1,a2##condition=(a0 eq a5)
+;   mv a3,a0
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a5, zero, 0x2a
-;   bne a0, a5, 0xc
+;   mv a3, a0
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -577,15 +568,16 @@ block0(v0: i64, v1: i32, v2: i32):
 ; VCode:
 ; block0:
 ;   li a5,42
-;   select a0,a1,a2##condition=(a0 eq a5)
+;   mv a3,a0
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a5, zero, 0x2a
-;   bne a0, a5, 0xc
+;   mv a3, a0
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -600,15 +592,16 @@ block0(v0: i64, v1: i64, v2: i64):
 ; VCode:
 ; block0:
 ;   li a5,42
-;   select a0,a1,a2##condition=(a0 eq a5)
+;   mv a3,a0
+;   select a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a5, zero, 0x2a
-;   bne a0, a5, 0xc
+;   mv a3, a0
 ;   mv a0, a1
-;   j 8
+;   beq a3, a5, 8
 ;   mv a0, a2
 ;   ret
 
@@ -629,10 +622,11 @@ block0(v0: i64, v1: i128, v2: i128):
 ;   sd s4,8(sp)
 ;   sd s6,0(sp)
 ; block0:
-;   mv s4,a1
-;   mv s6,a0
-;   li a5,42
-;   select [a0,a1],[s4,a2],[a3,a4]##condition=(s6 eq a5)
+;   mv s4,a2
+;   mv s6,a1
+;   li a2,42
+;   mv a5,a0
+;   select [a0,a1],[s6,s4],[a3,a4]##condition=(a5 eq a2)
 ;   ld s4,8(sp)
 ;   ld s6,0(sp)
 ;   addi sp,sp,16
@@ -651,13 +645,13 @@ block0(v0: i64, v1: i128, v2: i128):
 ;   sd s4, 8(sp)
 ;   sd s6, 0(sp)
 ; block1: ; offset 0x1c
-;   mv s4, a1
-;   mv s6, a0
-;   addi a5, zero, 0x2a
-;   bne s6, a5, 0x10
-;   mv a0, s4
-;   mv a1, a2
-;   j 0xc
+;   mv s4, a2
+;   mv s6, a1
+;   addi a2, zero, 0x2a
+;   mv a5, a0
+;   mv a0, s6
+;   mv a1, s4
+;   beq a5, a2, 0xc
 ;   mv a0, a3
 ;   mv a1, a4
 ;   ld s4, 8(sp)
@@ -696,9 +690,8 @@ block0(v0: i128, v1: i8, v2: i8):
 ;   xor a4, a1, a4
 ;   or a0, a5, a4
 ;   seqz a4, a0
-;   beqz a4, 0xc
 ;   mv a0, a2
-;   j 8
+;   bnez a4, 8
 ;   mv a0, a3
 ;   ret
 
@@ -730,9 +723,8 @@ block0(v0: i128, v1: i16, v2: i16):
 ;   xor a4, a1, a4
 ;   or a0, a5, a4
 ;   seqz a4, a0
-;   beqz a4, 0xc
 ;   mv a0, a2
-;   j 8
+;   bnez a4, 8
 ;   mv a0, a3
 ;   ret
 
@@ -764,9 +756,8 @@ block0(v0: i128, v1: i32, v2: i32):
 ;   xor a4, a1, a4
 ;   or a0, a5, a4
 ;   seqz a4, a0
-;   beqz a4, 0xc
 ;   mv a0, a2
-;   j 8
+;   bnez a4, 8
 ;   mv a0, a3
 ;   ret
 
@@ -798,9 +789,8 @@ block0(v0: i128, v1: i64, v2: i64):
 ;   xor a4, a1, a4
 ;   or a0, a5, a4
 ;   seqz a4, a0
-;   beqz a4, 0xc
 ;   mv a0, a2
-;   j 8
+;   bnez a4, 8
 ;   mv a0, a3
 ;   ret
 
@@ -819,21 +809,20 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-32
-;   sd s7,24(sp)
-;   sd s8,16(sp)
-;   sd s9,8(sp)
+;   sd s8,24(sp)
+;   sd s9,16(sp)
+;   sd s11,8(sp)
 ; block0:
 ;   li s8,42
 ;   li s9,0
 ;   xor a0,a0,s8
 ;   xor a1,a1,s9
 ;   or a0,a0,a1
-;   seqz a0,a0
-;   select [s7,a1],[a2,a3],[a4,a5]##condition=(a0 ne zero)
-;   mv a0,s7
-;   ld s7,24(sp)
-;   ld s8,16(sp)
-;   ld s9,8(sp)
+;   seqz s11,a0
+;   select [a0,a1],[a2,a3],[a4,a5]##condition=(s11 ne zero)
+;   ld s8,24(sp)
+;   ld s9,16(sp)
+;   ld s11,8(sp)
 ;   addi sp,sp,32
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -847,26 +836,24 @@ block0(v0: i128, v1: i128, v2: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x20
-;   sd s7, 0x18(sp)
-;   sd s8, 0x10(sp)
-;   sd s9, 8(sp)
+;   sd s8, 0x18(sp)
+;   sd s9, 0x10(sp)
+;   sd s11, 8(sp)
 ; block1: ; offset 0x20
 ;   addi s8, zero, 0x2a
 ;   mv s9, zero
 ;   xor a0, a0, s8
 ;   xor a1, a1, s9
 ;   or a0, a0, a1
-;   seqz a0, a0
-;   beqz a0, 0x10
-;   mv s7, a2
+;   seqz s11, a0
+;   mv a0, a2
 ;   mv a1, a3
-;   j 0xc
-;   mv s7, a4
+;   bnez s11, 0xc
+;   mv a0, a4
 ;   mv a1, a5
-;   mv a0, s7
-;   ld s7, 0x18(sp)
-;   ld s8, 0x10(sp)
-;   ld s9, 8(sp)
+;   ld s8, 0x18(sp)
+;   ld s9, 0x10(sp)
+;   ld s11, 8(sp)
 ;   addi sp, sp, 0x20
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-select.clif b/cranelift/filetests/filetests/isa/riscv64/simd-select.clif
index 370ac0902576..acbf77ed55d7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-select.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-select.clif
@@ -35,9 +35,8 @@ block0(v0: i64, v1: i64x2, v2: i64x2):
 ;   .byte 0x07, 0x85, 0x0f, 0x02
 ;   addi t6, sp, 0x20
 ;   .byte 0x07, 0x86, 0x0f, 0x02
-;   beqz a0, 0xc
 ;   .byte 0xd7, 0x37, 0xa0, 0x9e
-;   j 8
+;   bnez a0, 8
 ;   .byte 0xd7, 0x37, 0xc0, 0x9e
 ;   .byte 0xa7, 0x87, 0x05, 0x02
 ;   ld ra, 8(sp)
@@ -80,9 +79,8 @@ block0(v0: i32, v1: i32x4, v2: i32x4):
 ;   addi t6, sp, 0x20
 ;   .byte 0x07, 0x86, 0x0f, 0x02
 ;   sext.w a2, a0
-;   beqz a2, 0xc
 ;   .byte 0xd7, 0x34, 0xa0, 0x9e
-;   j 8
+;   bnez a2, 8
 ;   .byte 0xd7, 0x34, 0xc0, 0x9e
 ;   .byte 0xa7, 0x84, 0x05, 0x02
 ;   ld ra, 8(sp)
@@ -127,9 +125,8 @@ block0(v0: i16, v1: i16x8, v2: i16x8):
 ;   .byte 0x07, 0x86, 0x0f, 0x02
 ;   slli a2, a0, 0x30
 ;   srai a3, a2, 0x30
-;   beqz a3, 0xc
 ;   .byte 0xd7, 0x35, 0xa0, 0x9e
-;   j 8
+;   bnez a3, 8
 ;   .byte 0xd7, 0x35, 0xc0, 0x9e
 ;   .byte 0xa7, 0x85, 0x05, 0x02
 ;   ld ra, 8(sp)
@@ -172,9 +169,8 @@ block0(v0: i8, v1: i8x16, v2: i8x16):
 ;   addi t6, sp, 0x20
 ;   .byte 0x07, 0x86, 0x0f, 0x02
 ;   andi a2, a0, 0xff
-;   beqz a2, 0xc
 ;   .byte 0xd7, 0x34, 0xa0, 0x9e
-;   j 8
+;   bnez a2, 8
 ;   .byte 0xd7, 0x34, 0xc0, 0x9e
 ;   .byte 0xa7, 0x84, 0x05, 0x02
 ;   ld ra, 8(sp)
@@ -215,9 +211,8 @@ block0(v0: i64, v1: f64x2, v2: f64x2):
 ;   .byte 0x07, 0x85, 0x0f, 0x02
 ;   addi t6, sp, 0x20
 ;   .byte 0x07, 0x86, 0x0f, 0x02
-;   beqz a0, 0xc
 ;   .byte 0xd7, 0x37, 0xa0, 0x9e
-;   j 8
+;   bnez a0, 8
 ;   .byte 0xd7, 0x37, 0xc0, 0x9e
 ;   .byte 0xa7, 0x87, 0x05, 0x02
 ;   ld ra, 8(sp)
@@ -258,9 +253,8 @@ block0(v0: i64, v1: f32x4, v2: f32x4):
 ;   .byte 0x07, 0x85, 0x0f, 0x02
 ;   addi t6, sp, 0x20
 ;   .byte 0x07, 0x86, 0x0f, 0x02
-;   beqz a0, 0xc
 ;   .byte 0xd7, 0x37, 0xa0, 0x9e
-;   j 8
+;   bnez a0, 8
 ;   .byte 0xd7, 0x37, 0xc0, 0x9e
 ;   .byte 0xa7, 0x87, 0x05, 0x02
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif
index 30c5819e302b..c14a89689e97 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smax-zbb.clif
@@ -90,18 +90,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   slt a5,a3,a1
-;   sltu a4,a2,a0
-;   mv s7,a0
-;   xor a0,a3,a1
+;   sltu s1,a2,a0
+;   xor a4,a3,a1
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -116,24 +115,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   slt a5, a3, a1
-;   sltu a4, a2, a0
-;   mv s7, a0
-;   xor a0, a3, a1
+;   sltu s1, a2, a0
+;   xor a4, a3, a1
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/smax.clif b/cranelift/filetests/filetests/isa/riscv64/smax.clif
index 10377029ae03..72fe68009665 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smax.clif
@@ -23,9 +23,8 @@ block0(v0: i8, v1: i8):
 ;   srai a5, a3, 0x38
 ;   slli a1, a1, 0x38
 ;   srai a3, a1, 0x38
-;   bge a3, a5, 0xc
 ;   mv a0, a5
-;   j 8
+;   blt a3, a5, 8
 ;   mv a0, a3
 ;   ret
 
@@ -50,9 +49,8 @@ block0(v0: i16, v1: i16):
 ;   srai a5, a3, 0x30
 ;   slli a1, a1, 0x30
 ;   srai a3, a1, 0x30
-;   bge a3, a5, 0xc
 ;   mv a0, a5
-;   j 8
+;   blt a3, a5, 8
 ;   mv a0, a3
 ;   ret
 
@@ -73,9 +71,8 @@ block0(v0: i32, v1: i32):
 ; block0: ; offset 0x0
 ;   sext.w a3, a0
 ;   sext.w a5, a1
-;   bge a5, a3, 0xc
 ;   mv a0, a3
-;   j 8
+;   blt a5, a3, 8
 ;   mv a0, a5
 ;   ret
 
@@ -87,12 +84,15 @@ block0(v0: i64, v1: i64):
 
 ; VCode:
 ; block0:
-;   select a0,a0,a1##condition=(a0 sgt a1)
+;   mv a4,a0
+;   select a0,a4,a1##condition=(a4 sgt a1)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a0, 8
+;   mv a4, a0
+;   mv a0, a4
+;   blt a1, a4, 8
 ;   mv a0, a1
 ;   ret
 
@@ -108,18 +108,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   slt a5,a3,a1
-;   sltu a4,a2,a0
-;   mv s7,a0
-;   xor a0,a3,a1
+;   sltu s1,a2,a0
+;   xor a4,a3,a1
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -134,24 +133,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   slt a5, a3, a1
-;   sltu a4, a2, a0
-;   mv s7, a0
-;   xor a0, a3, a1
+;   sltu s1, a2, a0
+;   xor a4, a3, a1
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif
index 9b46e12d957e..5af7c25ff86f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smin-zbb.clif
@@ -90,18 +90,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   slt a5,a1,a3
-;   sltu a4,a0,a2
-;   mv s7,a0
-;   xor a0,a1,a3
+;   sltu s1,a0,a2
+;   xor a4,a1,a3
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -116,24 +115,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   slt a5, a1, a3
-;   sltu a4, a0, a2
-;   mv s7, a0
-;   xor a0, a1, a3
+;   sltu s1, a0, a2
+;   xor a4, a1, a3
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/smin.clif b/cranelift/filetests/filetests/isa/riscv64/smin.clif
index 3503329ebab1..8528fdc3a090 100644
--- a/cranelift/filetests/filetests/isa/riscv64/smin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/smin.clif
@@ -23,9 +23,8 @@ block0(v0: i8, v1: i8):
 ;   srai a5, a3, 0x38
 ;   slli a1, a1, 0x38
 ;   srai a3, a1, 0x38
-;   bge a5, a3, 0xc
 ;   mv a0, a5
-;   j 8
+;   blt a5, a3, 8
 ;   mv a0, a3
 ;   ret
 
@@ -50,9 +49,8 @@ block0(v0: i16, v1: i16):
 ;   srai a5, a3, 0x30
 ;   slli a1, a1, 0x30
 ;   srai a3, a1, 0x30
-;   bge a5, a3, 0xc
 ;   mv a0, a5
-;   j 8
+;   blt a5, a3, 8
 ;   mv a0, a3
 ;   ret
 
@@ -73,9 +71,8 @@ block0(v0: i32, v1: i32):
 ; block0: ; offset 0x0
 ;   sext.w a3, a0
 ;   sext.w a5, a1
-;   bge a3, a5, 0xc
 ;   mv a0, a3
-;   j 8
+;   blt a3, a5, 8
 ;   mv a0, a5
 ;   ret
 
@@ -87,12 +84,15 @@ block0(v0: i64, v1: i64):
 
 ; VCode:
 ; block0:
-;   select a0,a0,a1##condition=(a0 slt a1)
+;   mv a4,a0
+;   select a0,a4,a1##condition=(a4 slt a1)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a0, a1, 8
+;   mv a4, a0
+;   mv a0, a4
+;   blt a4, a1, 8
 ;   mv a0, a1
 ;   ret
 
@@ -108,18 +108,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   slt a5,a1,a3
-;   sltu a4,a0,a2
-;   mv s7,a0
-;   xor a0,a1,a3
+;   sltu s1,a0,a2
+;   xor a4,a1,a3
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -134,24 +133,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   slt a5, a1, a3
-;   sltu a4, a0, a2
-;   mv s7, a0
-;   xor a0, a1, a3
+;   sltu s1, a0, a2
+;   xor a4, a1, a3
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/sshr-const.clif b/cranelift/filetests/filetests/isa/riscv64/sshr-const.clif
index 2454c2269e92..dbb3ed234850 100644
--- a/cranelift/filetests/filetests/isa/riscv64/sshr-const.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/sshr-const.clif
@@ -420,25 +420,22 @@ block0(v0: i128):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -476,25 +473,22 @@ block0(v0: i128):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -532,25 +526,22 @@ block0(v0: i128):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -588,25 +579,22 @@ block0(v0: i128):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -676,10 +664,9 @@ block0(v0: i128):
 ;   mv a5, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, a5
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, s11
 ;   mv a1, a3
 ;   ld s11, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/sshr.clif b/cranelift/filetests/filetests/isa/riscv64/sshr.clif
index 3e3adc5aa132..2901c74d805d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/sshr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/sshr.clif
@@ -413,25 +413,22 @@ block0(v0: i128, v1: i8):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -466,25 +463,22 @@ block0(v0: i128, v1: i16):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -519,25 +513,22 @@ block0(v0: i128, v1: i32):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -572,25 +563,22 @@ block0(v0: i128, v1: i64):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi a0, zero, 0x40
 ;   sra a3, a1, a4
 ;   addi a4, zero, -1
-;   bgez a1, 0xc
 ;   mv t4, a4
-;   j 8
+;   bltz a1, 8
 ;   mv t4, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, t4
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -654,10 +642,9 @@ block0(v0: i128, v1: i128):
 ;   mv a5, zero
 ;   addi a4, zero, 0x40
 ;   andi a2, a2, 0x7f
-;   bltu a2, a4, 0x10
 ;   mv a0, a3
 ;   mv a1, a5
-;   j 0xc
+;   bgeu a2, a4, 0xc
 ;   mv a0, s11
 ;   mv a1, a3
 ;   ld s11, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/trunc.clif b/cranelift/filetests/filetests/isa/riscv64/trunc.clif
index 05fe998e65ee..e554ccf18381 100644
--- a/cranelift/filetests/filetests/isa/riscv64/trunc.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/trunc.clif
@@ -70,9 +70,8 @@ block0(v0: f64):
 ;   fsgnj.d fa4, fa2, fa0
 ;   fmv.d.x fa1, zero
 ;   fadd.d fa2, fa0, fa1, rne
-;   bnez a4, 0xc
 ;   fmv.d fa0, fa2
-;   j 8
+;   beqz a4, 8
 ;   fmv.d fa0, fa4
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif
index 3e613e4bd186..583b7f14efef 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umax-zbb.clif
@@ -94,18 +94,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   sltu a5,a3,a1
-;   sltu a4,a2,a0
-;   mv s7,a0
-;   xor a0,a3,a1
+;   sltu s1,a2,a0
+;   xor a4,a3,a1
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -120,24 +119,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   sltu a5, a3, a1
-;   sltu a4, a2, a0
-;   mv s7, a0
-;   xor a0, a3, a1
+;   sltu s1, a2, a0
+;   xor a4, a3, a1
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/umax.clif b/cranelift/filetests/filetests/isa/riscv64/umax.clif
index 45a254c12650..4895758b78ef 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umax.clif
@@ -19,9 +19,8 @@ block0(v0: i8, v1: i8):
 ; block0: ; offset 0x0
 ;   andi a3, a0, 0xff
 ;   andi a5, a1, 0xff
-;   bgeu a5, a3, 0xc
 ;   mv a0, a3
-;   j 8
+;   bltu a5, a3, 8
 ;   mv a0, a5
 ;   ret
 
@@ -46,9 +45,8 @@ block0(v0: i16, v1: i16):
 ;   srli a5, a3, 0x30
 ;   slli a1, a1, 0x30
 ;   srli a3, a1, 0x30
-;   bgeu a3, a5, 0xc
 ;   mv a0, a5
-;   j 8
+;   bltu a3, a5, 8
 ;   mv a0, a3
 ;   ret
 
@@ -73,9 +71,8 @@ block0(v0: i32, v1: i32):
 ;   srli a5, a3, 0x20
 ;   slli a1, a1, 0x20
 ;   srli a3, a1, 0x20
-;   bgeu a3, a5, 0xc
 ;   mv a0, a5
-;   j 8
+;   bltu a3, a5, 8
 ;   mv a0, a3
 ;   ret
 
@@ -87,12 +84,15 @@ block0(v0: i64, v1: i64):
 
 ; VCode:
 ; block0:
-;   select a0,a0,a1##condition=(a0 ugt a1)
+;   mv a4,a0
+;   select a0,a4,a1##condition=(a4 ugt a1)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a0, 8
+;   mv a4, a0
+;   mv a0, a4
+;   bltu a1, a4, 8
 ;   mv a0, a1
 ;   ret
 
@@ -108,18 +108,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   sltu a5,a3,a1
-;   sltu a4,a2,a0
-;   mv s7,a0
-;   xor a0,a3,a1
+;   sltu s1,a2,a0
+;   xor a4,a3,a1
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -134,24 +133,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   sltu a5, a3, a1
-;   sltu a4, a2, a0
-;   mv s7, a0
-;   xor a0, a3, a1
+;   sltu s1, a2, a0
+;   xor a4, a3, a1
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif b/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif
index e58dcd77277a..1aa46c528611 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umin-zbb.clif
@@ -94,18 +94,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   sltu a5,a1,a3
-;   sltu a4,a0,a2
-;   mv s7,a0
-;   xor a0,a1,a3
+;   sltu s1,a0,a2
+;   xor a4,a1,a3
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -120,24 +119,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   sltu a5, a1, a3
-;   sltu a4, a0, a2
-;   mv s7, a0
-;   xor a0, a1, a3
+;   sltu s1, a0, a2
+;   xor a4, a1, a3
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/umin.clif b/cranelift/filetests/filetests/isa/riscv64/umin.clif
index a4cc67386f1d..fb99352d36bb 100644
--- a/cranelift/filetests/filetests/isa/riscv64/umin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/umin.clif
@@ -19,9 +19,8 @@ block0(v0: i8, v1: i8):
 ; block0: ; offset 0x0
 ;   andi a3, a0, 0xff
 ;   andi a5, a1, 0xff
-;   bgeu a3, a5, 0xc
 ;   mv a0, a3
-;   j 8
+;   bltu a3, a5, 8
 ;   mv a0, a5
 ;   ret
 
@@ -46,9 +45,8 @@ block0(v0: i16, v1: i16):
 ;   srli a5, a3, 0x30
 ;   slli a1, a1, 0x30
 ;   srli a3, a1, 0x30
-;   bgeu a5, a3, 0xc
 ;   mv a0, a5
-;   j 8
+;   bltu a5, a3, 8
 ;   mv a0, a3
 ;   ret
 
@@ -73,9 +71,8 @@ block0(v0: i32, v1: i32):
 ;   srli a5, a3, 0x20
 ;   slli a1, a1, 0x20
 ;   srli a3, a1, 0x20
-;   bgeu a5, a3, 0xc
 ;   mv a0, a5
-;   j 8
+;   bltu a5, a3, 8
 ;   mv a0, a3
 ;   ret
 
@@ -87,12 +84,15 @@ block0(v0: i64, v1: i64):
 
 ; VCode:
 ; block0:
-;   select a0,a0,a1##condition=(a0 ult a1)
+;   mv a4,a0
+;   select a0,a4,a1##condition=(a4 ult a1)
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a0, a1, 8
+;   mv a4, a0
+;   mv a0, a4
+;   bltu a4, a1, 8
 ;   mv a0, a1
 ;   ret
 
@@ -108,18 +108,17 @@ block0(v0: i128, v1: i128):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ;   addi sp,sp,-16
-;   sd s7,8(sp)
+;   sd s1,8(sp)
 ;   sd s9,0(sp)
 ; block0:
 ;   sltu a5,a1,a3
-;   sltu a4,a0,a2
-;   mv s7,a0
-;   xor a0,a1,a3
+;   sltu s1,a0,a2
+;   xor a4,a1,a3
 ;   mv s9,a1
-;   select a5,a4,a5##condition=(a0 eq zero)
-;   mv a4,s7
+;   select a5,s1,a5##condition=(a4 eq zero)
+;   mv a4,a0
 ;   select [a0,a1],[a4,s9],[a2,a3]##condition=(a5 ne zero)
-;   ld s7,8(sp)
+;   ld s1,8(sp)
 ;   ld s9,0(sp)
 ;   addi sp,sp,16
 ;   ld ra,8(sp)
@@ -134,24 +133,22 @@ block0(v0: i128, v1: i128):
 ;   sd s0, 0(sp)
 ;   mv s0, sp
 ;   addi sp, sp, -0x10
-;   sd s7, 8(sp)
+;   sd s1, 8(sp)
 ;   sd s9, 0(sp)
 ; block1: ; offset 0x1c
 ;   sltu a5, a1, a3
-;   sltu a4, a0, a2
-;   mv s7, a0
-;   xor a0, a1, a3
+;   sltu s1, a0, a2
+;   xor a4, a1, a3
 ;   mv s9, a1
-;   bnez a0, 8
-;   mv a5, a4
-;   mv a4, s7
-;   beqz a5, 0x10
+;   bnez a4, 8
+;   mv a5, s1
+;   mv a4, a0
 ;   mv a0, a4
 ;   mv a1, s9
-;   j 0xc
+;   bnez a5, 0xc
 ;   mv a0, a2
 ;   mv a1, a3
-;   ld s7, 8(sp)
+;   ld s1, 8(sp)
 ;   ld s9, 0(sp)
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/ushr-const.clif b/cranelift/filetests/filetests/isa/riscv64/ushr-const.clif
index 2aac469d8d7b..309df79c26fb 100644
--- a/cranelift/filetests/filetests/isa/riscv64/ushr-const.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/ushr-const.clif
@@ -407,19 +407,17 @@ block0(v0: i128):
 ;   addi a2, zero, 0x40
 ;   sub a2, a2, a4
 ;   sll a5, a1, a2
-;   bnez a4, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a2, a5
 ;   srl a5, a0, a4
 ;   or a5, a2, a5
 ;   addi t0, zero, 0x40
 ;   srl a2, a1, a4
 ;   andi a4, a3, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a2
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a2
 ;   ret
@@ -454,19 +452,17 @@ block0(v0: i128):
 ;   addi a2, zero, 0x40
 ;   sub a2, a2, a4
 ;   sll a5, a1, a2
-;   bnez a4, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a2, a5
 ;   srl a5, a0, a4
 ;   or a5, a2, a5
 ;   addi t0, zero, 0x40
 ;   srl a2, a1, a4
 ;   andi a4, a3, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a2
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a2
 ;   ret
@@ -501,19 +497,17 @@ block0(v0: i128):
 ;   addi a2, zero, 0x40
 ;   sub a2, a2, a4
 ;   sll a5, a1, a2
-;   bnez a4, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a2, a5
 ;   srl a5, a0, a4
 ;   or a5, a2, a5
 ;   addi t0, zero, 0x40
 ;   srl a2, a1, a4
 ;   andi a4, a3, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a2
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a2
 ;   ret
@@ -548,19 +542,17 @@ block0(v0: i128):
 ;   addi a2, zero, 0x40
 ;   sub a2, a2, a4
 ;   sll a5, a1, a2
-;   bnez a4, 0xc
 ;   mv a2, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a2, a5
 ;   srl a5, a0, a4
 ;   or a5, a2, a5
 ;   addi t0, zero, 0x40
 ;   srl a2, a1, a4
 ;   andi a4, a3, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a2
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a2
 ;   ret
@@ -623,10 +615,9 @@ block0(v0: i128):
 ;   addi a2, zero, 0x40
 ;   srl a3, a1, a5
 ;   andi a5, a4, 0x7f
-;   bltu a5, a2, 0x10
 ;   mv a0, a3
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a5, a2, 0xc
 ;   mv a0, s11
 ;   mv a1, a3
 ;   ld s11, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/ushr.clif b/cranelift/filetests/filetests/isa/riscv64/ushr.clif
index 8e991c4625e4..2332389c33ef 100644
--- a/cranelift/filetests/filetests/isa/riscv64/ushr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/ushr.clif
@@ -400,19 +400,17 @@ block0(v0: i128, v1: i8):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi t0, zero, 0x40
 ;   srl a3, a1, a4
 ;   andi a4, a2, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a3
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -444,19 +442,17 @@ block0(v0: i128, v1: i16):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi t0, zero, 0x40
 ;   srl a3, a1, a4
 ;   andi a4, a2, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a3
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -488,19 +484,17 @@ block0(v0: i128, v1: i32):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi t0, zero, 0x40
 ;   srl a3, a1, a4
 ;   andi a4, a2, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a3
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -532,19 +526,17 @@ block0(v0: i128, v1: i64):
 ;   addi a3, zero, 0x40
 ;   sub a3, a3, a4
 ;   sll a5, a1, a3
-;   bnez a4, 0xc
 ;   mv a3, zero
-;   j 8
+;   beqz a4, 8
 ;   mv a3, a5
 ;   srl a5, a0, a4
 ;   or a5, a3, a5
 ;   addi t0, zero, 0x40
 ;   srl a3, a1, a4
 ;   andi a4, a2, 0x7f
-;   bltu a4, t0, 0x10
 ;   mv a0, a3
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a4, t0, 0xc
 ;   mv a0, a5
 ;   mv a1, a3
 ;   ret
@@ -601,10 +593,9 @@ block0(v0: i128, v1: i128):
 ;   addi a3, zero, 0x40
 ;   srl a4, a1, a5
 ;   andi a5, a2, 0x7f
-;   bltu a5, a3, 0x10
 ;   mv a0, a4
 ;   mv a1, zero
-;   j 0xc
+;   bgeu a5, a3, 0xc
 ;   mv a0, s11
 ;   mv a1, a4
 ;   ld s11, 8(sp)
diff --git a/cranelift/filetests/filetests/isa/riscv64/zca.clif b/cranelift/filetests/filetests/isa/riscv64/zca.clif
index 334cd4247e00..4086bb6353cb 100644
--- a/cranelift/filetests/filetests/isa/riscv64/zca.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/zca.clif
@@ -163,9 +163,8 @@ block0(v0: i8, v1: i8, v2: i8):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   andi a4, a0, 0xff
-;   beqz a4, 8
 ;   c.mv a0, a1
-;   c.j 4
+;   bnez a4, 6
 ;   c.mv a0, a2
 ;   c.jr ra