From 31834c7ee35cad32701543b2113fe06d56255030 Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Sat, 3 Sep 2022 10:33:26 +0100 Subject: [PATCH 1/4] cranelift: Re-enable some shift operations --- cranelift/fuzzgen/src/function_generator.rs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs index 4175a2ac5073..17718fa48580 100644 --- a/cranelift/fuzzgen/src/function_generator.rs +++ b/cranelift/fuzzgen/src/function_generator.rs @@ -298,17 +298,16 @@ const OPCODE_SIGNATURES: &'static [( (Opcode::Rotl, &[I128, I64], &[I128], insert_opcode), (Opcode::Rotl, &[I128, I128], &[I128], insert_opcode), // Ishl - // Some test cases disabled due to: https://github.com/bytecodealliance/wasmtime/issues/4699 (Opcode::Ishl, &[I8, I8], &[I8], insert_opcode), (Opcode::Ishl, &[I8, I16], &[I8], insert_opcode), (Opcode::Ishl, &[I8, I32], &[I8], insert_opcode), (Opcode::Ishl, &[I8, I64], &[I8], insert_opcode), - // (Opcode::Ishl, &[I8, I128], &[I8], insert_opcode), + (Opcode::Ishl, &[I8, I128], &[I8], insert_opcode), (Opcode::Ishl, &[I16, I8], &[I16], insert_opcode), (Opcode::Ishl, &[I16, I16], &[I16], insert_opcode), (Opcode::Ishl, &[I16, I32], &[I16], insert_opcode), (Opcode::Ishl, &[I16, I64], &[I16], insert_opcode), - // (Opcode::Ishl, &[I16, I128], &[I16], insert_opcode), + (Opcode::Ishl, &[I16, I128], &[I16], insert_opcode), (Opcode::Ishl, &[I32, I8], &[I32], insert_opcode), (Opcode::Ishl, &[I32, I16], &[I32], insert_opcode), (Opcode::Ishl, &[I32, I32], &[I32], insert_opcode), From 4cfab0f89958d476b044a5f225825f5bc750f270 Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Sat, 3 Sep 2022 10:37:19 +0100 Subject: [PATCH 2/4] fuzzgen: Disable Some FloatCC's for AArch64 --- cranelift/fuzzgen/src/function_generator.rs | 35 +++++++++++++++------ 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs index 17718fa48580..a57b72ee0139 100644 --- a/cranelift/fuzzgen/src/function_generator.rs +++ b/cranelift/fuzzgen/src/function_generator.rs @@ -135,7 +135,24 @@ fn insert_cmp( let rhs = builder.use_var(rhs); let res = if opcode == Opcode::Fcmp { - let cc = *fgen.u.choose(FloatCC::all())?; + // Some FloatCC's are not implemented on AArch64, see: + // https://github.com/bytecodealliance/wasmtime/issues/4850 + let float_cc = if cfg!(target_arch = "aarch64") { + &[ + FloatCC::Ordered, + FloatCC::Unordered, + FloatCC::Equal, + FloatCC::NotEqual, + FloatCC::LessThan, + FloatCC::LessThanOrEqual, + FloatCC::GreaterThan, + FloatCC::GreaterThanOrEqual, + ] + } else { + FloatCC::all() + }; + + let cc = *fgen.u.choose(float_cc)?; builder.ins().fcmp(cc, lhs, rhs) } else { let cc = *fgen.u.choose(IntCC::all())?; @@ -232,19 +249,21 @@ const OPCODE_SIGNATURES: &'static [( (Opcode::Imul, &[I64, I64], &[I64], insert_opcode), (Opcode::Imul, &[I128, I128], &[I128], insert_opcode), // Udiv - // udiv.i128 not implemented on x64: https://github.com/bytecodealliance/wasmtime/issues/4756 (Opcode::Udiv, &[I8, I8], &[I8], insert_opcode), (Opcode::Udiv, &[I16, I16], &[I16], insert_opcode), (Opcode::Udiv, &[I32, I32], &[I32], insert_opcode), (Opcode::Udiv, &[I64, I64], &[I64], insert_opcode), - // (Opcode::Udiv, &[I128, I128], &[I128], insert_opcode), + // udiv.i128 not implemented on x64: https://github.com/bytecodealliance/wasmtime/issues/4756 + #[cfg(not(target_arch = "x86_64"))] + (Opcode::Udiv, &[I128, I128], &[I128], insert_opcode), // Sdiv - // sdiv.i128 not implemented on x64: https://github.com/bytecodealliance/wasmtime/issues/4770 (Opcode::Sdiv, &[I8, I8], &[I8], insert_opcode), (Opcode::Sdiv, &[I16, I16], &[I16], insert_opcode), (Opcode::Sdiv, &[I32, I32], &[I32], insert_opcode), (Opcode::Sdiv, &[I64, I64], &[I64], insert_opcode), - // (Opcode::Sdiv, &[I128, I128], &[I128], insert_opcode), + // sdiv.i128 not implemented on x64: https://github.com/bytecodealliance/wasmtime/issues/4770 + #[cfg(not(target_arch = "x86_64"))] + (Opcode::Sdiv, &[I128, I128], &[I128], insert_opcode), // Rotr (Opcode::Rotr, &[I8, I8], &[I8], insert_opcode), (Opcode::Rotr, &[I8, I16], &[I8], insert_opcode), @@ -809,11 +828,7 @@ where let (block, args) = self.generate_target_block(builder)?; let cond = *self.u.choose(IntCC::all())?; - let bricmp_types = [ - I8, I16, I32, - I64, - // I128 - TODO: https://github.com/bytecodealliance/wasmtime/issues/4406 - ]; + let bricmp_types = [I8, I16, I32, I64, I128]; let _type = *self.u.choose(&bricmp_types[..])?; let lhs_var = self.get_variable_of_type(_type)?; From 3540b8d482ffcb6c843002ddc3f1387a697cfae6 Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Sat, 3 Sep 2022 12:03:56 +0100 Subject: [PATCH 3/4] cranelift: Disable i128 divs on aarch64 --- cranelift/fuzzgen/src/function_generator.rs | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs index a57b72ee0139..61dd03392e29 100644 --- a/cranelift/fuzzgen/src/function_generator.rs +++ b/cranelift/fuzzgen/src/function_generator.rs @@ -253,16 +253,20 @@ const OPCODE_SIGNATURES: &'static [( (Opcode::Udiv, &[I16, I16], &[I16], insert_opcode), (Opcode::Udiv, &[I32, I32], &[I32], insert_opcode), (Opcode::Udiv, &[I64, I64], &[I64], insert_opcode), - // udiv.i128 not implemented on x64: https://github.com/bytecodealliance/wasmtime/issues/4756 - #[cfg(not(target_arch = "x86_64"))] + // udiv.i128 not implemented in some backends: + // x64: https://github.com/bytecodealliance/wasmtime/issues/4756 + // aarch64: https://github.com/bytecodealliance/wasmtime/issues/4864 + #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))] (Opcode::Udiv, &[I128, I128], &[I128], insert_opcode), // Sdiv (Opcode::Sdiv, &[I8, I8], &[I8], insert_opcode), (Opcode::Sdiv, &[I16, I16], &[I16], insert_opcode), (Opcode::Sdiv, &[I32, I32], &[I32], insert_opcode), (Opcode::Sdiv, &[I64, I64], &[I64], insert_opcode), - // sdiv.i128 not implemented on x64: https://github.com/bytecodealliance/wasmtime/issues/4770 - #[cfg(not(target_arch = "x86_64"))] + // sdiv.i128 not implemented in some backends: + // x64: https://github.com/bytecodealliance/wasmtime/issues/4770 + // aarch64: https://github.com/bytecodealliance/wasmtime/issues/4864 + #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))] (Opcode::Sdiv, &[I128, I128], &[I128], insert_opcode), // Rotr (Opcode::Rotr, &[I8, I8], &[I8], insert_opcode), From fb1b8d0ce8c8e5e23f89763d1dcb1df799c8ac0e Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Sun, 4 Sep 2022 17:23:57 +0100 Subject: [PATCH 4/4] cranelift: Centralize IntCC selection --- cranelift/fuzzgen/src/function_generator.rs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/cranelift/fuzzgen/src/function_generator.rs b/cranelift/fuzzgen/src/function_generator.rs index 61dd03392e29..ee0e9c07f68f 100644 --- a/cranelift/fuzzgen/src/function_generator.rs +++ b/cranelift/fuzzgen/src/function_generator.rs @@ -830,10 +830,9 @@ where fn generate_bricmp(&mut self, builder: &mut FunctionBuilder) -> Result<()> { let (block, args) = self.generate_target_block(builder)?; - let cond = *self.u.choose(IntCC::all())?; - let bricmp_types = [I8, I16, I32, I64, I128]; - let _type = *self.u.choose(&bricmp_types[..])?; + let cc = *self.u.choose(IntCC::all())?; + let _type = *self.u.choose(&[I8, I16, I32, I64, I128])?; let lhs_var = self.get_variable_of_type(_type)?; let lhs_val = builder.use_var(lhs_var); @@ -843,7 +842,7 @@ where builder .ins() - .br_icmp(cond, lhs_val, rhs_val, block, &args[..]); + .br_icmp(cc, lhs_val, rhs_val, block, &args[..]); // After bricmp's we must generate a jump self.generate_jump(builder)?;