{"payload":{"header_redesign_enabled":false,"results":[{"id":"166282012","archived":false,"color":"#b2b7f8","followers":4,"has_funding_file":false,"hl_name":"billswartz7/utd-SystemVerilog","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":166282012,"name":"utd-SystemVerilog","owner_id":30846759,"owner_login":"billswartz7","updated_at":"2019-06-22T22:34:12.713Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":74,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Abillswartz7%252Futd-SystemVerilog%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/billswartz7/utd-SystemVerilog/star":{"post":"8LNgxU3puxfgoXaGF94xRB4VbJkJj8UQM3cBBvk2LEtVAGSRTcq0Dl4YScCyEcKSWxcvaOhoOKYHDQd79zXVDg"},"/billswartz7/utd-SystemVerilog/unstar":{"post":"oViAMuaT2_1Il09DvIb0bfOZM3Qc4NGaDPdeT2NEEigfeMFndsFT4Q8SprtrwyaUH5SeXeO49M5qzH4gsitHUA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"ssNAY4vxIpfcVoW6IFhd-ynb_dw-8fY6-msW_D5uMcRduFmlcCe59h57jz-8DMyU9ef29uv1I0FoZaXw2Lrr-g"}}},"title":"Repository search results"}