{"payload":{"header_redesign_enabled":false,"results":[{"id":"84682669","archived":false,"color":"#adb2cb","followers":12,"has_funding_file":false,"hl_name":"Yourigh/Rotary-encoder-VHDL-design","hl_trunc_description":"VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":84682669,"name":"Rotary-encoder-VHDL-design","owner_id":25552139,"owner_login":"Yourigh","updated_at":"2017-03-24T12:20:05.379Z","has_issues":true}},"sponsorable":false,"topics":["zynq","encoder","vivado","xilinx-fpga","zybo","zynq-7010","xilinx-vivado","rotary","axi"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":65,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AYourigh%252FRotary-encoder-VHDL-design%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/Yourigh/Rotary-encoder-VHDL-design/star":{"post":"VE-0vV5VV2_AyAhjP7CfoZqsPOL_uy5dbni3y_KDRAyjSUEnNiKLZWgQsKLzVfyukpp8DW449Av6NccT_rPEdA"},"/Yourigh/Rotary-encoder-VHDL-design/unstar":{"post":"Nl-0xfEO6ZVDryIV6PqQOap_R0VhAPBBOlP1EkH0Nw1Mp9JaAKoHDj0n-yBIFT2tI8BQqeZGQMPXZNNkl6eStQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"OLRtycj7TNr8HCcUR2qQB_c1JrZ6lTofjP_mRwqhnDjBzGVCWIWcpTKpEh1NFnzClWuPntYbvYTl_o90X0oT-Q"}}},"title":"Repository search results"}