{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":369765988,"defaultBranch":"master","name":"Hazard3","ownerLogin":"Wren6991","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2021-05-22T09:20:12.000Z","ownerAvatar":"https://github.com/avatars/u/1298595?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1710655270.0","currentOid":""},"activityList":{"items":[{"before":"fe4781627fb5813da61a1290cf65b67eceabc91e","after":"12d7550be5445a040a412a7acb29217bc8d16f6f","ref":"refs/heads/master","pushedAt":"2024-08-07T18:42:26.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Readme: Use non-recursive clone for riscv-gnu-toolchain. Use shallow clone for gcc14. (Save bandwidth and disk space)","shortMessageHtmlLink":"Readme: Use non-recursive clone for riscv-gnu-toolchain. Use shallow …"}},{"before":"0076b408fd19e969bffb64de0d30068d5288b165","after":"fe4781627fb5813da61a1290cf65b67eceabc91e","ref":"refs/heads/master","pushedAt":"2024-08-07T15:16:55.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Add port definitions to documentation","shortMessageHtmlLink":"Add port definitions to documentation"}},{"before":"3ef52ef2ab40f6719b664d07c3cc2e518df409be","after":"0076b408fd19e969bffb64de0d30068d5288b165","ref":"refs/heads/master","pushedAt":"2024-08-07T14:28:57.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Update readme instructions for Ubuntu 24.04","shortMessageHtmlLink":"Update readme instructions for Ubuntu 24.04"}},{"before":"dc7c7f9ae7d7ce6891e49f3c999228ee68e0bd0c","after":"3ef52ef2ab40f6719b664d07c3cc2e518df409be","ref":"refs/heads/master","pushedAt":"2024-08-07T14:27:07.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Update readme instructions for Ubuntu 24.04","shortMessageHtmlLink":"Update readme instructions for Ubuntu 24.04"}},{"before":"3c738d03566e6d866a08f04bdce1188608ac406c","after":"dc7c7f9ae7d7ce6891e49f3c999228ee68e0bd0c","ref":"refs/heads/master","pushedAt":"2024-08-07T14:23:49.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Update readme instructions for Ubuntu 24.04","shortMessageHtmlLink":"Update readme instructions for Ubuntu 24.04"}},{"before":"fbd96363c8bdd98061b68bb83449ed8fc259e5c3","after":"3c738d03566e6d866a08f04bdce1188608ac406c","ref":"refs/heads/master","pushedAt":"2024-08-01T07:45:35.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Remove redundant masking of meinext_irq field","shortMessageHtmlLink":"Remove redundant masking of meinext_irq field"}},{"before":"2665e2acc646b0ec6dece530b6dd4e76341f34fe","after":"fbd96363c8bdd98061b68bb83449ed8fc259e5c3","ref":"refs/heads/master","pushedAt":"2024-06-06T07:38:09.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"PPA: predecode stage 2 bypass mux controls at end of stage 1\n\nOR-of-ANDs style mux is used because it maps well on FPGA (particularly\nthis 3-input mux maps straight onto LUT6) and because this allows the\nzeroing of x0 to be implemented directly in the mux","shortMessageHtmlLink":"PPA: predecode stage 2 bypass mux controls at end of stage 1"}},{"before":"e3b3893cdf79b50f9c960f4dac0f934fc9bb56d2","after":"2665e2acc646b0ec6dece530b6dd4e76341f34fe","ref":"refs/heads/master","pushedAt":"2024-06-06T06:19:00.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix case overlap lint in instr_decompress. Now verilator lint clean","shortMessageHtmlLink":"Fix case overlap lint in instr_decompress. Now verilator lint clean"}},{"before":"e34aa5bb453e44978892ad176492a50ea4e3010f","after":"e3b3893cdf79b50f9c960f4dac0f934fc9bb56d2","ref":"refs/heads/master","pushedAt":"2024-06-06T05:59:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix partial case overlap lint for shared A/Zbb ALU ops","shortMessageHtmlLink":"Fix partial case overlap lint for shared A/Zbb ALU ops"}},{"before":"877c6aa5eeca2d89f8cf113081bc0fa3b7ac8260","after":"e34aa5bb453e44978892ad176492a50ea4e3010f","ref":"refs/heads/master","pushedAt":"2024-06-02T11:46:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"rvcpp: implement MPRV, and fix up CSR write tracing","shortMessageHtmlLink":"rvcpp: implement MPRV, and fix up CSR write tracing"}},{"before":"b02681467479bd3ea75e34ef7d3dbacd2a1daa53","after":"877c6aa5eeca2d89f8cf113081bc0fa3b7ac8260","ref":"refs/heads/master","pushedAt":"2024-06-02T10:22:07.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Add trace disassembly annotation script for rvcpp, and add runtests support for passing flags to tb, and running post-processing commands on test results.","shortMessageHtmlLink":"Add trace disassembly annotation script for rvcpp, and add runtests s…"}},{"before":"a9ba69f4dd8712558faf4484c196f7022d3d51b7","after":"b02681467479bd3ea75e34ef7d3dbacd2a1daa53","ref":"refs/heads/master","pushedAt":"2024-06-02T09:36:50.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"runtests: use argparse for argument parsing, and support passing a different tb executable","shortMessageHtmlLink":"runtests: use argparse for argument parsing, and support passing a di…"}},{"before":"a38981f98989275539503cb56a10048d3bec5262","after":"a9ba69f4dd8712558faf4484c196f7022d3d51b7","ref":"refs/heads/master","pushedAt":"2024-06-02T09:25:23.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Better default flags for CoreMark","shortMessageHtmlLink":"Better default flags for CoreMark"}},{"before":"cbc21729308e92b0a9bdd282d1f9835cce39b58e","after":"a38981f98989275539503cb56a10048d3bec5262","ref":"refs/heads/master","pushedAt":"2024-06-02T09:18:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Enable -Wextra for rvcpp","shortMessageHtmlLink":"Enable -Wextra for rvcpp"}},{"before":"3a747e1dde8a9c32e8b758852293e599ca36af58","after":"cbc21729308e92b0a9bdd282d1f9835cce39b58e","ref":"refs/heads/master","pushedAt":"2024-06-02T09:16:29.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"rvcpp: Add Zcb support. Also fix -Wparentheses as sometimes it does find things","shortMessageHtmlLink":"rvcpp: Add Zcb support. Also fix -Wparentheses as sometimes it does f…"}},{"before":"b883be3c20d1d2dacf8e0353768caa09be0b735d","after":"3a747e1dde8a9c32e8b758852293e599ca36af58","ref":"refs/heads/master","pushedAt":"2024-06-01T17:24:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Disable zcmp in multilib-gen-gen for now, as it is still not supported in latest binutils release","shortMessageHtmlLink":"Disable zcmp in multilib-gen-gen for now, as it is still not supporte…"}},{"before":"7430523c455656dfe5274f0d39a63894229afa05","after":"b883be3c20d1d2dacf8e0353768caa09be0b735d","ref":"refs/heads/master","pushedAt":"2024-06-01T17:01:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Update multilib-gen-gen for GCC14 extensions: Zicond, Zcmp, Zcb. Hopefully handle the Zca vs C thing gracefully.","shortMessageHtmlLink":"Update multilib-gen-gen for GCC14 extensions: Zicond, Zcmp, Zcb. Hope…"}},{"before":"96e0e6659751744bef71658b1b2c3528a5270d04","after":"7430523c455656dfe5274f0d39a63894229afa05","ref":"refs/heads/master","pushedAt":"2024-06-01T14:53:58.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Update .gitignore in riscv-tests to ignore output of debug tests","shortMessageHtmlLink":"Update .gitignore in riscv-tests to ignore output of debug tests"}},{"before":"b55e43eb16a3411fe3785c0ed9c509187e2deaed","after":"96e0e6659751744bef71658b1b2c3528a5270d04","ref":"refs/heads/master","pushedAt":"2024-06-01T14:41:40.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix fence.i being marked invalid in debug mode.\n\nThis was done because the implementation depends on the value of PC\n(it's a jump-to-next), and PC-dependent instructions are permitted to\nbe flagged as invalid in debug mode, to permit sharing of PC and the\ndpc CSR.\n\nHowever this is not valid in this case because the dependency on PC is\nan implementation detail, not an architected dependency. Instead just\nsuppress the jump in debug mode. Suppressing the jump is still required\nto avoid flushing following program buffer entries from the prefetch\nqueue during debug mode execution.\n\nFrom a functional point of view not much has changed, it just removes\nan inconsistency where fence.i appeared to be implemented in M/U mode\nbut not in debug mode. This removes a complaint from openocd when it\nexecutes a fence + fence.i after writing to memory.","shortMessageHtmlLink":"Fix fence.i being marked invalid in debug mode."}},{"before":"26f78732fdbd11a2fef69219021189b33d01603e","after":"b55e43eb16a3411fe3785c0ed9c509187e2deaed","ref":"refs/heads/master","pushedAt":"2024-06-01T14:25:50.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix event loops reported by Verilator UNOPTFLAT lints.\n\nDecode is now split into a block which depends only on the instruction\nbits, and a block which gates critical decode signals based on fetch\nfaults, invalidity etc.\n\nApply a similar transform to the gating of the uop counter update.\n\ncxxrtl performance seems unchanged after removing the event loops, but\nverilator and live-scheduled simulators should improve.","shortMessageHtmlLink":"Fix event loops reported by Verilator UNOPTFLAT lints."}},{"before":"d1f142172883de8a1e26bbd057fd46e683c1ae4d","after":"26f78732fdbd11a2fef69219021189b33d01603e","ref":"refs/heads/master","pushedAt":"2024-05-29T15:00:12.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix final two width lints in JTAG DTM. They now shrink the design by 100 LUTs instead of growing it? A mystery","shortMessageHtmlLink":"Fix final two width lints in JTAG DTM. They now shrink the design by …"}},{"before":"799f4f2c2675ab7ac62c6b4b3ad4e9186ee12040","after":"d1f142172883de8a1e26bbd057fd46e683c1ae4d","ref":"refs/heads/master","pushedAt":"2024-05-29T14:54:15.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic.","shortMessageHtmlLink":"Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl.…"}},{"before":"6da0e12bbd6956407d4f3de58dbdad8afe20cf14","after":"799f4f2c2675ab7ac62c6b4b3ad4e9186ee12040","ref":"refs/heads/master","pushedAt":"2024-05-29T14:32:56.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix verilator lint width issues in triggers, PMP, DM.\n\nThere was one genuine issue introduced by PPA changes in 78a5cb98e which\naffected instruction injection on multiple harts from the DM (indicating\nSMP debug testing needs to be part of regular automated regressions,\ninstead of semi-manual...). The rest are cosmetic.","shortMessageHtmlLink":"Fix verilator lint width issues in triggers, PMP, DM."}},{"before":"d239de803c49b90704d8414bf195e6f190e7de3f","after":"6da0e12bbd6956407d4f3de58dbdad8afe20cf14","ref":"refs/heads/master","pushedAt":"2024-05-29T13:03:24.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Merge latest riscv-tests: updates for debug + ISA tests.\n\nAdd a list of excluded tests, with reasons, to run-debug-tests.sh","shortMessageHtmlLink":"Merge latest riscv-tests: updates for debug + ISA tests."}},{"before":"8b9503c8044af429e640d5e6eb6d910fe87aae5a","after":"d239de803c49b90704d8414bf195e6f190e7de3f","ref":"refs/heads/master","pushedAt":"2024-05-27T15:55:08.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Do not rely on environment variables for any intra-project paths\n\nIt's no longer necessary to source `sourceme` before running any\nof the project Makefiles.","shortMessageHtmlLink":"Do not rely on environment variables for any intra-project paths"}},{"before":"141da555072e431cdac2f0722d570f048575d8a1","after":"8b9503c8044af429e640d5e6eb6d910fe87aae5a","ref":"refs/heads/master","pushedAt":"2024-05-27T12:13:03.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"lint: clean up a couple of width fixes in JTAG DTM, and add missing\ndefault case to DM acmd state machine. Also remove unnecessary clear\nof JTAG DR shifter on TAP reset state, which saves a bit of logic. Two\nwidth mismatches are left unfixed in the DTM (the ones with shifts)\nbecause they bizarrely increase area by 100 LUT4s when fixed.","shortMessageHtmlLink":"lint: clean up a couple of width fixes in JTAG DTM, and add missing"}},{"before":"5b31e2679075ca6e187ccd71f82b7bd6351aecce","after":"141da555072e431cdac2f0722d570f048575d8a1","ref":"refs/heads/master","pushedAt":"2024-05-27T11:26:29.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about.","shortMessageHtmlLink":"tb: remove the WIDE_TIMER_IRQ flag in favour of always having the sam…"}},{"before":"78a5cb98ea5d184c7b8bf31249ce8ac69e4abf68","after":"5b31e2679075ca6e187ccd71f82b7bd6351aecce","ref":"refs/heads/master","pushedAt":"2024-05-27T10:07:07.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression","shortMessageHtmlLink":"tb Makefile: use clang++-16 explicitly, because clang++-18 (now defau…"}},{"before":"360b034f76162beb5a0c53130b0d7562a5e04bb5","after":"78a5cb98ea5d184c7b8bf31249ce8ac69e4abf68","ref":"refs/heads/master","pushedAt":"2024-05-27T07:17:15.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"PPA: Register instruction injection output from DM, to reduce routing impact on frontend prefetch queue","shortMessageHtmlLink":"PPA: Register instruction injection output from DM, to reduce routing…"}},{"before":"ee8876f68aba180866dd7820e241d2b071e8395f","after":"360b034f76162beb5a0c53130b0d7562a5e04bb5","ref":"refs/heads/master","pushedAt":"2024-05-26T17:06:24.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Wren6991","name":"Luke Wren","path":"/Wren6991","primaryAvatarUrl":"https://github.com/avatars/u/1298595?s=80&v=4"},"commit":{"message":"Fix a few width issues identified by verilator lint. All of them gave\nwell-defined correct results already (i.e. correctly zero-extended per\nspec) but best to avoid the noise.","shortMessageHtmlLink":"Fix a few width issues identified by verilator lint. All of them gave"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAElIFvEgA","startCursor":null,"endCursor":null}},"title":"Activity · Wren6991/Hazard3"}