| counter | XoshiroBenchv1w1 | XoshiroBenchv1w128 | XoshiroBenchv2w128 | XoshiroBenchv3w256 | XoshiroBenchv4w1 | XoshiroBenchv4w128 | XoshiroBenchv4w256 | XoshiroBenchv4w512 | XoshiroBenchv4w512SoA |
|---|---|---|---|---|---|---|---|---|---|
| duration | 13798.0000 | 12092.0000 | 12114.0000 | 6385.0000 | 13834.0000 | 10028.0000 | 5131.0000 | 4324.0000 | 4547.0000 |
| task-clock | 14438.9900 | 12731.5800 | 12754.2100 | 7025.6300 | 14474.4700 | 10668.4600 | 5771.2600 | 4965.5100 | 5187.3000 |
| cycles | 54.5322 | 48.0783 | 48.1771 | 26.5410 | 54.6727 | 40.2771 | 21.8053 | 18.7482 | 19.5961 |
| stalled-cycles-backend | 0.0023 | 0.0020 | 0.0020 | 0.0013 | 0.0022 | 0.0018 | 0.0009 | 0.0008 | 0.0009 |
| stalled-cycles-frontend | 0.0007 | 0.0005 | 0.0005 | 0.0002 | 0.0005 | 0.0005 | 0.0003 | 0.0002 | 0.0002 |
| iTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| iTLB-loads | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| instructions | 250.3886 | 184.9281 | 184.9955 | 78.7205 | 250.2758 | 119.7256 | 62.4678 | 34.2182 | 60.6637 |
| branch-instructions | 17.6448 | 9.4937 | 9.4922 | 5.3921 | 17.6457 | 9.4790 | 5.3810 | 3.3587 | 3.3624 |
| branch-misses | 0.0318 | 0.0001 | 0.0001 | 0.0000 | 0.0318 | 0.0000 | 0.0045 | 0.0000 | 0.0000 |
| ex_ret_instr | 250.3218 | 184.9769 | 184.8477 | 78.7804 | 250.3380 | 119.7812 | 62.4743 | 34.2145 | 60.6174 |
| ex_ret_ops | 237.1346 | 179.9323 | 179.8879 | 77.8429 | 237.1025 | 114.7458 | 61.4747 | 37.3649 | 65.6746 |
| ex_no_retire.all | 9.5255 | 3.7646 | 3.7666 | 3.7350 | 4.4711 | 10.1085 | 6.6117 | 9.1957 | 8.0290 |
| ex_div_busy | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| sse_avx_ops_retired.all | 0.0000 | 154.7277 | 154.8263 | 60.9486 | 0.0000 | 89.5641 | 44.6078 | 24.5169 | 44.7621 |
| sse_avx_ops_retired.sse_avx_other | 0.0000 | 40.9104 | 40.9290 | 4.3276 | 0.0000 | 8.3727 | 4.3097 | 4.4268 | 2.5440 |
| sse_avx_ops_retired.sse_avx_shuffle | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 2.0100 |
| sse_avx_ops_retired.sse_avx_mov | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| sse_avx_ops_retired.sse_avx_logical | 0.0000 | 56.9334 | 56.9209 | 28.2858 | 0.0000 | 40.5846 | 20.1351 | 10.0480 | 20.1069 |
| sse_avx_ops_retired.sse_avx_shift | 0.0000 | 40.6633 | 40.6377 | 20.2114 | 0.0000 | 24.3494 | 12.0704 | 6.0287 | 12.0641 |
| packed_int_op_type.int128_mov | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| packed_int_op_type.int256_mov | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| packed_int_op_type.all | 0.0000 | 154.6995 | 154.6583 | 60.9464 | 0.0000 | 89.5081 | 44.5739 | 0.0314 | 44.7300 |
| fp_ret_sse_avx_ops.all | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.add_sub_flops | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.mult_flops | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.mac_flops | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.div_flops | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| fp_ops_retired_by_width.all | 0.0000 | 154.6090 | 154.6389 | 60.8735 | 0.0000 | 89.6012 | 44.6068 | 24.5104 | 52.7986 |
| fp_ops_retired_by_width.mmx_uops_retired | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| fp_ops_retired_by_width.pack_128_uops_retired | 0.0000 | 154.6147 | 154.6911 | 0.0316 | 0.0000 | 89.5783 | 0.0315 | 0.0314 | 0.0314 |
| fp_ops_retired_by_width.pack_256_uops_retired | 0.0000 | 0.0000 | 0.0000 | 60.8408 | 0.0000 | 0.0000 | 44.5528 | 0.0000 | 52.7427 |
| fp_ops_retired_by_width.pack_512_uops_retired | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 24.4627 | 0.0000 |
| fp_ops_retired_by_width.scalar_uops_retired | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| cache-misses | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0000 | 0.0000 | 0.0000 |
| cache-references | 0.0019 | 0.0011 | 0.0011 | 0.0007 | 0.0013 | 0.0009 | 0.0005 | 0.0004 | 0.0004 |
| all_data_cache_accesses | 19.9488 | 11.5638 | 11.5650 | 7.4776 | 20.0545 | 11.5484 | 7.4610 | 7.5580 | 5.6520 |
| L1-dcache-load-misses | 0.0010 | 0.0009 | 0.0009 | 0.0006 | 0.0010 | 0.0007 | 0.0004 | 0.0003 | 0.0002 |
| L1-dcache-loads | 18.7926 | 10.5461 | 10.5457 | 6.4602 | 18.8338 | 10.5295 | 6.4521 | 6.6849 | 4.6489 |
| L1-dcache-prefetches | 0.0007 | 0.0006 | 0.0007 | 0.0003 | 0.0007 | 0.0005 | 0.0003 | 0.0002 | 0.0001 |
| L1-icache-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| L1-icache-loads | 0.0005 | 0.0009 | 0.0010 | 0.0003 | 0.0007 | 0.0004 | 0.0002 | 0.0002 | 0.0003 |
| dTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| dTLB-loads | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |