{"payload":{"header_redesign_enabled":false,"results":[{"id":"258462543","archived":false,"color":"#e34c26","followers":0,"has_funding_file":false,"hl_name":"PhatLe15/Computer-Architecture-Design","hl_trunc_description":"Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and contro…","language":"HTML","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":258462543,"name":"Computer-Architecture-Design","owner_id":55205234,"owner_login":"PhatLe15","updated_at":"2021-02-12T22:04:19.752Z","has_issues":true}},"sponsorable":false,"topics":["performance-analysis","uart-verilog","soc","truth-tables","mips-processor","fpga-validation"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":83,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253APhatLe15%252FComputer-Architecture-Design%2B%2Blanguage%253AHTML","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/PhatLe15/Computer-Architecture-Design/star":{"post":"k-KGbEMm_Yc_lPpieg5zHRxL1arcUIiMWjDsKqG2hdLzBJo6GUV_4VdAtWtgdL0SM6PKH65XXqH504dQET3n7g"},"/PhatLe15/Computer-Architecture-Design/unstar":{"post":"pUEZITz9opZZA2Eh7WdoX0jHoQmUgf4gwhbvP1vSmzTXGt5x4taCSZ1CBgtJ5k53ep-K3oyZzKXkoSpPe1Z1oA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"BFuqxKqUfqYRkvbqDVR8F8h1PFsHH-ih3sd1-kHYslc3jfhseek1GdDYPKBHPOxqYLqwRSFljCVbdobRkhDg3w"}}},"title":"Repository search results"}