{"payload":{"header_redesign_enabled":false,"results":[{"id":"445532960","archived":false,"color":"#adb2cb","followers":47,"has_funding_file":false,"hl_name":"MJoergen/HyperRAM","hl_trunc_description":"Portable HyperRAM controller","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":445532960,"name":"HyperRAM","owner_id":1299486,"owner_login":"MJoergen","updated_at":"2024-07-22T11:08:41.558Z","has_issues":true}},"sponsorable":false,"topics":["fpga","vhdl","intel","xilinx","vivado","altera","lattice","modelsim","questasim","avalon","quartus","artix","questa","hyperram"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":66,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AMJoergen%252FHyperRAM%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/MJoergen/HyperRAM/star":{"post":"vtnOvGfnLfAw8oRM1pOVeUPcdlJiwf83Dz2LiKpI_uRqOx-yKFN0otz1O7SEGbuIw9RtvSj4QLJOj6LWAynDYw"},"/MJoergen/HyperRAM/unstar":{"post":"fPdRWW3qldyr3kqjoCTzeF097GidxzGbQ-NdZu40hnHbGozdZ6a4zAD5zwDAZL1z7eWNgRZkGcTgZTNUf5Vm7g"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"8PodB7mIcecUvFGNO0V6HJXMYVAsO6KJZj-o27vMyypG24R0ynLMWHj8bISaXQNGvCk84OQWgJ1jIuWQux7D8w"}}},"title":"Repository search results"}