{"payload":{"header_redesign_enabled":false,"results":[{"id":"437890229","archived":false,"color":"#b2b7f8","followers":81,"has_funding_file":false,"hl_name":"Fraunhofer-IMS/airisc_core_complex","hl_trunc_description":"Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.","language":"Verilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":437890229,"name":"airisc_core_complex","owner_id":85744726,"owner_login":"Fraunhofer-IMS","updated_at":"2023-11-06T17:11:54.142Z","has_issues":true}},"sponsorable":false,"topics":["security","asic","ai","fpga","embedded-systems","riscv","verilog","safety","risc-v","functional-safety","asil","smart-sensors"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":70,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AFraunhofer-IMS%252Fairisc_core_complex%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/Fraunhofer-IMS/airisc_core_complex/star":{"post":"mv5k_bBdQuhrd84qdFOy4PTCH1d80aJ1MCrPoUtjHG_a-OXNNvBpUPLXSZMZQAkdZksjyyx7Em9WiNsQdhwkxg"},"/Fraunhofer-IMS/airisc_core_complex/unstar":{"post":"CS0JGTZWZQAp5yVPWj6eIWd0MKUOk0ssPQqSJzI7YM83MN1a-SmWrU_y0SBUTC8salv1dSSLgspuiwGKpJTNCw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"SRJL13Hpep4OIk7abDnv8o3ETkeAGnnLsXJ4YVbu86dejHKbl_Pc0O-Y9CIjukkXy42cDhhBMgsyDFQxutH_bw"}}},"title":"Repository search results"}