diff --git a/src/virt.rs b/src/virt.rs
index 3d53594..a2d91e1 100644
--- a/src/virt.rs
+++ b/src/virt.rs
@@ -1,6 +1,7 @@
 //! Firmware Virtualisation
 use miralis_core::abi;
 
+use crate::arch::misa::H;
 use crate::arch::pmp::pmpcfg;
 use crate::arch::{
     mie, misa, mstatus, mtvec, parse_mpp_return_mode, satp, Arch, Architecture, Csr,
@@ -52,11 +53,17 @@ impl VirtContext {
     pub const fn new(hart_id: usize, nb_pmp: usize) -> Self {
         assert!(nb_pmp <= 64, "Too many PMP registers");
 
+        let mut misa_value: usize = 0x0;
+
+        if Plat::HAS_H_MODE {
+            misa_value |= H
+        }
+
         VirtContext {
             host_stack: 0,
             regs: [0; 32],
             csr: VirtCsr {
-                misa: 0,
+                misa: misa_value,
                 mie: 0,
                 mip: 0,
                 mtvec: 0,
@@ -1157,9 +1164,8 @@ impl HwRegisterContextSetter<Csr> for VirtContext {
                 // misa shows the extensions available : we cannot have more than possible in hardware
                 let arch_misa: usize = Arch::read_csr(Csr::Misa);
                 // Update misa to a legal value
-                self.csr.misa = (value & arch_misa & misa::MISA_CHANGE_FILTER & !misa::DISABLED)
-                    | misa::MXL
-                    | misa::H;
+                self.csr.misa =
+                    (value & arch_misa & misa::MISA_CHANGE_FILTER & !misa::DISABLED) | misa::MXL;
             }
             Csr::Mie => self.csr.mie = value & hw.interrupts & mie::MIE_WRITE_FILTER,
             Csr::Mip => {